Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Just radeon and nouveau, mostly regressions fixers, and a couple of
radeon register checker fixes."
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/nouveau: fix acpi edid retrieval
drm/nvc0/disp: fix regression in vblank semaphore release
drm/nv40/mpeg: fix context handling
drm/nv40/graph: fix typo in type names
drm/nv41/vm: fix typo in type name
drm/radeon/si: add some missing regs to the VM reg checker
drm/radeon/cayman: add some missing regs to the VM reg checker
drm/radeon/dce3: switch back to old pll allocation order for discrete
+57
-36
+12
-8
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+12
-8
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
···
22
22
* Authors: Ben Skeggs
23
23
*/
24
24
25
+
#include <subdev/bar.h>
26
+
25
27
#include <engine/software.h>
26
28
#include <engine/disp.h>
27
29
···
39
37
static void
40
38
nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
41
39
{
40
+
struct nouveau_bar *bar = nouveau_bar(priv);
42
41
struct nouveau_disp *disp = &priv->base;
43
42
struct nouveau_software_chan *chan, *temp;
44
43
unsigned long flags;
···
49
46
if (chan->vblank.crtc != crtc)
50
47
continue;
51
48
52
-
nv_wr32(priv, 0x001704, chan->vblank.channel);
53
-
nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
54
-
55
49
if (nv_device(priv)->chipset == 0x50) {
50
+
nv_wr32(priv, 0x001704, chan->vblank.channel);
51
+
nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
52
+
bar->flush(bar);
56
53
nv_wr32(priv, 0x001570, chan->vblank.offset);
57
54
nv_wr32(priv, 0x001574, chan->vblank.value);
58
55
} else {
59
-
if (nv_device(priv)->chipset >= 0xc0) {
60
-
nv_wr32(priv, 0x06000c,
61
-
upper_32_bits(chan->vblank.offset));
62
-
}
63
-
nv_wr32(priv, 0x060010, chan->vblank.offset);
56
+
nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
57
+
bar->flush(bar);
58
+
nv_wr32(priv, 0x06000c,
59
+
upper_32_bits(chan->vblank.offset));
60
+
nv_wr32(priv, 0x060010,
61
+
lower_32_bits(chan->vblank.offset));
64
62
nv_wr32(priv, 0x060014, chan->vblank.value);
65
63
}
66
64
+2
-2
drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
+2
-2
drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
···
156
156
static int
157
157
nv40_graph_context_fini(struct nouveau_object *object, bool suspend)
158
158
{
159
-
struct nv04_graph_priv *priv = (void *)object->engine;
160
-
struct nv04_graph_chan *chan = (void *)object;
159
+
struct nv40_graph_priv *priv = (void *)object->engine;
160
+
struct nv40_graph_chan *chan = (void *)object;
161
161
u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4;
162
162
int ret = 0;
163
163
+1
-1
drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
+1
-1
drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
+1
-1
drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
+1
-1
drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_connector.c
+1
-1
drivers/gpu/drm/nouveau/nouveau_connector.c
···
355
355
* valid - it's not (rh#613284)
356
356
*/
357
357
if (nv_encoder->dcb->lvdsconf.use_acpi_for_edid) {
358
-
if (!(nv_connector->edid = nouveau_acpi_edid(dev, connector))) {
358
+
if ((nv_connector->edid = nouveau_acpi_edid(dev, connector))) {
359
359
status = connector_status_connected;
360
360
goto out;
361
361
}
+31
-23
drivers/gpu/drm/radeon/atombios_crtc.c
+31
-23
drivers/gpu/drm/radeon/atombios_crtc.c
···
1696
1696
return ATOM_PPLL2;
1697
1697
DRM_ERROR("unable to allocate a PPLL\n");
1698
1698
return ATOM_PPLL_INVALID;
1699
-
} else {
1700
-
if (ASIC_IS_AVIVO(rdev)) {
1701
-
/* in DP mode, the DP ref clock can come from either PPLL
1702
-
* depending on the asic:
1703
-
* DCE3: PPLL1 or PPLL2
1704
-
*/
1705
-
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1706
-
/* use the same PPLL for all DP monitors */
1707
-
pll = radeon_get_shared_dp_ppll(crtc);
1708
-
if (pll != ATOM_PPLL_INVALID)
1709
-
return pll;
1710
-
} else {
1711
-
/* use the same PPLL for all monitors with the same clock */
1712
-
pll = radeon_get_shared_nondp_ppll(crtc);
1713
-
if (pll != ATOM_PPLL_INVALID)
1714
-
return pll;
1715
-
}
1716
-
/* all other cases */
1717
-
pll_in_use = radeon_get_pll_use_mask(crtc);
1699
+
} else if (ASIC_IS_AVIVO(rdev)) {
1700
+
/* in DP mode, the DP ref clock can come from either PPLL
1701
+
* depending on the asic:
1702
+
* DCE3: PPLL1 or PPLL2
1703
+
*/
1704
+
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1705
+
/* use the same PPLL for all DP monitors */
1706
+
pll = radeon_get_shared_dp_ppll(crtc);
1707
+
if (pll != ATOM_PPLL_INVALID)
1708
+
return pll;
1709
+
} else {
1710
+
/* use the same PPLL for all monitors with the same clock */
1711
+
pll = radeon_get_shared_nondp_ppll(crtc);
1712
+
if (pll != ATOM_PPLL_INVALID)
1713
+
return pll;
1714
+
}
1715
+
/* all other cases */
1716
+
pll_in_use = radeon_get_pll_use_mask(crtc);
1717
+
/* the order shouldn't matter here, but we probably
1718
+
* need this until we have atomic modeset
1719
+
*/
1720
+
if (rdev->flags & RADEON_IS_IGP) {
1718
1721
if (!(pll_in_use & (1 << ATOM_PPLL1)))
1719
1722
return ATOM_PPLL1;
1720
1723
if (!(pll_in_use & (1 << ATOM_PPLL2)))
1721
1724
return ATOM_PPLL2;
1722
-
DRM_ERROR("unable to allocate a PPLL\n");
1723
-
return ATOM_PPLL_INVALID;
1724
1725
} else {
1725
-
/* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1726
-
return radeon_crtc->crtc_id;
1726
+
if (!(pll_in_use & (1 << ATOM_PPLL2)))
1727
+
return ATOM_PPLL2;
1728
+
if (!(pll_in_use & (1 << ATOM_PPLL1)))
1729
+
return ATOM_PPLL1;
1727
1730
}
1731
+
DRM_ERROR("unable to allocate a PPLL\n");
1732
+
return ATOM_PPLL_INVALID;
1733
+
} else {
1734
+
/* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1735
+
return radeon_crtc->crtc_id;
1728
1736
}
1729
1737
}
1730
1738
+3
drivers/gpu/drm/radeon/evergreen_cs.c
+3
drivers/gpu/drm/radeon/evergreen_cs.c
+4
drivers/gpu/drm/radeon/evergreend.h
+4
drivers/gpu/drm/radeon/evergreend.h
+1
drivers/gpu/drm/radeon/si.c
+1
drivers/gpu/drm/radeon/si.c