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PCI: dwc: Advertise dynamic inbound mapping support

The DesignWare EP core has supported updating the inbound iATU mapping
for an already configured BAR (i.e. allowing pci_epc_set_bar() to be
called again without a prior pci_epc_clear_bar()) since
commit 4284c88fff0e ("PCI: designware-ep: Allow pci_epc_set_bar() update
inbound map address").

Now that this capability is exposed via the dynamic_inbound_mapping EPC
feature bit, set it for DWC-based EP glue drivers using a common
initializer macro to avoid duplicating the same flag in each driver.

Note that pci-layerscape-ep.c is untouched. It currently constructs the
feature struct dynamically in ls_pcie_ep_init(). Once converted to a
static feature definition, it will use DWC_EPC_COMMON_FEATURES as well.

Signed-off-by: Koichiro Den <den@valinux.co.jp>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260124145012.2794108-4-den@valinux.co.jp

authored by

Koichiro Den and committed by
Manivannan Sadhasivam c0f1506f 31fb9540

+19
+1
drivers/pci/controller/dwc/pci-dra7xx.c
··· 424 424 } 425 425 426 426 static const struct pci_epc_features dra7xx_pcie_epc_features = { 427 + DWC_EPC_COMMON_FEATURES, 427 428 .linkup_notifier = true, 428 429 .msi_capable = true, 429 430 };
+3
drivers/pci/controller/dwc/pci-imx6.c
··· 1388 1388 } 1389 1389 1390 1390 static const struct pci_epc_features imx8m_pcie_epc_features = { 1391 + DWC_EPC_COMMON_FEATURES, 1391 1392 .msi_capable = true, 1392 1393 .bar[BAR_1] = { .type = BAR_RESERVED, }, 1393 1394 .bar[BAR_3] = { .type = BAR_RESERVED, }, ··· 1398 1397 }; 1399 1398 1400 1399 static const struct pci_epc_features imx8q_pcie_epc_features = { 1400 + DWC_EPC_COMMON_FEATURES, 1401 1401 .msi_capable = true, 1402 1402 .bar[BAR_1] = { .type = BAR_RESERVED, }, 1403 1403 .bar[BAR_3] = { .type = BAR_RESERVED, }, ··· 1419 1417 * BAR5 | Enable | 32-bit | 64 KB | Programmable Size 1420 1418 */ 1421 1419 static const struct pci_epc_features imx95_pcie_epc_features = { 1420 + DWC_EPC_COMMON_FEATURES, 1422 1421 .msi_capable = true, 1423 1422 .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, 1424 1423 .align = SZ_4K,
+1
drivers/pci/controller/dwc/pci-keystone.c
··· 930 930 } 931 931 932 932 static const struct pci_epc_features ks_pcie_am654_epc_features = { 933 + DWC_EPC_COMMON_FEATURES, 933 934 .msi_capable = true, 934 935 .msix_capable = true, 935 936 .bar[BAR_0] = { .type = BAR_RESERVED, },
+1
drivers/pci/controller/dwc/pcie-artpec6.c
··· 370 370 } 371 371 372 372 static const struct pci_epc_features artpec6_pcie_epc_features = { 373 + DWC_EPC_COMMON_FEATURES, 373 374 .msi_capable = true, 374 375 }; 375 376
+1
drivers/pci/controller/dwc/pcie-designware-plat.c
··· 61 61 } 62 62 63 63 static const struct pci_epc_features dw_plat_pcie_epc_features = { 64 + DWC_EPC_COMMON_FEATURES, 64 65 .msi_capable = true, 65 66 .msix_capable = true, 66 67 };
+3
drivers/pci/controller/dwc/pcie-designware.h
··· 305 305 /* Default eDMA LLP memory size */ 306 306 #define DMA_LLP_MEM_SIZE PAGE_SIZE 307 307 308 + /* Common struct pci_epc_feature bits among DWC EP glue drivers */ 309 + #define DWC_EPC_COMMON_FEATURES .dynamic_inbound_mapping = true 310 + 308 311 struct dw_pcie; 309 312 struct dw_pcie_rp; 310 313 struct dw_pcie_ep;
+2
drivers/pci/controller/dwc/pcie-dw-rockchip.c
··· 382 382 } 383 383 384 384 static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = { 385 + DWC_EPC_COMMON_FEATURES, 385 386 .linkup_notifier = true, 386 387 .msi_capable = true, 387 388 .msix_capable = true, ··· 403 402 * BARs) would be overwritten, resulting in (all other BARs) no longer working. 404 403 */ 405 404 static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = { 405 + DWC_EPC_COMMON_FEATURES, 406 406 .linkup_notifier = true, 407 407 .msi_capable = true, 408 408 .msix_capable = true,
+1
drivers/pci/controller/dwc/pcie-keembay.c
··· 309 309 } 310 310 311 311 static const struct pci_epc_features keembay_pcie_epc_features = { 312 + DWC_EPC_COMMON_FEATURES, 312 313 .msi_capable = true, 313 314 .msix_capable = true, 314 315 .bar[BAR_0] = { .only_64bit = true, },
+1
drivers/pci/controller/dwc/pcie-qcom-ep.c
··· 820 820 } 821 821 822 822 static const struct pci_epc_features qcom_pcie_epc_features = { 823 + DWC_EPC_COMMON_FEATURES, 823 824 .linkup_notifier = true, 824 825 .msi_capable = true, 825 826 .align = SZ_4K,
+1
drivers/pci/controller/dwc/pcie-rcar-gen4.c
··· 420 420 } 421 421 422 422 static const struct pci_epc_features rcar_gen4_pcie_epc_features = { 423 + DWC_EPC_COMMON_FEATURES, 423 424 .msi_capable = true, 424 425 .bar[BAR_1] = { .type = BAR_RESERVED, }, 425 426 .bar[BAR_3] = { .type = BAR_RESERVED, },
+1
drivers/pci/controller/dwc/pcie-stm32-ep.c
··· 70 70 } 71 71 72 72 static const struct pci_epc_features stm32_pcie_epc_features = { 73 + DWC_EPC_COMMON_FEATURES, 73 74 .msi_capable = true, 74 75 .align = SZ_64K, 75 76 };
+1
drivers/pci/controller/dwc/pcie-tegra194.c
··· 1988 1988 } 1989 1989 1990 1990 static const struct pci_epc_features tegra_pcie_epc_features = { 1991 + DWC_EPC_COMMON_FEATURES, 1991 1992 .linkup_notifier = true, 1992 1993 .msi_capable = true, 1993 1994 .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
+2
drivers/pci/controller/dwc/pcie-uniphier-ep.c
··· 420 420 .init = uniphier_pcie_pro5_init_ep, 421 421 .wait = NULL, 422 422 .features = { 423 + DWC_EPC_COMMON_FEATURES, 423 424 .linkup_notifier = false, 424 425 .msi_capable = true, 425 426 .msix_capable = false, ··· 439 438 .init = uniphier_pcie_nx1_init_ep, 440 439 .wait = uniphier_pcie_nx1_wait_ep, 441 440 .features = { 441 + DWC_EPC_COMMON_FEATURES, 442 442 .linkup_notifier = false, 443 443 .msi_capable = true, 444 444 .msix_capable = false,