tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: add the sched_score to amdgpu_ring_init

Allow separate ring to share the same scheduler score.

No functional change.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Christian König and committed by
Alex Deucher c107171b 7df4ceb6

+93 -99
+26 -24
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
··· 439 439 * Helper function for amdgpu_fence_driver_init(). 440 440 */ 441 441 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 442 - unsigned num_hw_submission) 442 + unsigned num_hw_submission, 443 + atomic_t *sched_score) 443 444 { 444 445 struct amdgpu_device *adev = ring->adev; 445 446 long timeout; ··· 468 467 return -ENOMEM; 469 468 470 469 /* No need to setup the GPU scheduler for rings that don't need it */ 471 - if (!ring->no_scheduler) { 472 - switch (ring->funcs->type) { 473 - case AMDGPU_RING_TYPE_GFX: 474 - timeout = adev->gfx_timeout; 475 - break; 476 - case AMDGPU_RING_TYPE_COMPUTE: 477 - timeout = adev->compute_timeout; 478 - break; 479 - case AMDGPU_RING_TYPE_SDMA: 480 - timeout = adev->sdma_timeout; 481 - break; 482 - default: 483 - timeout = adev->video_timeout; 484 - break; 485 - } 470 + if (ring->no_scheduler) 471 + return 0; 486 472 487 - r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, 488 - num_hw_submission, amdgpu_job_hang_limit, 489 - timeout, NULL, ring->name); 490 - if (r) { 491 - DRM_ERROR("Failed to create scheduler on ring %s.\n", 492 - ring->name); 493 - return r; 494 - } 473 + switch (ring->funcs->type) { 474 + case AMDGPU_RING_TYPE_GFX: 475 + timeout = adev->gfx_timeout; 476 + break; 477 + case AMDGPU_RING_TYPE_COMPUTE: 478 + timeout = adev->compute_timeout; 479 + break; 480 + case AMDGPU_RING_TYPE_SDMA: 481 + timeout = adev->sdma_timeout; 482 + break; 483 + default: 484 + timeout = adev->video_timeout; 485 + break; 486 + } 487 + 488 + r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, 489 + num_hw_submission, amdgpu_job_hang_limit, 490 + timeout, sched_score, ring->name); 491 + if (r) { 492 + DRM_ERROR("Failed to create scheduler on ring %s.\n", 493 + ring->name); 494 + return r; 495 495 } 496 496 497 497 return 0;
+2 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
··· 310 310 ring->eop_gpu_addr = kiq->eop_gpu_addr; 311 311 ring->no_scheduler = true; 312 312 sprintf(ring->name, "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue); 313 - r = amdgpu_ring_init(adev, ring, 1024, 314 - irq, AMDGPU_CP_KIQ_IRQ_DRIVER0, 315 - AMDGPU_RING_PRIO_DEFAULT); 313 + r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0, 314 + AMDGPU_RING_PRIO_DEFAULT, NULL); 316 315 if (r) 317 316 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); 318 317
+4 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
··· 164 164 */ 165 165 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 166 166 unsigned int max_dw, struct amdgpu_irq_src *irq_src, 167 - unsigned int irq_type, unsigned int hw_prio) 167 + unsigned int irq_type, unsigned int hw_prio, 168 + atomic_t *sched_score) 168 169 { 169 170 int r; 170 171 int sched_hw_submission = amdgpu_sched_hw_submission; ··· 190 189 ring->adev = adev; 191 190 ring->idx = adev->num_rings++; 192 191 adev->rings[ring->idx] = ring; 193 - r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission); 192 + r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission, 193 + sched_score); 194 194 if (r) 195 195 return r; 196 196 }
+4 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
··· 111 111 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 112 112 113 113 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 114 - unsigned num_hw_submission); 114 + unsigned num_hw_submission, 115 + atomic_t *sched_score); 115 116 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 116 117 struct amdgpu_irq_src *irq_src, 117 118 unsigned irq_type); ··· 283 282 void amdgpu_ring_undo(struct amdgpu_ring *ring); 284 283 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 285 284 unsigned int ring_size, struct amdgpu_irq_src *irq_src, 286 - unsigned int irq_type, unsigned int prio); 285 + unsigned int irq_type, unsigned int prio, 286 + atomic_t *sched_score); 287 287 void amdgpu_ring_fini(struct amdgpu_ring *ring); 288 288 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 289 289 uint32_t reg0, uint32_t val0,
+2 -3
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
··· 984 984 sprintf(ring->name, "sdma%d", i); 985 985 r = amdgpu_ring_init(adev, ring, 1024, 986 986 &adev->sdma.trap_irq, 987 - (i == 0) ? 988 - AMDGPU_SDMA_IRQ_INSTANCE0 : 987 + (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 989 988 AMDGPU_SDMA_IRQ_INSTANCE1, 990 - AMDGPU_RING_PRIO_DEFAULT); 989 + AMDGPU_RING_PRIO_DEFAULT, NULL); 991 990 if (r) 992 991 return r; 993 992 }
+4 -5
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 4458 4458 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4459 4459 4460 4460 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4461 - r = amdgpu_ring_init(adev, ring, 1024, 4462 - &adev->gfx.eop_irq, irq_type, 4463 - AMDGPU_RING_PRIO_DEFAULT); 4461 + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4462 + AMDGPU_RING_PRIO_DEFAULT, NULL); 4464 4463 if (r) 4465 4464 return r; 4466 4465 return 0; ··· 4493 4494 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4494 4495 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4495 4496 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4496 - r = amdgpu_ring_init(adev, ring, 1024, 4497 - &adev->gfx.eop_irq, irq_type, hw_prio); 4497 + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4498 + hw_prio, NULL); 4498 4499 if (r) 4499 4500 return r; 4500 4501
+2 -2
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
··· 3114 3114 r = amdgpu_ring_init(adev, ring, 1024, 3115 3115 &adev->gfx.eop_irq, 3116 3116 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 3117 - AMDGPU_RING_PRIO_DEFAULT); 3117 + AMDGPU_RING_PRIO_DEFAULT, NULL); 3118 3118 if (r) 3119 3119 return r; 3120 3120 } ··· 3137 3137 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3138 3138 r = amdgpu_ring_init(adev, ring, 1024, 3139 3139 &adev->gfx.eop_irq, irq_type, 3140 - AMDGPU_RING_PRIO_DEFAULT); 3140 + AMDGPU_RING_PRIO_DEFAULT, NULL); 3141 3141 if (r) 3142 3142 return r; 3143 3143 }
+2 -2
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
··· 4438 4438 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4439 4439 r = amdgpu_ring_init(adev, ring, 1024, 4440 4440 &adev->gfx.eop_irq, irq_type, 4441 - AMDGPU_RING_PRIO_DEFAULT); 4441 + AMDGPU_RING_PRIO_DEFAULT, NULL); 4442 4442 if (r) 4443 4443 return r; 4444 4444 ··· 4512 4512 r = amdgpu_ring_init(adev, ring, 1024, 4513 4513 &adev->gfx.eop_irq, 4514 4514 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 4515 - AMDGPU_RING_PRIO_DEFAULT); 4515 + AMDGPU_RING_PRIO_DEFAULT, NULL); 4516 4516 if (r) 4517 4517 return r; 4518 4518 }
+3 -3
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
··· 1927 1927 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1928 1928 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT; 1929 1929 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1930 - r = amdgpu_ring_init(adev, ring, 1024, 1931 - &adev->gfx.eop_irq, irq_type, hw_prio); 1930 + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1931 + hw_prio, NULL); 1932 1932 if (r) 1933 1933 return r; 1934 1934 ··· 2033 2033 2034 2034 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2035 2035 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 2036 - AMDGPU_RING_PRIO_DEFAULT); 2036 + AMDGPU_RING_PRIO_DEFAULT, NULL); 2037 2037 if (r) 2038 2038 return r; 2039 2039 }
+4 -5
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 2286 2286 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 2287 2287 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 2288 2288 /* type-2 packets are deprecated on MEC, use type-3 instead */ 2289 - return amdgpu_ring_init(adev, ring, 1024, 2290 - &adev->gfx.eop_irq, irq_type, hw_prio); 2289 + return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 2290 + hw_prio, NULL); 2291 2291 } 2292 2292 2293 2293 static int gfx_v9_0_sw_init(void *handle) ··· 2376 2376 sprintf(ring->name, "gfx_%d", i); 2377 2377 ring->use_doorbell = true; 2378 2378 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2379 - r = amdgpu_ring_init(adev, ring, 1024, 2380 - &adev->gfx.eop_irq, 2379 + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, 2381 2380 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, 2382 - AMDGPU_RING_PRIO_DEFAULT); 2381 + AMDGPU_RING_PRIO_DEFAULT, NULL); 2383 2382 if (r) 2384 2383 return r; 2385 2384 }
+1 -1
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
··· 487 487 ring = &adev->jpeg.inst->ring_dec; 488 488 sprintf(ring->name, "jpeg_dec"); 489 489 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 490 - 0, AMDGPU_RING_PRIO_DEFAULT); 490 + 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 491 491 if (r) 492 492 return r; 493 493
+1 -1
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
··· 108 108 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 109 109 sprintf(ring->name, "jpeg_dec"); 110 110 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 111 - 0, AMDGPU_RING_PRIO_DEFAULT); 111 + 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 112 112 if (r) 113 113 return r; 114 114
+1 -1
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
··· 115 115 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i; 116 116 sprintf(ring->name, "jpeg_dec_%d", i); 117 117 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq, 118 - 0, AMDGPU_RING_PRIO_DEFAULT); 118 + 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 119 119 if (r) 120 120 return r; 121 121
+1 -1
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
··· 94 94 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; 95 95 sprintf(ring->name, "jpeg_dec"); 96 96 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, 97 - AMDGPU_RING_PRIO_DEFAULT); 97 + AMDGPU_RING_PRIO_DEFAULT, NULL); 98 98 if (r) 99 99 return r; 100 100
+2 -1
drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
··· 848 848 ring->no_scheduler = true; 849 849 sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 850 850 851 - return amdgpu_ring_init(adev, ring, 1024, NULL, 0, AMDGPU_RING_PRIO_DEFAULT); 851 + return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 852 + AMDGPU_RING_PRIO_DEFAULT, NULL); 852 853 } 853 854 854 855 static int mes_v10_1_mqd_sw_init(struct amdgpu_device *adev)
+3 -5
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
··· 876 876 ring->ring_obj = NULL; 877 877 ring->use_doorbell = false; 878 878 sprintf(ring->name, "sdma%d", i); 879 - r = amdgpu_ring_init(adev, ring, 1024, 880 - &adev->sdma.trap_irq, 881 - (i == 0) ? 882 - AMDGPU_SDMA_IRQ_INSTANCE0 : 879 + r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 880 + (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 883 881 AMDGPU_SDMA_IRQ_INSTANCE1, 884 - AMDGPU_RING_PRIO_DEFAULT); 882 + AMDGPU_RING_PRIO_DEFAULT, NULL); 885 883 if (r) 886 884 return r; 887 885 }
+3 -5
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
··· 1160 1160 } 1161 1161 1162 1162 sprintf(ring->name, "sdma%d", i); 1163 - r = amdgpu_ring_init(adev, ring, 1024, 1164 - &adev->sdma.trap_irq, 1165 - (i == 0) ? 1166 - AMDGPU_SDMA_IRQ_INSTANCE0 : 1163 + r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1164 + (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 1167 1165 AMDGPU_SDMA_IRQ_INSTANCE1, 1168 - AMDGPU_RING_PRIO_DEFAULT); 1166 + AMDGPU_RING_PRIO_DEFAULT, NULL); 1169 1167 if (r) 1170 1168 return r; 1171 1169 }
+2 -2
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
··· 1968 1968 sprintf(ring->name, "sdma%d", i); 1969 1969 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1970 1970 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1971 - AMDGPU_RING_PRIO_DEFAULT); 1971 + AMDGPU_RING_PRIO_DEFAULT, NULL); 1972 1972 if (r) 1973 1973 return r; 1974 1974 ··· 1987 1987 r = amdgpu_ring_init(adev, ring, 1024, 1988 1988 &adev->sdma.trap_irq, 1989 1989 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1990 - AMDGPU_RING_PRIO_DEFAULT); 1990 + AMDGPU_RING_PRIO_DEFAULT, NULL); 1991 1991 if (r) 1992 1992 return r; 1993 1993 }
+3 -5
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
··· 1273 1273 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset 1274 1274 1275 1275 sprintf(ring->name, "sdma%d", i); 1276 - r = amdgpu_ring_init(adev, ring, 1024, 1277 - &adev->sdma.trap_irq, 1278 - (i == 0) ? 1279 - AMDGPU_SDMA_IRQ_INSTANCE0 : 1276 + r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1277 + (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 1280 1278 AMDGPU_SDMA_IRQ_INSTANCE1, 1281 - AMDGPU_RING_PRIO_DEFAULT); 1279 + AMDGPU_RING_PRIO_DEFAULT, NULL); 1282 1280 if (r) 1283 1281 return r; 1284 1282 }
+2 -3
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
··· 1283 1283 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1284 1284 1285 1285 sprintf(ring->name, "sdma%d", i); 1286 - r = amdgpu_ring_init(adev, ring, 1024, 1287 - &adev->sdma.trap_irq, 1286 + r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1288 1287 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1289 - AMDGPU_RING_PRIO_DEFAULT); 1288 + AMDGPU_RING_PRIO_DEFAULT, NULL); 1290 1289 if (r) 1291 1290 return r; 1292 1291 }
+2 -3
drivers/gpu/drm/amd/amdgpu/si_dma.c
··· 507 507 sprintf(ring->name, "sdma%d", i); 508 508 r = amdgpu_ring_init(adev, ring, 1024, 509 509 &adev->sdma.trap_irq, 510 - (i == 0) ? 511 - AMDGPU_SDMA_IRQ_INSTANCE0 : 510 + (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 512 511 AMDGPU_SDMA_IRQ_INSTANCE1, 513 - AMDGPU_RING_PRIO_DEFAULT); 512 + AMDGPU_RING_PRIO_DEFAULT, NULL); 514 513 if (r) 515 514 return r; 516 515 }
+1 -1
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
··· 562 562 ring = &adev->uvd.inst->ring; 563 563 sprintf(ring->name, "uvd"); 564 564 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, 565 - AMDGPU_RING_PRIO_DEFAULT); 565 + AMDGPU_RING_PRIO_DEFAULT, NULL); 566 566 if (r) 567 567 return r; 568 568
+1 -1
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
··· 119 119 ring = &adev->uvd.inst->ring; 120 120 sprintf(ring->name, "uvd"); 121 121 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, 122 - AMDGPU_RING_PRIO_DEFAULT); 122 + AMDGPU_RING_PRIO_DEFAULT, NULL); 123 123 if (r) 124 124 return r; 125 125
+1 -1
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
··· 117 117 ring = &adev->uvd.inst->ring; 118 118 sprintf(ring->name, "uvd"); 119 119 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, 120 - AMDGPU_RING_PRIO_DEFAULT); 120 + AMDGPU_RING_PRIO_DEFAULT, NULL); 121 121 if (r) 122 122 return r; 123 123
+2 -2
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
··· 420 420 ring = &adev->uvd.inst->ring; 421 421 sprintf(ring->name, "uvd"); 422 422 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, 423 - AMDGPU_RING_PRIO_DEFAULT); 423 + AMDGPU_RING_PRIO_DEFAULT, NULL); 424 424 if (r) 425 425 return r; 426 426 ··· 434 434 sprintf(ring->name, "uvd_enc%d", i); 435 435 r = amdgpu_ring_init(adev, ring, 512, 436 436 &adev->uvd.inst->irq, 0, 437 - AMDGPU_RING_PRIO_DEFAULT); 437 + AMDGPU_RING_PRIO_DEFAULT, NULL); 438 438 if (r) 439 439 return r; 440 440 }
+2 -2
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
··· 454 454 sprintf(ring->name, "uvd_%d", ring->me); 455 455 r = amdgpu_ring_init(adev, ring, 512, 456 456 &adev->uvd.inst[j].irq, 0, 457 - AMDGPU_RING_PRIO_DEFAULT); 457 + AMDGPU_RING_PRIO_DEFAULT, NULL); 458 458 if (r) 459 459 return r; 460 460 } ··· 475 475 } 476 476 r = amdgpu_ring_init(adev, ring, 512, 477 477 &adev->uvd.inst[j].irq, 0, 478 - AMDGPU_RING_PRIO_DEFAULT); 478 + AMDGPU_RING_PRIO_DEFAULT, NULL); 479 479 if (r) 480 480 return r; 481 481 }
+2 -3
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
··· 433 433 for (i = 0; i < adev->vce.num_rings; i++) { 434 434 ring = &adev->vce.ring[i]; 435 435 sprintf(ring->name, "vce%d", i); 436 - r = amdgpu_ring_init(adev, ring, 512, 437 - &adev->vce.irq, 0, 438 - AMDGPU_RING_PRIO_DEFAULT); 436 + r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0, 437 + AMDGPU_RING_PRIO_DEFAULT, NULL); 439 438 if (r) 440 439 return r; 441 440 }
+1 -1
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
··· 443 443 ring = &adev->vce.ring[i]; 444 444 sprintf(ring->name, "vce%d", i); 445 445 r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0, 446 - AMDGPU_RING_PRIO_DEFAULT); 446 + AMDGPU_RING_PRIO_DEFAULT, NULL); 447 447 if (r) 448 448 return r; 449 449 }
+1 -1
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
··· 477 477 ring->doorbell_index = adev->doorbell_index.uvd_vce.vce_ring2_3 * 2 + 1; 478 478 } 479 479 r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0, 480 - AMDGPU_RING_PRIO_DEFAULT); 480 + AMDGPU_RING_PRIO_DEFAULT, NULL); 481 481 if (r) 482 482 return r; 483 483 }
+2 -2
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
··· 129 129 ring = &adev->vcn.inst->ring_dec; 130 130 sprintf(ring->name, "vcn_dec"); 131 131 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 132 - AMDGPU_RING_PRIO_DEFAULT); 132 + AMDGPU_RING_PRIO_DEFAULT, NULL); 133 133 if (r) 134 134 return r; 135 135 ··· 148 148 ring = &adev->vcn.inst->ring_enc[i]; 149 149 sprintf(ring->name, "vcn_enc%d", i); 150 150 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 151 - AMDGPU_RING_PRIO_DEFAULT); 151 + AMDGPU_RING_PRIO_DEFAULT, NULL); 152 152 if (r) 153 153 return r; 154 154 }
+2 -2
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
··· 136 136 137 137 sprintf(ring->name, "vcn_dec"); 138 138 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 139 - AMDGPU_RING_PRIO_DEFAULT); 139 + AMDGPU_RING_PRIO_DEFAULT, NULL); 140 140 if (r) 141 141 return r; 142 142 ··· 167 167 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i; 168 168 sprintf(ring->name, "vcn_enc%d", i); 169 169 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 170 - AMDGPU_RING_PRIO_DEFAULT); 170 + AMDGPU_RING_PRIO_DEFAULT, NULL); 171 171 if (r) 172 172 return r; 173 173 }
+2 -2
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
··· 189 189 (amdgpu_sriov_vf(adev) ? 2*j : 8*j); 190 190 sprintf(ring->name, "vcn_dec_%d", j); 191 191 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 192 - 0, AMDGPU_RING_PRIO_DEFAULT); 192 + 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 193 193 if (r) 194 194 return r; 195 195 ··· 203 203 sprintf(ring->name, "vcn_enc_%d.%d", j, i); 204 204 r = amdgpu_ring_init(adev, ring, 512, 205 205 &adev->vcn.inst[j].irq, 0, 206 - AMDGPU_RING_PRIO_DEFAULT); 206 + AMDGPU_RING_PRIO_DEFAULT, NULL); 207 207 if (r) 208 208 return r; 209 209 }
+2 -2
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
··· 209 209 ring->no_scheduler = true; 210 210 sprintf(ring->name, "vcn_dec_%d", i); 211 211 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 212 - AMDGPU_RING_PRIO_DEFAULT); 212 + AMDGPU_RING_PRIO_DEFAULT, NULL); 213 213 if (r) 214 214 return r; 215 215 ··· 231 231 ring->no_scheduler = true; 232 232 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 233 233 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 234 - AMDGPU_RING_PRIO_DEFAULT); 234 + AMDGPU_RING_PRIO_DEFAULT, NULL); 235 235 if (r) 236 236 return r; 237 237 }