-1

Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml

reviewed

··· 7 7 title: Ceva AHCI SATA Controller 8 8 9 9 maintainers: 10 10 - - Mubin Sayyed <mubin.sayyed@amd.com> 11 10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> 12 11 13 12 description: |

+17 -1

Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml

reviewed

··· 111 111 unevaluatedProperties: false 112 112 113 113 port@1: 114 114 - $ref: /schemas/graph.yaml#/properties/port 114 114 + $ref: /schemas/graph.yaml#/$defs/port-base 115 115 + unevaluatedProperties: false 115 116 description: 116 117 DSI output port node to the panel or the next bridge 117 118 in the chain 119 119 + 120 120 + properties: 121 121 + endpoint: 122 122 + $ref: /schemas/media/video-interfaces.yaml# 123 123 + unevaluatedProperties: false 124 124 + 125 125 + properties: 126 126 + data-lanes: 127 127 + description: array of physical DSI data lane indexes. 128 128 + minItems: 1 129 129 + items: 130 130 + - const: 1 131 131 + - const: 2 132 132 + - const: 3 133 133 + - const: 4 118 134 119 135 required: 120 136 - port@0

-1

Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml

reviewed

··· 12 12 PS_MODE). Every pin can be configured as input/output. 13 13 14 14 maintainers: 15 15 - - Mubin Sayyed <mubin.sayyed@amd.com> 16 15 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> 17 16 18 17 properties:

+1

Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml

reviewed

··· 19 19 - fsl,imx8mp-irqsteer 20 20 - fsl,imx8qm-irqsteer 21 21 - fsl,imx8qxp-irqsteer 22 22 + - fsl,imx94-irqsteer 22 23 - const: fsl,imx-irqsteer 23 24 24 25 reg:

-9

Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml

reviewed

··· 9 9 maintainers: 10 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11 11 12 12 - select: 13 13 - properties: 14 14 - compatible: 15 15 - contains: 16 16 - const: renesas,tpu 17 17 - required: 18 18 - - compatible 19 19 - - '#pwm-cells' 20 20 - 21 12 properties: 22 13 compatible: 23 14 items:

-1

Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml

reviewed

··· 7 7 title: Zynq UltraScale+ MPSoC and Versal reset 8 8 9 9 maintainers: 10 10 - - Mubin Sayyed <mubin.sayyed@amd.com> 11 10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> 12 11 13 12 description: |

+1 -1

Documentation/devicetree/bindings/soc/fsl/fsl,ls1028a-reset.yaml

reviewed

··· 7 7 title: Freescale Layerscape Reset Registers Module 8 8 9 9 maintainers: 10 10 - - Frank Li 10 10 + - Frank Li <Frank.Li@nxp.com> 11 11 12 12 description: 13 13 Reset Module includes chip reset, service processor control and Reset Control

+8 -3

Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml

reviewed

··· 18 18 19 19 properties: 20 20 compatible: 21 21 - enum: 22 22 - - nxp,imx95-sysctr-timer 23 23 - - nxp,sysctr-timer 21 21 + oneOf: 22 22 + - enum: 23 23 + - nxp,imx95-sysctr-timer 24 24 + - nxp,sysctr-timer 25 25 + - items: 26 26 + - enum: 27 27 + - nxp,imx94-sysctr-timer 28 28 + - const: nxp,imx95-sysctr-timer 24 29 25 30 reg: 26 31 maxItems: 1

-56

Documentation/devicetree/bindings/timer/renesas,tpu.yaml

reviewed

··· 1 1 - # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 - %YAML 1.2 3 3 - --- 4 4 - $id: http://devicetree.org/schemas/timer/renesas,tpu.yaml# 5 5 - $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 - 7 7 - title: Renesas H8/300 Timer Pulse Unit 8 8 - 9 9 - maintainers: 10 10 - - Yoshinori Sato <ysato@users.sourceforge.jp> 11 11 - 12 12 - description: 13 13 - The TPU is a 16bit timer/counter with configurable clock inputs and 14 14 - programmable compare match. 15 15 - This implementation supports only cascade mode. 16 16 - 17 17 - select: 18 18 - properties: 19 19 - compatible: 20 20 - contains: 21 21 - const: renesas,tpu 22 22 - '#pwm-cells': false 23 23 - required: 24 24 - - compatible 25 25 - 26 26 - properties: 27 27 - compatible: 28 28 - const: renesas,tpu 29 29 - 30 30 - reg: 31 31 - items: 32 32 - - description: First channel 33 33 - - description: Second channel 34 34 - 35 35 - clocks: 36 36 - maxItems: 1 37 37 - 38 38 - clock-names: 39 39 - const: fck 40 40 - 41 41 - required: 42 42 - - compatible 43 43 - - reg 44 44 - - clocks 45 45 - - clock-names 46 46 - 47 47 - additionalProperties: false 48 48 - 49 49 - examples: 50 50 - - | 51 51 - tpu: tpu@ffffe0 { 52 52 - compatible = "renesas,tpu"; 53 53 - reg = <0xffffe0 16>, <0xfffff0 12>; 54 54 - clocks = <&pclk>; 55 55 - clock-names = "fck"; 56 56 - };

-1

Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml

reviewed

··· 7 7 title: Xilinx SuperSpeed DWC3 USB SoC controller 8 8 9 9 maintainers: 10 10 - - Mubin Sayyed <mubin.sayyed@amd.com> 11 10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> 12 11 13 12 properties:

-1

Documentation/devicetree/bindings/usb/microchip,usb5744.yaml

reviewed

··· 17 17 18 18 maintainers: 19 19 - Michal Simek <michal.simek@amd.com> 20 20 - - Mubin Sayyed <mubin.sayyed@amd.com> 21 20 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> 22 21 23 22 properties:

-1

Documentation/devicetree/bindings/usb/xlnx,usb2.yaml

reviewed

··· 7 7 title: Xilinx udc controller 8 8 9 9 maintainers: 10 10 - - Mubin Sayyed <mubin.sayyed@amd.com> 11 10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> 12 11 13 12 properties: