+1 -1

arch/powerpc/include/asm/hugetlb.h

reviewed

··· 15 15 16 16 extern bool hugetlb_disabled; 17 17 18 18 - void hugetlbpage_init_default(void); 18 18 + void __init hugetlbpage_init_default(void); 19 19 20 20 int slice_is_hugepage_only_range(struct mm_struct *mm, unsigned long addr, 21 21 unsigned long len);

+1 -1

arch/powerpc/include/asm/mmu_context.h

reviewed

··· 71 71 } 72 72 73 73 extern int hash__alloc_context_id(void); 74 74 - extern void hash__reserve_context_id(int id); 74 74 + void __init hash__reserve_context_id(int id); 75 75 extern void __destroy_context(int context_id); 76 76 static inline void mmu_context_init(void) { } 77 77

+1 -1

arch/powerpc/mm/book3s32/mmu.c

reviewed

··· 76 76 return 0; 77 77 } 78 78 79 79 - static int find_free_bat(void) 79 79 + static int __init find_free_bat(void) 80 80 { 81 81 int b; 82 82 int n = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;

+3 -3

arch/powerpc/mm/book3s64/hash_utils.c

reviewed

··· 662 662 } 663 663 #endif /* CONFIG_HUGETLB_PAGE */ 664 664 665 665 - static void mmu_psize_set_default_penc(void) 665 665 + static void __init mmu_psize_set_default_penc(void) 666 666 { 667 667 int bpsize, apsize; 668 668 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++) ··· 672 672 673 673 #ifdef CONFIG_PPC_64K_PAGES 674 674 675 675 - static bool might_have_hea(void) 675 675 + static bool __init might_have_hea(void) 676 676 { 677 677 /* 678 678 * The HEA ethernet adapter requires awareness of the ··· 743 743 * low-order N bits as the encoding for the 2^(12+N) byte page size 744 744 * (if it exists). 745 745 */ 746 746 - static void init_hpte_page_sizes(void) 746 746 + static void __init init_hpte_page_sizes(void) 747 747 { 748 748 long int ap, bp; 749 749 long int shift, penc;

+1 -1

arch/powerpc/mm/book3s64/hugetlbpage.c

reviewed

··· 150 150 set_huge_pte_at(vma->vm_mm, addr, ptep, pte); 151 151 } 152 152 153 153 - void hugetlbpage_init_default(void) 153 153 + void __init hugetlbpage_init_default(void) 154 154 { 155 155 /* Set default large page size. Currently, we pick 16M or 1M 156 156 * depending on what is available

+1 -1

arch/powerpc/mm/book3s64/mmu_context.c

reviewed

··· 32 32 } 33 33 34 34 #ifdef CONFIG_PPC_64S_HASH_MMU 35 35 - void hash__reserve_context_id(int id) 35 35 + void __init hash__reserve_context_id(int id) 36 36 { 37 37 int result = ida_alloc_range(&mmu_context_ida, id, id, GFP_KERNEL); 38 38

+1 -1

arch/powerpc/mm/book3s64/pkeys.c

reviewed

··· 66 66 return 1; 67 67 } 68 68 69 69 - static int scan_pkey_feature(void) 69 69 + static int __init scan_pkey_feature(void) 70 70 { 71 71 int ret; 72 72 int pkeys_total = 0;

+2 -2

arch/powerpc/mm/book3s64/radix_pgtable.c

reviewed

··· 499 499 return 1; 500 500 } 501 501 502 502 - static unsigned long radix_memory_block_size(void) 502 502 + static unsigned long __init radix_memory_block_size(void) 503 503 { 504 504 unsigned long mem_block_size = MIN_MEMORY_BLOCK_SIZE; 505 505 ··· 517 517 518 518 #else /* CONFIG_MEMORY_HOTPLUG */ 519 519 520 520 - static unsigned long radix_memory_block_size(void) 520 520 + static unsigned long __init radix_memory_block_size(void) 521 521 { 522 522 return 1UL * 1024 * 1024 * 1024; 523 523 }

+2 -2

arch/powerpc/mm/nohash/44x.c

reviewed

··· 38 38 39 39 unsigned long tlb_47x_boltmap[1024/8]; 40 40 41 41 - static void ppc44x_update_tlb_hwater(void) 41 41 + static void __init ppc44x_update_tlb_hwater(void) 42 42 { 43 43 /* The TLB miss handlers hard codes the watermark in a cmpli 44 44 * instruction to improve performances rather than loading it ··· 122 122 /* 123 123 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU 124 124 */ 125 125 - static void ppc47x_pin_tlb(unsigned int virt, unsigned int phys) 125 125 + static void __init ppc47x_pin_tlb(unsigned int virt, unsigned int phys) 126 126 { 127 127 unsigned int rA; 128 128 int bolted;

+1 -1

arch/powerpc/mm/nohash/fsl_book3e.c

reviewed

··· 259 259 flush_instruction_cache(); 260 260 } 261 261 262 262 - static unsigned long tlbcam_sz(int idx) 262 262 + static unsigned long __init tlbcam_sz(int idx) 263 263 { 264 264 return tlbcam_addrs[idx].limit - tlbcam_addrs[idx].start + 1; 265 265 }

+2 -2

arch/powerpc/mm/nohash/tlb.c

reviewed

··· 432 432 } 433 433 } 434 434 435 435 - static void setup_page_sizes(void) 435 435 + static void __init setup_page_sizes(void) 436 436 { 437 437 unsigned int tlb0cfg; 438 438 unsigned int tlb0ps; ··· 570 570 } 571 571 } 572 572 573 573 - static void setup_mmu_htw(void) 573 573 + static void __init setup_mmu_htw(void) 574 574 { 575 575 /* 576 576 * If we want to use HW tablewalk, enable it by patching the TLB miss

+3 -3

arch/powerpc/mm/numa.c

reviewed

··· 134 134 return 0; 135 135 } 136 136 137 137 - static void reset_numa_cpu_lookup_table(void) 137 137 + static void __init reset_numa_cpu_lookup_table(void) 138 138 { 139 139 unsigned int cpu; 140 140 ··· 372 372 * ibm,numa-lookup-index-table= {N, domainid1, domainid2, ..... domainidN} 373 373 * ibm,numa-distance-table = { N, 1, 2, 4, 5, 1, 6, .... N elements} 374 374 */ 375 375 - static void initialize_form2_numa_distance_lookup_table(void) 375 375 + static void __init initialize_form2_numa_distance_lookup_table(void) 376 376 { 377 377 int i, j; 378 378 struct device_node *root; ··· 581 581 return 0; 582 582 } 583 583 584 584 - static int get_nid_and_numa_distance(struct drmem_lmb *lmb) 584 584 + static int __init get_nid_and_numa_distance(struct drmem_lmb *lmb) 585 585 { 586 586 struct assoc_arrays aa = { .arrays = NULL }; 587 587 int default_nid = NUMA_NO_NODE;

+1 -1

arch/powerpc/mm/ptdump/ptdump.c

reviewed

··· 315 315 316 316 DEFINE_SHOW_ATTRIBUTE(ptdump); 317 317 318 318 - static void build_pgtable_complete_mask(void) 318 318 + static void __init build_pgtable_complete_mask(void) 319 319 { 320 320 unsigned int i, j; 321 321