Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
firmware: zynqmp: Move crypto API's to separate file
For better maintainability move crypto related API's to
new zynqmp-crypto.c file.
Signed-off-by: Harsh Jain <h.jain@amd.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
authored by
Harsh Jain
and committed by
Herbert Xu
c15291e2
1ccc00d7
+89
-63
+1
-1
drivers/firmware/xilinx/Makefile
+1
-1
drivers/firmware/xilinx/Makefile
+59
drivers/firmware/xilinx/zynqmp-crypto.c
+59
drivers/firmware/xilinx/zynqmp-crypto.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Firmware layer for XilSecure APIs.
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*
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* Copyright (C) 2014-2022 Xilinx, Inc.
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* Copyright (C) 2022-2025 Advanced Micro Devices, Inc.
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*/
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#include <linux/firmware/xlnx-zynqmp.h>
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#include <linux/module.h>
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/**
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* zynqmp_pm_aes_engine - Access AES hardware to encrypt/decrypt the data using
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* AES-GCM core.
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* @address: Address of the AesParams structure.
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* @out: Returned output value
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*
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* Return: Returns status, either success or error code.
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*/
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int zynqmp_pm_aes_engine(const u64 address, u32 *out)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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+
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if (!out)
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return -EINVAL;
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ret = zynqmp_pm_invoke_fn(PM_SECURE_AES, ret_payload, 2, upper_32_bits(address),
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lower_32_bits(address));
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*out = ret_payload[1];
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return ret;
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);
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/**
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* zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash
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* @address: Address of the data/ Address of output buffer where
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* hash should be stored.
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* @size: Size of the data.
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* @flags:
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* BIT(0) - for initializing csudma driver and SHA3(Here address
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* and size inputs can be NULL).
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* BIT(1) - to call Sha3_Update API which can be called multiple
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* times when data is not contiguous.
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* BIT(2) - to get final hash of the whole updated data.
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* Hash will be overwritten at provided address with
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* 48 bytes.
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*
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* Return: Returns status, either success or error code.
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*/
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int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags)
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{
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u32 lower_addr = lower_32_bits(address);
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u32 upper_addr = upper_32_bits(address);
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return zynqmp_pm_invoke_fn(PM_SECURE_SHA, NULL, 4, upper_addr, lower_addr, size, flags);
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash);
-49
drivers/firmware/xilinx/zynqmp.c
-49
drivers/firmware/xilinx/zynqmp.c
···
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EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi);
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/**
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* zynqmp_pm_aes_engine - Access AES hardware to encrypt/decrypt the data using
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* AES-GCM core.
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* @address: Address of the AesParams structure.
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* @out: Returned output value
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*
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* Return: Returns status, either success or error code.
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*/
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int zynqmp_pm_aes_engine(const u64 address, u32 *out)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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if (!out)
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return -EINVAL;
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ret = zynqmp_pm_invoke_fn(PM_SECURE_AES, ret_payload, 2, upper_32_bits(address),
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lower_32_bits(address));
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*out = ret_payload[1];
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return ret;
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);
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-
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/**
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* zynqmp_pm_efuse_access - Provides access to efuse memory.
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* @address: Address of the efuse params structure
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* @out: Returned output value
···
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return ret;
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_efuse_access);
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-
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/**
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* zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash
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* @address: Address of the data/ Address of output buffer where
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* hash should be stored.
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* @size: Size of the data.
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* @flags:
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* BIT(0) - for initializing csudma driver and SHA3(Here address
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* and size inputs can be NULL).
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* BIT(1) - to call Sha3_Update API which can be called multiple
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* times when data is not contiguous.
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* BIT(2) - to get final hash of the whole updated data.
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* Hash will be overwritten at provided address with
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* 48 bytes.
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*
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* Return: Returns status, either success or error code.
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*/
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int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags)
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{
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u32 lower_addr = lower_32_bits(address);
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u32 upper_addr = upper_32_bits(address);
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return zynqmp_pm_invoke_fn(PM_SECURE_SHA, NULL, 4, upper_addr, lower_addr, size, flags);
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash);
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/**
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* zynqmp_pm_register_notifier() - PM API for register a subsystem
+28
include/linux/firmware/xlnx-zynqmp-crypto.h
+28
include/linux/firmware/xlnx-zynqmp-crypto.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Firmware layer for XilSECURE APIs.
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*
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* Copyright (C) 2014-2022 Xilinx, Inc.
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* Copyright (C) 2022-2025 Advanced Micro Devices, Inc.
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*/
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#ifndef __FIRMWARE_XLNX_ZYNQMP_CRYPTO_H__
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#define __FIRMWARE_XLNX_ZYNQMP_CRYPTO_H__
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#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
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int zynqmp_pm_aes_engine(const u64 address, u32 *out);
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int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
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#else
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static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
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const u32 flags)
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{
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return -ENODEV;
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}
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#endif
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#endif /* __FIRMWARE_XLNX_ZYNQMP_CRYPTO_H__ */
+1
-13
include/linux/firmware/xlnx-zynqmp.h
+1
-13
include/linux/firmware/xlnx-zynqmp.h
···
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#include <linux/err.h>
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#include <linux/firmware/xlnx-zynqmp-ufs.h>
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#include <linux/firmware/xlnx-zynqmp-crypto.h>
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#define ZYNQMP_PM_VERSION_MAJOR 1
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#define ZYNQMP_PM_VERSION_MINOR 0
···
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int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
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const u32 qos,
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const enum zynqmp_pm_request_ack ack);
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int zynqmp_pm_aes_engine(const u64 address, u32 *out);
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int zynqmp_pm_efuse_access(const u64 address, u32 *out);
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int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
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int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
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int zynqmp_pm_fpga_get_status(u32 *value);
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int zynqmp_pm_fpga_get_config_status(u32 *value);
···
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return -ENODEV;
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}
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static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
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const u32 flags)
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{
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return -ENODEV;
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}