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dt-bindings: phy: Add Apple Type-C PHY

Apple's Type-C PHY (ATCPHY) is a PHY for USB 2.0, USB 3.x,
USB4/Thunderbolt, and DisplayPort connectivity found in Apple Silicon
SoCs.

The PHY handles muxing between these different protocols and also provides
the reset controller for the attached dwc3 USB controller.

Reviewed-by: Neal Gompa <neal@gompa.dev>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Sven Peter <sven@kernel.org>
Link: https://patch.msgid.link/20251214-b4-atcphy-v3-2-ba82b20e9459@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Sven Peter and committed by
Vinod Koul
c1538b87 a722de30

+223
+222
Documentation/devicetree/bindings/phy/apple,atcphy.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/phy/apple,atcphy.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Apple Type-C PHY (ATCPHY) 8 + 9 + maintainers: 10 + - Sven Peter <sven@kernel.org> 11 + 12 + description: > 13 + The Apple Type-C PHY (ATCPHY) is a combined PHY for USB 2.0, USB 3.x, 14 + USB4/Thunderbolt, and DisplayPort connectivity via Type-C ports found in 15 + Apple Silicon SoCs. 16 + 17 + The PHY handles muxing between these different protocols and also provides the 18 + reset controller for the attached DWC3 USB controller. 19 + 20 + It is designed for USB4 operation and does not handle individual differential 21 + pairs as distinct DisplayPort lanes. Any reference to lane in this binding 22 + hence refers to two differential pairs (RX and TX) as used in USB terminology. 23 + 24 + In order to correctly setup these lanes for the various modes calibration 25 + values copied from Apple's firmware and converted to the format described 26 + below by our bootloader m1n1 are required. Without these only USB2 operation 27 + is possible. 28 + 29 + allOf: 30 + - $ref: /schemas/usb/usb-switch.yaml# 31 + 32 + $defs: 33 + apple,tunable: 34 + $ref: /schemas/types.yaml#/definitions/uint32-matrix 35 + items: 36 + items: 37 + - description: Register offset 38 + - description: Mask to be applied to the register value 39 + - description: Bits to be set after applying the mask 40 + description: > 41 + List of (register offset, mask, value) tuples copied from Apple's Device 42 + Tree by our bootloader m1n1 and used to configure the PHY. These values 43 + even vary for a single product/device and likely contain calibration 44 + values determined by Apple at manufacturing time. 45 + Unless otherwise noted these tunables are always applied to the core 46 + register region. 47 + 48 + properties: 49 + compatible: 50 + oneOf: 51 + - items: 52 + - enum: 53 + - apple,t6000-atcphy 54 + - apple,t6020-atcphy 55 + - apple,t8112-atcphy 56 + - const: apple,t8103-atcphy 57 + - const: apple,t8103-atcphy 58 + 59 + reg: 60 + items: 61 + - description: Common controls for all PHYs (USB2/3/4, DisplayPort, TBT) 62 + - description: DisplayPort Alternate Mode PHY specific controls 63 + - description: Type-C PHY AXI to Apple Fabric interconnect controls 64 + - description: USB2 PHY specific controls 65 + - description: USB3 PIPE interface controls 66 + 67 + reg-names: 68 + items: 69 + - const: core 70 + - const: lpdptx 71 + - const: axi2af 72 + - const: usb2phy 73 + - const: pipehandler 74 + 75 + "#phy-cells": 76 + const: 1 77 + 78 + "#reset-cells": 79 + const: 0 80 + 81 + mode-switch: true 82 + orientation-switch: true 83 + 84 + power-domains: 85 + maxItems: 1 86 + 87 + ports: 88 + $ref: /schemas/graph.yaml#/properties/ports 89 + properties: 90 + port@0: 91 + $ref: /schemas/graph.yaml#/properties/port 92 + description: Outgoing connection to the SS port of the Type-C connector. 93 + 94 + port@1: 95 + $ref: /schemas/graph.yaml#/properties/port 96 + description: Incoming endpoint from the USB3 controller. 97 + 98 + port@2: 99 + $ref: /schemas/graph.yaml#/properties/port 100 + description: Incoming endpoint from the DisplayPort controller. 101 + 102 + port@3: 103 + $ref: /schemas/graph.yaml#/properties/port 104 + description: Incoming endpoint from the USB4/Thunderbolt controller. 105 + 106 + apple,tunable-common-a: 107 + $ref: "#/$defs/apple,tunable" 108 + description: > 109 + Common tunables required for all modes, applied before tunable-axi2af. 110 + 111 + apple,tunable-axi2af: 112 + $ref: "#/$defs/apple,tunable" 113 + description: > 114 + AXI to Apple Fabric tunables, required for all modes. Unlike all other 115 + tunables these are applied to the axi2af region. 116 + 117 + apple,tunable-common-b: 118 + $ref: "#/$defs/apple,tunable" 119 + description: > 120 + Common tunables required for all modes, applied after tunable-axi2af. 121 + 122 + apple,tunable-lane0-usb: 123 + $ref: "#/$defs/apple,tunable" 124 + description: USB3 tunables for lane 0. 125 + 126 + apple,tunable-lane1-usb: 127 + $ref: "#/$defs/apple,tunable" 128 + description: USB3 tunables for lane 1. 129 + 130 + apple,tunable-lane0-cio: 131 + $ref: "#/$defs/apple,tunable" 132 + description: USB4/Thunderbolt ("Converged IO") tunables for lane 0. 133 + 134 + apple,tunable-lane1-cio: 135 + $ref: "#/$defs/apple,tunable" 136 + description: USB4/Thunderbolt ("Converged IO") tunables for lane 1. 137 + 138 + apple,tunable-lane0-dp: 139 + $ref: "#/$defs/apple,tunable" 140 + description: > 141 + DisplayPort tunables for lane 0. 142 + 143 + Note that lane here refers to a USB RX and TX pair re-used for DisplayPort 144 + and not to an individual DisplayPort differential lane. 145 + 146 + apple,tunable-lane1-dp: 147 + $ref: "#/$defs/apple,tunable" 148 + description: > 149 + DisplayPort tunables for lane 1. 150 + 151 + Note that lane here refers to a USB RX and TX pair re-used for DisplayPort 152 + and not to an individual DisplayPort differential lane. 153 + 154 + required: 155 + - compatible 156 + - reg 157 + - reg-names 158 + - "#phy-cells" 159 + - "#reset-cells" 160 + - orientation-switch 161 + - mode-switch 162 + - power-domains 163 + - ports 164 + 165 + additionalProperties: false 166 + 167 + examples: 168 + - | 169 + phy@83000000 { 170 + compatible = "apple,t8103-atcphy"; 171 + reg = <0x83000000 0x4c000>, 172 + <0x83050000 0x8000>, 173 + <0x80000000 0x4000>, 174 + <0x82a90000 0x4000>, 175 + <0x82a84000 0x4000>; 176 + reg-names = "core", "lpdptx", "axi2af", "usb2phy", 177 + "pipehandler"; 178 + 179 + #phy-cells = <1>; 180 + #reset-cells = <0>; 181 + 182 + orientation-switch; 183 + mode-switch; 184 + power-domains = <&ps_atc0_usb>; 185 + 186 + ports { 187 + #address-cells = <1>; 188 + #size-cells = <0>; 189 + 190 + port@0 { 191 + reg = <0>; 192 + 193 + endpoint { 194 + remote-endpoint = <&typec_connector_ss>; 195 + }; 196 + }; 197 + 198 + port@1 { 199 + reg = <1>; 200 + 201 + endpoint { 202 + remote-endpoint = <&dwc3_ss_out>; 203 + }; 204 + }; 205 + 206 + port@2 { 207 + reg = <2>; 208 + 209 + endpoint { 210 + remote-endpoint = <&dcp_dp_out>; 211 + }; 212 + }; 213 + 214 + port@3 { 215 + reg = <3>; 216 + 217 + endpoint { 218 + remote-endpoint = <&acio_tbt_out>; 219 + }; 220 + }; 221 + }; 222 + };
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MAINTAINERS
··· 2471 2471 F: Documentation/devicetree/bindings/nvmem/apple,efuses.yaml 2472 2472 F: Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml 2473 2473 F: Documentation/devicetree/bindings/pci/apple,pcie.yaml 2474 + F: Documentation/devicetree/bindings/phy/apple,atcphy.yaml 2474 2475 F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml 2475 2476 F: Documentation/devicetree/bindings/power/apple* 2476 2477 F: Documentation/devicetree/bindings/power/reset/apple,smc-reboot.yaml