tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"Exynos, i915 and msm fixes and one core fix.

exynos:
hdmi power off and mixer issues

msm:
iommu, build fixes,

i915:
regression races and warning fixes"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (22 commits)
drm/i915: vlv_prepare_pll is only needed in case of non DSI interfaces
drm: fix NULL pointer access by wrong ioctl
drm/exynos: enable vsync interrupt while waiting for vblank
drm/exynos: soft reset mixer before reconfigure after power-on
drm/exynos: allow multiple layer updates per vsync for mixer
drm/i915: Hold the table lock whilst walking the file's idr and counting the objects in debugfs
drm/i915: BDW: Adding Reserved PCI IDs.
drm/i915: Only mark the ctx as initialised after a SET_CONTEXT operation
drm/exynos: stop mixer before gating clocks during poweroff
drm/exynos: set power state variable after enabling clocks and power
drm/exynos: disable unused windows on apply
drm/exynos: Fix de-registration ordering
drm/exynos: change zero to NULL for sparse
drm/exynos: dpi: Fix NULL pointer dereference with legacy bindings
drm/exynos: hdmi: fix power order issue
drm/i915: default to having backlight if VBT not available
drm/i915: cache hw power well enabled state
drm/msm: fix IOMMU cleanup for -EPROBE_DEFER
drm/msm: use PAGE_ALIGNED instead of IS_ALIGNED(PAGE_SIZE)
drm/msm/hdmi: set hdp clock rate before prepare_enable
...

Linus Torvalds c163b524 3493860c

+169 -70
+2 -1
drivers/gpu/drm/drm_drv.c
··· 419 419 retcode = -EFAULT; 420 420 goto err_i1; 421 421 } 422 - } else 422 + } else if (cmd & IOC_OUT) { 423 423 memset(kdata, 0, usize); 424 + } 424 425 425 426 if (ioctl->flags & DRM_UNLOCKED) 426 427 retcode = func(dev, kdata, file_priv);
+1 -1
drivers/gpu/drm/exynos/exynos_drm_dpi.c
··· 40 40 { 41 41 struct exynos_dpi *ctx = connector_to_dpi(connector); 42 42 43 - if (!ctx->panel->connector) 43 + if (ctx->panel && !ctx->panel->connector) 44 44 drm_panel_attach(ctx->panel, &ctx->connector); 45 45 46 46 return connector_status_connected;
+4 -4
drivers/gpu/drm/exynos/exynos_drm_drv.c
··· 765 765 766 766 return 0; 767 767 768 - err_unregister_pd: 769 - platform_device_unregister(exynos_drm_pdev); 770 - 771 768 err_remove_vidi: 772 769 #ifdef CONFIG_DRM_EXYNOS_VIDI 773 770 exynos_drm_remove_vidi(); 771 + 772 + err_unregister_pd: 774 773 #endif 774 + platform_device_unregister(exynos_drm_pdev); 775 775 776 776 return ret; 777 777 } 778 778 779 779 static void exynos_drm_exit(void) 780 780 { 781 + platform_driver_unregister(&exynos_drm_platform_driver); 781 782 #ifdef CONFIG_DRM_EXYNOS_VIDI 782 783 exynos_drm_remove_vidi(); 783 784 #endif 784 785 platform_device_unregister(exynos_drm_pdev); 785 - platform_driver_unregister(&exynos_drm_platform_driver); 786 786 } 787 787 788 788 module_init(exynos_drm_init);
+1 -1
drivers/gpu/drm/exynos/exynos_drm_drv.h
··· 343 343 int exynos_dpi_remove(struct device *dev); 344 344 #else 345 345 static inline struct exynos_drm_display * 346 - exynos_dpi_probe(struct device *dev) { return 0; } 346 + exynos_dpi_probe(struct device *dev) { return NULL; } 347 347 static inline int exynos_dpi_remove(struct device *dev) { return 0; } 348 348 #endif 349 349
+2
drivers/gpu/drm/exynos/exynos_drm_fimd.c
··· 741 741 win_data = &ctx->win_data[i]; 742 742 if (win_data->enabled) 743 743 fimd_win_commit(mgr, i); 744 + else 745 + fimd_win_disable(mgr, i); 744 746 } 745 747 746 748 fimd_commit(mgr);
+19
drivers/gpu/drm/exynos/exynos_hdmi.c
··· 2090 2090 2091 2091 static void hdmi_dpms(struct exynos_drm_display *display, int mode) 2092 2092 { 2093 + struct hdmi_context *hdata = display->ctx; 2094 + struct drm_encoder *encoder = hdata->encoder; 2095 + struct drm_crtc *crtc = encoder->crtc; 2096 + struct drm_crtc_helper_funcs *funcs = NULL; 2097 + 2093 2098 DRM_DEBUG_KMS("mode %d\n", mode); 2094 2099 2095 2100 switch (mode) { ··· 2104 2099 case DRM_MODE_DPMS_STANDBY: 2105 2100 case DRM_MODE_DPMS_SUSPEND: 2106 2101 case DRM_MODE_DPMS_OFF: 2102 + /* 2103 + * The SFRs of VP and Mixer are updated by Vertical Sync of 2104 + * Timing generator which is a part of HDMI so the sequence 2105 + * to disable TV Subsystem should be as following, 2106 + * VP -> Mixer -> HDMI 2107 + * 2108 + * Below codes will try to disable Mixer and VP(if used) 2109 + * prior to disabling HDMI. 2110 + */ 2111 + if (crtc) 2112 + funcs = crtc->helper_private; 2113 + if (funcs && funcs->dpms) 2114 + (*funcs->dpms)(crtc, mode); 2115 + 2107 2116 hdmi_poweroff(display); 2108 2117 break; 2109 2118 default:
+35 -15
drivers/gpu/drm/exynos/exynos_mixer.c
··· 377 377 mixer_regs_dump(ctx); 378 378 } 379 379 380 + static void mixer_stop(struct mixer_context *ctx) 381 + { 382 + struct mixer_resources *res = &ctx->mixer_res; 383 + int timeout = 20; 384 + 385 + mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN); 386 + 387 + while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) && 388 + --timeout) 389 + usleep_range(10000, 12000); 390 + 391 + mixer_regs_dump(ctx); 392 + } 393 + 380 394 static void vp_video_buffer(struct mixer_context *ctx, int win) 381 395 { 382 396 struct mixer_resources *res = &ctx->mixer_res; ··· 511 497 static void mixer_layer_update(struct mixer_context *ctx) 512 498 { 513 499 struct mixer_resources *res = &ctx->mixer_res; 514 - u32 val; 515 500 516 - val = mixer_reg_read(res, MXR_CFG); 517 - 518 - /* allow one update per vsync only */ 519 - if (!(val & MXR_CFG_LAYER_UPDATE_COUNT_MASK)) 520 - mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE); 501 + mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE); 521 502 } 522 503 523 504 static void mixer_graph_buffer(struct mixer_context *ctx, int win) ··· 1019 1010 } 1020 1011 mutex_unlock(&mixer_ctx->mixer_mutex); 1021 1012 1013 + drm_vblank_get(mgr->crtc->dev, mixer_ctx->pipe); 1014 + 1022 1015 atomic_set(&mixer_ctx->wait_vsync_event, 1); 1023 1016 1024 1017 /* ··· 1031 1020 !atomic_read(&mixer_ctx->wait_vsync_event), 1032 1021 HZ/20)) 1033 1022 DRM_DEBUG_KMS("vblank wait timed out.\n"); 1023 + 1024 + drm_vblank_put(mgr->crtc->dev, mixer_ctx->pipe); 1034 1025 } 1035 1026 1036 1027 static void mixer_window_suspend(struct exynos_drm_manager *mgr) ··· 1074 1061 mutex_unlock(&ctx->mixer_mutex); 1075 1062 return; 1076 1063 } 1077 - ctx->powered = true; 1064 + 1078 1065 mutex_unlock(&ctx->mixer_mutex); 1079 1066 1080 1067 pm_runtime_get_sync(ctx->dev); ··· 1084 1071 clk_prepare_enable(res->vp); 1085 1072 clk_prepare_enable(res->sclk_mixer); 1086 1073 } 1074 + 1075 + mutex_lock(&ctx->mixer_mutex); 1076 + ctx->powered = true; 1077 + mutex_unlock(&ctx->mixer_mutex); 1078 + 1079 + mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); 1087 1080 1088 1081 mixer_reg_write(res, MXR_INT_EN, ctx->int_en); 1089 1082 mixer_win_reset(ctx); ··· 1103 1084 struct mixer_resources *res = &ctx->mixer_res; 1104 1085 1105 1086 mutex_lock(&ctx->mixer_mutex); 1106 - if (!ctx->powered) 1107 - goto out; 1087 + if (!ctx->powered) { 1088 + mutex_unlock(&ctx->mixer_mutex); 1089 + return; 1090 + } 1108 1091 mutex_unlock(&ctx->mixer_mutex); 1109 1092 1093 + mixer_stop(ctx); 1110 1094 mixer_window_suspend(mgr); 1111 1095 1112 1096 ctx->int_en = mixer_reg_read(res, MXR_INT_EN); 1097 + 1098 + mutex_lock(&ctx->mixer_mutex); 1099 + ctx->powered = false; 1100 + mutex_unlock(&ctx->mixer_mutex); 1113 1101 1114 1102 clk_disable_unprepare(res->mixer); 1115 1103 if (ctx->vp_enabled) { ··· 1125 1099 } 1126 1100 1127 1101 pm_runtime_put_sync(ctx->dev); 1128 - 1129 - mutex_lock(&ctx->mixer_mutex); 1130 - ctx->powered = false; 1131 - 1132 - out: 1133 - mutex_unlock(&ctx->mixer_mutex); 1134 1102 } 1135 1103 1136 1104 static void mixer_dpms(struct exynos_drm_manager *mgr, int mode)
+1
drivers/gpu/drm/exynos/regs-mixer.h
··· 78 78 #define MXR_STATUS_BIG_ENDIAN (1 << 3) 79 79 #define MXR_STATUS_ENDIAN_MASK (1 << 3) 80 80 #define MXR_STATUS_SYNC_ENABLE (1 << 2) 81 + #define MXR_STATUS_REG_IDLE (1 << 1) 81 82 #define MXR_STATUS_REG_RUN (1 << 0) 82 83 83 84 /* bits for MXR_CFG */
+2
drivers/gpu/drm/i915/i915_debugfs.c
··· 446 446 447 447 memset(&stats, 0, sizeof(stats)); 448 448 stats.file_priv = file->driver_priv; 449 + spin_lock(&file->table_lock); 449 450 idr_for_each(&file->object_idr, per_file_stats, &stats); 451 + spin_unlock(&file->table_lock); 450 452 /* 451 453 * Although we have a valid reference on file->pid, that does 452 454 * not guarantee that the task_struct who called get_pid() is
+2
drivers/gpu/drm/i915/i915_drv.h
··· 977 977 bool always_on; 978 978 /* power well enable/disable usage count */ 979 979 int count; 980 + /* cached hw enabled state */ 981 + bool hw_enabled; 980 982 unsigned long domains; 981 983 unsigned long data; 982 984 const struct i915_power_well_ops *ops;
+5 -3
drivers/gpu/drm/i915/i915_gem_context.c
··· 598 598 struct intel_context *from = ring->last_context; 599 599 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(to); 600 600 u32 hw_flags = 0; 601 + bool uninitialized = false; 601 602 int ret, i; 602 603 603 604 if (from != NULL && ring == &dev_priv->ring[RCS]) { ··· 697 696 i915_gem_context_unreference(from); 698 697 } 699 698 699 + uninitialized = !to->is_initialized && from == NULL; 700 + to->is_initialized = true; 701 + 700 702 done: 701 703 i915_gem_context_reference(to); 702 704 ring->last_context = to; 703 705 to->last_ring = ring; 704 706 705 - if (ring->id == RCS && !to->is_initialized && from == NULL) { 707 + if (uninitialized) { 706 708 ret = i915_gem_render_state_init(ring); 707 709 if (ret) 708 710 DRM_ERROR("init render state: %d\n", ret); 709 711 } 710 - 711 - to->is_initialized = true; 712 712 713 713 return 0; 714 714
+3 -3
drivers/gpu/drm/i915/intel_bios.c
··· 315 315 const struct bdb_lfp_backlight_data *backlight_data; 316 316 const struct bdb_lfp_backlight_data_entry *entry; 317 317 318 - /* Err to enabling backlight if no backlight block. */ 319 - dev_priv->vbt.backlight.present = true; 320 - 321 318 backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT); 322 319 if (!backlight_data) 323 320 return; ··· 1084 1087 enum port port; 1085 1088 1086 1089 dev_priv->vbt.crt_ddc_pin = GMBUS_PORT_VGADDC; 1090 + 1091 + /* Default to having backlight */ 1092 + dev_priv->vbt.backlight.present = true; 1087 1093 1088 1094 /* LFP panel data */ 1089 1095 dev_priv->vbt.lvds_dither = 1;
+7 -6
drivers/gpu/drm/i915/intel_display.c
··· 4564 4564 if (intel_crtc->active) 4565 4565 return; 4566 4566 4567 - vlv_prepare_pll(intel_crtc); 4567 + is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); 4568 + 4569 + if (!is_dsi && !IS_CHERRYVIEW(dev)) 4570 + vlv_prepare_pll(intel_crtc); 4568 4571 4569 4572 /* Set up the display plane register */ 4570 4573 dspcntr = DISPPLANE_GAMMA_ENABLE; ··· 4600 4597 for_each_encoder_on_crtc(dev, crtc, encoder) 4601 4598 if (encoder->pre_pll_enable) 4602 4599 encoder->pre_pll_enable(encoder); 4603 - 4604 - is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); 4605 4600 4606 4601 if (!is_dsi) { 4607 4602 if (IS_CHERRYVIEW(dev)) ··· 12412 12411 12413 12412 for_each_pipe(i) { 12414 12413 error->pipe[i].power_domain_on = 12415 - intel_display_power_enabled_sw(dev_priv, 12416 - POWER_DOMAIN_PIPE(i)); 12414 + intel_display_power_enabled_unlocked(dev_priv, 12415 + POWER_DOMAIN_PIPE(i)); 12417 12416 if (!error->pipe[i].power_domain_on) 12418 12417 continue; 12419 12418 ··· 12448 12447 enum transcoder cpu_transcoder = transcoders[i]; 12449 12448 12450 12449 error->transcoder[i].power_domain_on = 12451 - intel_display_power_enabled_sw(dev_priv, 12450 + intel_display_power_enabled_unlocked(dev_priv, 12452 12451 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); 12453 12452 if (!error->transcoder[i].power_domain_on) 12454 12453 continue;
+2 -2
drivers/gpu/drm/i915/intel_drv.h
··· 950 950 void intel_power_domains_remove(struct drm_i915_private *); 951 951 bool intel_display_power_enabled(struct drm_i915_private *dev_priv, 952 952 enum intel_display_power_domain domain); 953 - bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv, 954 - enum intel_display_power_domain domain); 953 + bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, 954 + enum intel_display_power_domain domain); 955 955 void intel_display_power_get(struct drm_i915_private *dev_priv, 956 956 enum intel_display_power_domain domain); 957 957 void intel_display_power_put(struct drm_i915_private *dev_priv,
+15 -22
drivers/gpu/drm/i915/intel_pm.c
··· 5603 5603 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 5604 5604 } 5605 5605 5606 - bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv, 5607 - enum intel_display_power_domain domain) 5606 + bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, 5607 + enum intel_display_power_domain domain) 5608 5608 { 5609 5609 struct i915_power_domains *power_domains; 5610 5610 struct i915_power_well *power_well; ··· 5615 5615 return false; 5616 5616 5617 5617 power_domains = &dev_priv->power_domains; 5618 + 5618 5619 is_enabled = true; 5620 + 5619 5621 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 5620 5622 if (power_well->always_on) 5621 5623 continue; 5622 5624 5623 - if (!power_well->count) { 5625 + if (!power_well->hw_enabled) { 5624 5626 is_enabled = false; 5625 5627 break; 5626 5628 } 5627 5629 } 5630 + 5628 5631 return is_enabled; 5629 5632 } 5630 5633 ··· 5635 5632 enum intel_display_power_domain domain) 5636 5633 { 5637 5634 struct i915_power_domains *power_domains; 5638 - struct i915_power_well *power_well; 5639 - bool is_enabled; 5640 - int i; 5641 - 5642 - if (dev_priv->pm.suspended) 5643 - return false; 5635 + bool ret; 5644 5636 5645 5637 power_domains = &dev_priv->power_domains; 5646 5638 5647 - is_enabled = true; 5648 - 5649 5639 mutex_lock(&power_domains->lock); 5650 - for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 5651 - if (power_well->always_on) 5652 - continue; 5653 - 5654 - if (!power_well->ops->is_enabled(dev_priv, power_well)) { 5655 - is_enabled = false; 5656 - break; 5657 - } 5658 - } 5640 + ret = intel_display_power_enabled_unlocked(dev_priv, domain); 5659 5641 mutex_unlock(&power_domains->lock); 5660 5642 5661 - return is_enabled; 5643 + return ret; 5662 5644 } 5663 5645 5664 5646 /* ··· 5964 5976 if (!power_well->count++) { 5965 5977 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 5966 5978 power_well->ops->enable(dev_priv, power_well); 5979 + power_well->hw_enabled = true; 5967 5980 } 5968 5981 5969 5982 check_power_well_state(dev_priv, power_well); ··· 5994 6005 5995 6006 if (!--power_well->count && i915.disable_power_well) { 5996 6007 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 6008 + power_well->hw_enabled = false; 5997 6009 power_well->ops->disable(dev_priv, power_well); 5998 6010 } 5999 6011 ··· 6257 6267 int i; 6258 6268 6259 6269 mutex_lock(&power_domains->lock); 6260 - for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) 6270 + for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 6261 6271 power_well->ops->sync_hw(dev_priv, power_well); 6272 + power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 6273 + power_well); 6274 + } 6262 6275 mutex_unlock(&power_domains->lock); 6263 6276 } 6264 6277
+2
drivers/gpu/drm/msm/hdmi/hdmi.c
··· 277 277 static const char *hpd_reg_names[] = {"hpd-gdsc", "hpd-5v"}; 278 278 static const char *pwr_reg_names[] = {"core-vdda", "core-vcc"}; 279 279 static const char *hpd_clk_names[] = {"iface_clk", "core_clk", "mdp_core_clk"}; 280 + static unsigned long hpd_clk_freq[] = {0, 19200000, 0}; 280 281 static const char *pwr_clk_names[] = {"extp_clk", "alt_iface_clk"}; 281 282 282 283 config.phy_init = hdmi_phy_8x74_init; ··· 287 286 config.pwr_reg_names = pwr_reg_names; 288 287 config.pwr_reg_cnt = ARRAY_SIZE(pwr_reg_names); 289 288 config.hpd_clk_names = hpd_clk_names; 289 + config.hpd_freq = hpd_clk_freq; 290 290 config.hpd_clk_cnt = ARRAY_SIZE(hpd_clk_names); 291 291 config.pwr_clk_names = pwr_clk_names; 292 292 config.pwr_clk_cnt = ARRAY_SIZE(pwr_clk_names);
+1
drivers/gpu/drm/msm/hdmi/hdmi.h
··· 87 87 88 88 /* clks that need to be on for hpd: */ 89 89 const char **hpd_clk_names; 90 + const long unsigned *hpd_freq; 90 91 int hpd_clk_cnt; 91 92 92 93 /* clks that need to be on for screen pwr (ie pixel clk): */
+8
drivers/gpu/drm/msm/hdmi/hdmi_connector.c
··· 127 127 } 128 128 129 129 for (i = 0; i < config->hpd_clk_cnt; i++) { 130 + if (config->hpd_freq && config->hpd_freq[i]) { 131 + ret = clk_set_rate(hdmi->hpd_clks[i], 132 + config->hpd_freq[i]); 133 + if (ret) 134 + dev_warn(dev->dev, "failed to set clk %s (%d)\n", 135 + config->hpd_clk_names[i], ret); 136 + } 137 + 130 138 ret = clk_prepare_enable(hdmi->hpd_clks[i]); 131 139 if (ret) { 132 140 dev_err(dev->dev, "failed to enable hpd clk: %s (%d)\n",
+17 -5
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
··· 20 20 #include "msm_mmu.h" 21 21 #include "mdp5_kms.h" 22 22 23 + static const char *iommu_ports[] = { 24 + "mdp_0", 25 + }; 26 + 23 27 static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev); 24 28 25 29 static int mdp5_hw_init(struct msm_kms *kms) ··· 108 104 static void mdp5_destroy(struct msm_kms *kms) 109 105 { 110 106 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 107 + struct msm_mmu *mmu = mdp5_kms->mmu; 108 + 109 + if (mmu) { 110 + mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); 111 + mmu->funcs->destroy(mmu); 112 + } 111 113 kfree(mdp5_kms); 112 114 } 113 115 ··· 226 216 return ret; 227 217 } 228 218 229 - static const char *iommu_ports[] = { 230 - "mdp_0", 231 - }; 232 - 233 219 static int get_clk(struct platform_device *pdev, struct clk **clkp, 234 220 const char *name) 235 221 { ··· 323 317 mmu = msm_iommu_new(dev, config->iommu); 324 318 if (IS_ERR(mmu)) { 325 319 ret = PTR_ERR(mmu); 320 + dev_err(dev->dev, "failed to init iommu: %d\n", ret); 326 321 goto fail; 327 322 } 323 + 328 324 ret = mmu->funcs->attach(mmu, iommu_ports, 329 325 ARRAY_SIZE(iommu_ports)); 330 - if (ret) 326 + if (ret) { 327 + dev_err(dev->dev, "failed to attach iommu: %d\n", ret); 328 + mmu->funcs->destroy(mmu); 331 329 goto fail; 330 + } 332 331 } else { 333 332 dev_info(dev->dev, "no iommu, fallback to phys " 334 333 "contig buffers for scanout\n"); 335 334 mmu = NULL; 336 335 } 336 + mdp5_kms->mmu = mmu; 337 337 338 338 mdp5_kms->id = msm_register_mmu(dev, mmu); 339 339 if (mdp5_kms->id < 0) {
+1
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
··· 33 33 34 34 /* mapper-id used to request GEM buffer mapped for scanout: */ 35 35 int id; 36 + struct msm_mmu *mmu; 36 37 37 38 /* for tracking smp allocation amongst pipes: */ 38 39 mdp5_smp_state_t smp_state;
+1 -1
drivers/gpu/drm/msm/msm_drv.c
··· 159 159 static int get_mdp_ver(struct platform_device *pdev) 160 160 { 161 161 #ifdef CONFIG_OF 162 - const static struct of_device_id match_types[] = { { 162 + static const struct of_device_id match_types[] = { { 163 163 .compatible = "qcom,mdss_mdp", 164 164 .data = (void *)5, 165 165 }, {
+1 -1
drivers/gpu/drm/msm/msm_fbdev.c
··· 59 59 struct drm_framebuffer *fb = NULL; 60 60 struct fb_info *fbi = NULL; 61 61 struct drm_mode_fb_cmd2 mode_cmd = {0}; 62 - dma_addr_t paddr; 62 + uint32_t paddr; 63 63 int ret, size; 64 64 65 65 sizes->surface_bpp = 32;
+6
drivers/gpu/drm/msm/msm_gem.c
··· 278 278 uint32_t *iova) 279 279 { 280 280 struct msm_gem_object *msm_obj = to_msm_bo(obj); 281 + struct drm_device *dev = obj->dev; 281 282 int ret = 0; 282 283 283 284 if (!msm_obj->domain[id].iova) { 284 285 struct msm_drm_private *priv = obj->dev->dev_private; 285 286 struct msm_mmu *mmu = priv->mmus[id]; 286 287 struct page **pages = get_pages(obj); 288 + 289 + if (!mmu) { 290 + dev_err(dev->dev, "null MMU pointer\n"); 291 + return -EINVAL; 292 + } 287 293 288 294 if (IS_ERR(pages)) 289 295 return PTR_ERR(pages);
+20 -3
drivers/gpu/drm/msm/msm_iommu.c
··· 28 28 unsigned long iova, int flags, void *arg) 29 29 { 30 30 DBG("*** fault: iova=%08lx, flags=%d", iova, flags); 31 - return 0; 31 + return -ENOSYS; 32 32 } 33 33 34 34 static int msm_iommu_attach(struct msm_mmu *mmu, const char **names, int cnt) ··· 40 40 for (i = 0; i < cnt; i++) { 41 41 struct device *msm_iommu_get_ctx(const char *ctx_name); 42 42 struct device *ctx = msm_iommu_get_ctx(names[i]); 43 - if (IS_ERR_OR_NULL(ctx)) 43 + if (IS_ERR_OR_NULL(ctx)) { 44 + dev_warn(dev->dev, "couldn't get %s context", names[i]); 44 45 continue; 46 + } 45 47 ret = iommu_attach_device(iommu->domain, ctx); 46 48 if (ret) { 47 49 dev_warn(dev->dev, "could not attach iommu to %s", names[i]); ··· 52 50 } 53 51 54 52 return 0; 53 + } 54 + 55 + static void msm_iommu_detach(struct msm_mmu *mmu, const char **names, int cnt) 56 + { 57 + struct msm_iommu *iommu = to_msm_iommu(mmu); 58 + int i; 59 + 60 + for (i = 0; i < cnt; i++) { 61 + struct device *msm_iommu_get_ctx(const char *ctx_name); 62 + struct device *ctx = msm_iommu_get_ctx(names[i]); 63 + if (IS_ERR_OR_NULL(ctx)) 64 + continue; 65 + iommu_detach_device(iommu->domain, ctx); 66 + } 55 67 } 56 68 57 69 static int msm_iommu_map(struct msm_mmu *mmu, uint32_t iova, ··· 126 110 127 111 VERB("unmap[%d]: %08x(%x)", i, iova, bytes); 128 112 129 - BUG_ON(!IS_ALIGNED(bytes, PAGE_SIZE)); 113 + BUG_ON(!PAGE_ALIGNED(bytes)); 130 114 131 115 da += bytes; 132 116 } ··· 143 127 144 128 static const struct msm_mmu_funcs funcs = { 145 129 .attach = msm_iommu_attach, 130 + .detach = msm_iommu_detach, 146 131 .map = msm_iommu_map, 147 132 .unmap = msm_iommu_unmap, 148 133 .destroy = msm_iommu_destroy,
+1
drivers/gpu/drm/msm/msm_mmu.h
··· 22 22 23 23 struct msm_mmu_funcs { 24 24 int (*attach)(struct msm_mmu *mmu, const char **names, int cnt); 25 + void (*detach)(struct msm_mmu *mmu, const char **names, int cnt); 25 26 int (*map)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt, 26 27 unsigned len, int prot); 27 28 int (*unmap)(struct msm_mmu *mmu, uint32_t iova, struct sg_table *sgt,
+10 -2
include/drm/i915_pciids.h
··· 237 237 #define INTEL_BDW_GT3D_IDS(info) \ 238 238 _INTEL_BDW_D_IDS(3, info) 239 239 240 + #define INTEL_BDW_RSVDM_IDS(info) \ 241 + _INTEL_BDW_M_IDS(4, info) 242 + 243 + #define INTEL_BDW_RSVDD_IDS(info) \ 244 + _INTEL_BDW_D_IDS(4, info) 245 + 240 246 #define INTEL_BDW_M_IDS(info) \ 241 247 INTEL_BDW_GT12M_IDS(info), \ 242 - INTEL_BDW_GT3M_IDS(info) 248 + INTEL_BDW_GT3M_IDS(info), \ 249 + INTEL_BDW_RSVDM_IDS(info) 243 250 244 251 #define INTEL_BDW_D_IDS(info) \ 245 252 INTEL_BDW_GT12D_IDS(info), \ 246 - INTEL_BDW_GT3D_IDS(info) 253 + INTEL_BDW_GT3D_IDS(info), \ 254 + INTEL_BDW_RSVDD_IDS(info) 247 255 248 256 #define INTEL_CHV_IDS(info) \ 249 257 INTEL_VGA_DEVICE(0x22b0, info), \