tjh.dev / kernel
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Merge tag 'sh-for-v6.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux

Pull sh updates from Adrian Glaubitz:
"Fix a compiler warning in the J2 probing code and a fix by Sergey
Shtylyov to avoid using IRQ0 on SH3 and SH4 targets. Masahiro Yamada
made some clean-up in the build system to address reports by the 0day
bot.

The most notable changes come from Artur Rojek who addressed a number
of issues in the DMA code, in particular a fix for the DMA channel
offset calculation that was introduced in in 7f47c7189b3e ("sh: dma:
More legacy cpu dma chainsawing.") in 2012!

Together with another change to correct the number of DMA channels for
each SuperH SoC according to specification, Artur's series unbreaks
the kernel on the SH7709 SoC allowing Linux to boot on the HP Jornada
680 handheld again.

Summary:

- Provide unxlate_dev_mem_ptr() in asm/io.h

- dma: Correct the number of DMA channels for SH7709

- dma: Drop incorrect SH_DMAC_BASE1 definition for SH4

- dma: Fix DMA channel offset calculation

- Remove compiler flag duplication

- Refactor header include path addition

- Move build rule for cchips/hd6446x/ to arch/sh/Kbuild

- Fix -Wmissing-include-dirs warnings for various platforms

- Avoid using IRQ0 on SH3 and SH4

- j2: Use ioremap() to translate device tree address into kernel
memory"

* tag 'sh-for-v6.5-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux:
sh: Provide unxlate_dev_mem_ptr() in asm/io.h
sh: dma: Correct the number of DMA channels for SH7709
sh: dma: Drop incorrect SH_DMAC_BASE1 definition for SH4
sh: dma: Fix DMA channel offset calculation
sh: Remove compiler flag duplication
sh: Refactor header include path addition
sh: Move build rule for cchips/hd6446x/ to arch/sh/Kbuild
sh: Fix -Wmissing-include-dirs warnings for various platforms
sh: Avoid using IRQ0 on SH3 and SH4
sh: j2: Use ioremap() to translate device tree address into kernel memory

Linus Torvalds c17414a2 7afb9d76

+66 -54
+2
arch/sh/Kbuild
··· 3 3 obj-$(CONFIG_SH_FPU_EMU) += math-emu/ 4 4 obj-$(CONFIG_USE_BUILTIN_DTB) += boot/dts/ 5 5 6 + obj-$(CONFIG_HD6446X_SERIES) += cchips/hd6446x/ 7 + 6 8 # for cleaning 7 9 subdir- += boot
+2 -24
arch/sh/Makefile
··· 116 116 117 117 # Mach groups 118 118 machdir-$(CONFIG_SOLUTION_ENGINE) += mach-se 119 - machdir-$(CONFIG_SH_HP6XX) += mach-hp6xx 120 119 machdir-$(CONFIG_SH_DREAMCAST) += mach-dreamcast 121 120 machdir-$(CONFIG_SH_SH03) += mach-sh03 122 - machdir-$(CONFIG_SH_RTS7751R2D) += mach-r2d 123 - machdir-$(CONFIG_SH_HIGHLANDER) += mach-highlander 124 121 machdir-$(CONFIG_SH_MIGOR) += mach-migor 125 - machdir-$(CONFIG_SH_AP325RXA) += mach-ap325rxa 126 122 machdir-$(CONFIG_SH_KFR2R09) += mach-kfr2r09 127 123 machdir-$(CONFIG_SH_ECOVEC) += mach-ecovec24 128 - machdir-$(CONFIG_SH_SDK7780) += mach-sdk7780 129 124 machdir-$(CONFIG_SH_SDK7786) += mach-sdk7786 130 125 machdir-$(CONFIG_SH_X3PROTO) += mach-x3proto 131 - machdir-$(CONFIG_SH_SH7763RDP) += mach-sh7763rdp 132 - machdir-$(CONFIG_SH_SH4202_MICRODEV) += mach-microdev 133 126 machdir-$(CONFIG_SH_LANDISK) += mach-landisk 134 - machdir-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2 135 - machdir-$(CONFIG_SH_RSK) += mach-rsk 136 - 137 - ifneq ($(machdir-y),) 138 - core-y += $(addprefix arch/sh/boards/, \ 139 - $(filter-out ., $(patsubst %,%/,$(machdir-y)))) 140 - endif 141 - 142 - # Common machine type headers. Not part of the arch/sh/boards/ hierarchy. 143 - machdir-y += mach-common 144 - 145 - # Companion chips 146 - core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/ 127 + machdir-y += mach-common 147 128 148 129 # 149 130 # CPU header paths ··· 145 164 146 165 drivers-y += arch/sh/drivers/ 147 166 148 - cflags-y += $(foreach d, $(cpuincdir-y), -I $(srctree)/arch/sh/include/$(d)) \ 149 - $(foreach d, $(machdir-y), -I $(srctree)/arch/sh/include/$(d)) 150 - 167 + KBUILD_CPPFLAGS += $(addprefix -I $(srctree)/arch/sh/include/, $(cpuincdir-y) $(machdir-y)) 151 168 KBUILD_CFLAGS += -pipe $(cflags-y) 152 - KBUILD_CPPFLAGS += $(cflags-y) 153 169 KBUILD_AFLAGS += $(cflags-y) 154 170 155 171 ifeq ($(CONFIG_MCOUNT),y)
+19
arch/sh/boards/Makefile
··· 18 18 obj-$(CONFIG_SH_APSH4AD0A) += board-apsh4ad0a.o 19 19 20 20 obj-$(CONFIG_SH_DEVICE_TREE) += of-generic.o 21 + 22 + obj-$(CONFIG_SOLUTION_ENGINE) += mach-se/ 23 + obj-$(CONFIG_SH_HP6XX) += mach-hp6xx/ 24 + obj-$(CONFIG_SH_DREAMCAST) += mach-dreamcast/ 25 + obj-$(CONFIG_SH_SH03) += mach-sh03/ 26 + obj-$(CONFIG_SH_RTS7751R2D) += mach-r2d/ 27 + obj-$(CONFIG_SH_HIGHLANDER) += mach-highlander/ 28 + obj-$(CONFIG_SH_MIGOR) += mach-migor/ 29 + obj-$(CONFIG_SH_AP325RXA) += mach-ap325rxa/ 30 + obj-$(CONFIG_SH_KFR2R09) += mach-kfr2r09/ 31 + obj-$(CONFIG_SH_ECOVEC) += mach-ecovec24/ 32 + obj-$(CONFIG_SH_SDK7780) += mach-sdk7780/ 33 + obj-$(CONFIG_SH_SDK7786) += mach-sdk7786/ 34 + obj-$(CONFIG_SH_X3PROTO) += mach-x3proto/ 35 + obj-$(CONFIG_SH_SH7763RDP) += mach-sh7763rdp/ 36 + obj-$(CONFIG_SH_SH4202_MICRODEV)+= mach-microdev/ 37 + obj-$(CONFIG_SH_LANDISK) += mach-landisk/ 38 + obj-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2/ 39 + obj-$(CONFIG_SH_RSK) += mach-rsk/
+8 -6
arch/sh/drivers/dma/Kconfig
··· 28 28 config NR_ONCHIP_DMA_CHANNELS 29 29 int 30 30 depends on SH_DMA 31 - default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \ 32 - CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7091 31 + default "4" if CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7750 || \ 32 + CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7751 || \ 33 + CPU_SUBTYPE_SH7091 33 34 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \ 34 35 CPU_SUBTYPE_SH7760 35 - default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || \ 36 - CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7724 36 + default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7724 || \ 37 + CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 37 38 default "6" 38 39 help 39 40 This allows you to specify the number of channels that the on-chip 40 - DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the 41 - SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6. 41 + DMAC supports. This will be 4 for SH7709/SH7750/SH7750S/SH7751/SH7091, 42 + 8 for SH7750R/SH7751R/SH7760, and 12 for SH7723/SH7724/SH7780/SH7785. 43 + Default is 6. 42 44 43 45 config SH_DMABRG 44 46 bool "SH7760 DMABRG support"
+24 -13
arch/sh/drivers/dma/dma-sh.c
··· 19 19 #include <cpu/dma.h> 20 20 21 21 /* 22 + * Some of the SoCs feature two DMAC modules. In such a case, the channels are 23 + * distributed equally among them. 24 + */ 25 + #ifdef SH_DMAC_BASE1 26 + #define SH_DMAC_NR_MD_CH (CONFIG_NR_ONCHIP_DMA_CHANNELS / 2) 27 + #else 28 + #define SH_DMAC_NR_MD_CH CONFIG_NR_ONCHIP_DMA_CHANNELS 29 + #endif 30 + 31 + #define SH_DMAC_CH_SZ 0x10 32 + 33 + /* 22 34 * Define the default configuration for dual address memory-memory transfer. 23 35 * The 0x400 value represents auto-request, external->external. 24 36 */ ··· 41 29 unsigned long base = SH_DMAC_BASE0; 42 30 43 31 #ifdef SH_DMAC_BASE1 44 - if (chan >= 6) 32 + if (chan >= SH_DMAC_NR_MD_CH) 45 33 base = SH_DMAC_BASE1; 46 34 #endif 47 35 ··· 52 40 { 53 41 unsigned long base = dma_find_base(chan); 54 42 55 - /* Normalize offset calculation */ 56 - if (chan >= 9) 57 - chan -= 6; 58 - if (chan >= 4) 59 - base += 0x10; 43 + chan = (chan % SH_DMAC_NR_MD_CH) * SH_DMAC_CH_SZ; 60 44 61 - return base + (chan * 0x10); 45 + /* DMAOR is placed inside the channel register space. Step over it. */ 46 + if (chan >= DMAOR) 47 + base += SH_DMAC_CH_SZ; 48 + 49 + return base + chan; 62 50 } 63 51 64 52 #ifdef CONFIG_SH_DMA_IRQ_MULTI ··· 262 250 #define NR_DMAOR 1 263 251 #endif 264 252 265 - /* 266 - * DMAOR bases are broken out amongst channel groups. DMAOR0 manages 267 - * channels 0 - 5, DMAOR1 6 - 11 (optional). 268 - */ 269 - #define dmaor_read_reg(n) __raw_readw(dma_find_base((n)*6)) 270 - #define dmaor_write_reg(n, data) __raw_writew(data, dma_find_base(n)*6) 253 + #define dmaor_read_reg(n) __raw_readw(dma_find_base((n) * \ 254 + SH_DMAC_NR_MD_CH) + DMAOR) 255 + #define dmaor_write_reg(n, data) __raw_writew(data, \ 256 + dma_find_base((n) * \ 257 + SH_DMAC_NR_MD_CH) + DMAOR) 271 258 272 259 static inline int dmaor_reset(int no) 273 260 {
+1
arch/sh/include/asm/io.h
··· 286 286 * access 287 287 */ 288 288 #define xlate_dev_mem_ptr(p) __va(p) 289 + #define unxlate_dev_mem_ptr(p, v) do { } while (0) 289 290 290 291 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE 291 292 int valid_phys_addr_range(phys_addr_t addr, size_t size);
-1
arch/sh/include/cpu-sh4/cpu/dma.h
··· 13 13 #define DMAE0_IRQ evt2irq(0x6c0) 14 14 15 15 #define SH_DMAC_BASE0 0xffa00000 16 - #define SH_DMAC_BASE1 0xffa00070 17 16 18 17 #endif /* __ASM_CPU_SH4_DMA_H */
+1 -1
arch/sh/include/mach-common/mach/highlander.h
··· 176 176 #define IVDR_CK_ON 4 /* iVDR Clock ON */ 177 177 #endif 178 178 179 - #define HL_FPGA_IRQ_BASE 200 179 + #define HL_FPGA_IRQ_BASE (200 + 16) 180 180 #define HL_NR_IRL 15 181 181 182 182 #define IRQ_AX88796 (HL_FPGA_IRQ_BASE + 0)
+1 -1
arch/sh/include/mach-common/mach/r2d.h
··· 47 47 48 48 #define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ 49 49 50 - #define R2D_FPGA_IRQ_BASE 100 50 + #define R2D_FPGA_IRQ_BASE (100 + 16) 51 51 52 52 #define IRQ_VOYAGER (R2D_FPGA_IRQ_BASE + 0) 53 53 #define IRQ_EXT (R2D_FPGA_IRQ_BASE + 1)
+1 -1
arch/sh/include/mach-dreamcast/mach/sysasic.h
··· 22 22 takes. 23 23 */ 24 24 25 - #define HW_EVENT_IRQ_BASE 48 25 + #define HW_EVENT_IRQ_BASE (48 + 16) 26 26 27 27 /* IRQ 13 */ 28 28 #define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */
+1 -1
arch/sh/include/mach-se/mach/se7724.h
··· 37 37 #define IRQ2_IRQ evt2irq(0x640) 38 38 39 39 /* Bits in IRQ012 registers */ 40 - #define SE7724_FPGA_IRQ_BASE 220 40 + #define SE7724_FPGA_IRQ_BASE (220 + 16) 41 41 42 42 /* IRQ0 */ 43 43 #define IRQ0_BASE SE7724_FPGA_IRQ_BASE
+1 -1
arch/sh/kernel/cpu/sh2/probe.c
··· 21 21 if (!of_flat_dt_is_compatible(node, "jcore,cache")) 22 22 return 0; 23 23 24 - j2_ccr_base = (u32 __iomem *)of_flat_dt_translate_address(node); 24 + j2_ccr_base = ioremap(of_flat_dt_translate_address(node), 4); 25 25 26 26 return 1; 27 27 }
+2 -2
arch/sh/kernel/cpu/sh3/entry.S
··· 470 470 mov r4, r0 ! save vector->jmp table offset for later 471 471 472 472 shlr2 r4 ! vector to IRQ# conversion 473 - add #-0x10, r4 474 473 475 - cmp/pz r4 ! is it a valid IRQ? 474 + mov #0x10, r5 475 + cmp/hs r5, r4 ! is it a valid IRQ? 476 476 bt 10f 477 477 478 478 /*
+3 -3
include/linux/sh_intc.h
··· 13 13 /* 14 14 * Convert back and forth between INTEVT and IRQ values. 15 15 */ 16 - #ifdef CONFIG_CPU_HAS_INTEVT 17 - #define evt2irq(evt) (((evt) >> 5) - 16) 18 - #define irq2evt(irq) (((irq) + 16) << 5) 16 + #ifdef CONFIG_CPU_HAS_INTEVT /* Avoid IRQ0 (invalid for platform devices) */ 17 + #define evt2irq(evt) ((evt) >> 5) 18 + #define irq2evt(irq) ((irq) << 5) 19 19 #else 20 20 #define evt2irq(evt) (evt) 21 21 #define irq2evt(irq) (irq)