Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: add NBIO 6.1 driver
This handles nbio 6.1 specific implementations which
are used by various other IPs.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Junwei Zhang
and committed by
Alex Deucher
c1d83da9
b0fd18b0
+286
-1
+1
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+1
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+233
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+233
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
···
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+
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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+
*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#include "amdgpu_atombios.h"
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#include "nbio_v6_1.h"
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#include "vega10/soc15ip.h"
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#include "vega10/NBIO/nbio_6_1_default.h"
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#include "vega10/NBIO/nbio_6_1_offset.h"
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#include "vega10/NBIO/nbio_6_1_sh_mask.h"
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#include "vega10/vega10_enum.h"
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+
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#define smnCPM_CONTROL 0x11180460
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#define smnPCIE_CNTL2 0x11180070
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u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
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{
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u32 tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0));
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tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
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tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
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return tmp;
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}
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+
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u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
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uint32_t idx)
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{
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return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx);
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}
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+
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void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev,
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uint32_t idx, uint32_t val)
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{
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WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0) + idx, val);
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}
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void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
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{
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if (enable)
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WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN),
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BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
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else
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WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_FB_EN), 0);
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}
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void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)
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{
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WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
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}
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u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
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{
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return RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE));
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}
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+
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static const u32 nbio_sdma_doorbell_range_reg[] =
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{
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SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE),
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SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE)
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};
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void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
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bool use_doorbell, int doorbell_index)
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{
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u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]);
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if (use_doorbell) {
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doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
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doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
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} else
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doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
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WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range);
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}
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void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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u32 tmp;
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tmp = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_PF_0_0_RCC_DOORBELL_APER_EN));
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if (enable)
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tmp = REG_SET_FIELD(tmp, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
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else
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tmp = REG_SET_FIELD(tmp, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
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WREG32(SOC15_REG_OFFSET(NBIO, 0, mmRCC_PF_0_0_RCC_DOORBELL_APER_EN), tmp);
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}
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void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
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bool enable)
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{
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u32 tmp = 0;
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if (enable) {
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tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
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WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW),
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lower_32_bits(adev->doorbell.base));
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WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH),
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upper_32_bits(adev->doorbell.base));
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}
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WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL), tmp);
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}
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void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
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bool use_doorbell, int doorbell_index)
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{
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u32 ih_doorbell_range = RREG32(SOC15_REG_OFFSET(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE));
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if (use_doorbell) {
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
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} else
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ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
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WREG32(SOC15_REG_OFFSET(NBIO, 0, mmBIF_IH_DOORBELL_RANGE), ih_doorbell_range);
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}
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void nbio_v6_1_ih_control(struct amdgpu_device *adev)
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{
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u32 interrupt_cntl;
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/* setup interrupt control */
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WREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL2), adev->dummy_page.addr >> 8);
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interrupt_cntl = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL));
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/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
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* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
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*/
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
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/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
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WREG32(SOC15_REG_OFFSET(NBIO, 0, mmINTERRUPT_CNTL), interrupt_cntl);
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}
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void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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def = data = RREG32_PCIE(smnCPM_CONTROL);
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
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data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
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CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
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} else {
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data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
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CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
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CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
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}
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if (def != data)
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WREG32_PCIE(smnCPM_CONTROL, data);
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}
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void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t def, data;
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def = data = RREG32_PCIE(smnPCIE_CNTL2);
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
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data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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} else {
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data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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}
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if (def != data)
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WREG32_PCIE(smnPCIE_CNTL2, data);
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}
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struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
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struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
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int nbio_v6_1_init(struct amdgpu_device *adev)
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{
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nbio_v6_1_hdp_flush_reg.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
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nbio_v6_1_hdp_flush_reg.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
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nbio_v6_1_hdp_flush_reg.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK;
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nbio_v6_1_hdp_flush_reg.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK;
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nbio_v6_1_hdp_flush_reg.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK;
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nbio_v6_1_hdp_flush_reg.ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK;
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nbio_v6_1_hdp_flush_reg.ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK;
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nbio_v6_1_hdp_flush_reg.ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK;
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nbio_v6_1_hdp_flush_reg.ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK;
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nbio_v6_1_hdp_flush_reg.ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK;
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nbio_v6_1_hdp_flush_reg.ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK;
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nbio_v6_1_hdp_flush_reg.ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK;
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nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK;
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nbio_v6_1_hdp_flush_reg.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK;
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+
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nbio_v6_1_pcie_index_data.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX);
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nbio_v6_1_pcie_index_data.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA);
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+
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return 0;
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}
+52
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+52
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
···
1
+
/*
2
+
* Copyright 2016 Advanced Micro Devices, Inc.
3
+
*
4
+
* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
21
+
*
22
+
*/
23
+
24
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#ifndef __NBIO_V6_1_H__
25
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#define __NBIO_V6_1_H__
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#include "soc15_common.h"
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+
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extern struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
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extern struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;
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int nbio_v6_1_init(struct amdgpu_device *adev);
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u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
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uint32_t idx);
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void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev,
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uint32_t idx, uint32_t val);
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void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable);
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void nbio_v6_1_hdp_flush(struct amdgpu_device *adev);
38
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u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev);
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void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
40
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bool use_doorbell, int doorbell_index);
41
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void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
42
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bool enable);
43
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void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
44
+
bool enable);
45
+
void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
46
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bool use_doorbell, int doorbell_index);
47
+
void nbio_v6_1_ih_control(struct amdgpu_device *adev);
48
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u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev);
49
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void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable);
50
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void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable);
51
+
52
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#endif