Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Reduce stack size for dml31_ModeSupportAndSystemConfigurationFull
Move code using the Pipe struct to a new helper function.
Works around[0] this warning (resulting in failure to build a RHEL debug
kernel with Werror enabled):
../drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c: In function ‘dml31_ModeSupportAndSystemConfigurationFull’:
../drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c:5740:1: warning: the frame size of 2144 bytes is larger than 2048 bytes [-Wframe-larger-than=]
The culprit seems to be the Pipe struct, so pull the relevant block out
into its own sub-function. (This is porting
commit a62427ef9b55 ("drm/amd/display: Reduce stack size for dml21_ModeSupportAndSystemConfigurationFull")
from dml31 to dml21)
[0] AFAICT this doesn't actually reduce the total amount of stack which
can be used, just moves some of it from
dml31_ModeSupportAndSystemConfigurationFull to the new helper function,
so the former happens to no longer exceed the limit for a single
function.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Michel Dänzer
and committed by
Alex Deucher
c1e003d3
ba6f8c13
+99
-86
+99
-86
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+99
-86
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
···
3949
3949
return BPP_INVALID;
3950
3950
}
3951
3951
3952
+
static noinline void CalculatePrefetchSchedulePerPlane(
3953
+
struct display_mode_lib *mode_lib,
3954
+
double HostVMInefficiencyFactor,
3955
+
int i,
3956
+
unsigned j,
3957
+
unsigned k)
3958
+
{
3959
+
struct vba_vars_st *v = &mode_lib->vba;
3960
+
Pipe myPipe;
3961
+
3962
+
myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
3963
+
myPipe.DISPCLK = v->RequiredDISPCLK[i][j];
3964
+
myPipe.PixelClock = v->PixelClock[k];
3965
+
myPipe.DCFCLKDeepSleep = v->ProjectedDCFCLKDeepSleep[i][j];
3966
+
myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
3967
+
myPipe.ScalerEnabled = v->ScalerEnabled[k];
3968
+
myPipe.SourceScan = v->SourceScan[k];
3969
+
myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
3970
+
myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
3971
+
myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
3972
+
myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
3973
+
myPipe.InterlaceEnable = v->Interlace[k];
3974
+
myPipe.NumberOfCursors = v->NumberOfCursors[k];
3975
+
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
3976
+
myPipe.HTotal = v->HTotal[k];
3977
+
myPipe.DCCEnable = v->DCCEnable[k];
3978
+
myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
3979
+
|| v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1;
3980
+
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
3981
+
myPipe.BytePerPixelY = v->BytePerPixelY[k];
3982
+
myPipe.BytePerPixelC = v->BytePerPixelC[k];
3983
+
myPipe.ProgressiveToInterlaceUnitInOPP = v->ProgressiveToInterlaceUnitInOPP;
3984
+
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
3985
+
mode_lib,
3986
+
HostVMInefficiencyFactor,
3987
+
&myPipe,
3988
+
v->DSCDelayPerState[i][k],
3989
+
v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
3990
+
v->DPPCLKDelaySCL,
3991
+
v->DPPCLKDelaySCLLBOnly,
3992
+
v->DPPCLKDelayCNVCCursor,
3993
+
v->DISPCLKDelaySubtotal,
3994
+
v->SwathWidthYThisState[k] / v->HRatio[k],
3995
+
v->OutputFormat[k],
3996
+
v->MaxInterDCNTileRepeaters,
3997
+
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
3998
+
v->MaximumVStartup[i][j][k],
3999
+
v->GPUVMMaxPageTableLevels,
4000
+
v->GPUVMEnable,
4001
+
v->HostVMEnable,
4002
+
v->HostVMMaxNonCachedPageTableLevels,
4003
+
v->HostVMMinPageSize,
4004
+
v->DynamicMetadataEnable[k],
4005
+
v->DynamicMetadataVMEnabled,
4006
+
v->DynamicMetadataLinesBeforeActiveRequired[k],
4007
+
v->DynamicMetadataTransmittedBytes[k],
4008
+
v->UrgLatency[i],
4009
+
v->ExtraLatency,
4010
+
v->TimeCalc,
4011
+
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
4012
+
v->MetaRowBytes[i][j][k],
4013
+
v->DPTEBytesPerRow[i][j][k],
4014
+
v->PrefetchLinesY[i][j][k],
4015
+
v->SwathWidthYThisState[k],
4016
+
v->PrefillY[k],
4017
+
v->MaxNumSwY[k],
4018
+
v->PrefetchLinesC[i][j][k],
4019
+
v->SwathWidthCThisState[k],
4020
+
v->PrefillC[k],
4021
+
v->MaxNumSwC[k],
4022
+
v->swath_width_luma_ub_this_state[k],
4023
+
v->swath_width_chroma_ub_this_state[k],
4024
+
v->SwathHeightYThisState[k],
4025
+
v->SwathHeightCThisState[k],
4026
+
v->TWait,
4027
+
&v->DSTXAfterScaler[k],
4028
+
&v->DSTYAfterScaler[k],
4029
+
&v->LineTimesForPrefetch[k],
4030
+
&v->PrefetchBW[k],
4031
+
&v->LinesForMetaPTE[k],
4032
+
&v->LinesForMetaAndDPTERow[k],
4033
+
&v->VRatioPreY[i][j][k],
4034
+
&v->VRatioPreC[i][j][k],
4035
+
&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
4036
+
&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
4037
+
&v->NoTimeForDynamicMetadata[i][j][k],
4038
+
&v->Tno_bw[k],
4039
+
&v->prefetch_vmrow_bw[k],
4040
+
&v->dummy7[k],
4041
+
&v->dummy8[k],
4042
+
&v->dummy13[k],
4043
+
&v->VUpdateOffsetPix[k],
4044
+
&v->VUpdateWidthPix[k],
4045
+
&v->VReadyOffsetPix[k]);
4046
+
}
4047
+
3952
4048
void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
3953
4049
{
3954
4050
struct vba_vars_st *v = &mode_lib->vba;
···
5372
5276
v->SREnterPlusExitTime);
5373
5277
5374
5278
for (k = 0; k < v->NumberOfActivePlanes; k++) {
5375
-
Pipe myPipe;
5376
-
5377
-
myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
5378
-
myPipe.DISPCLK = v->RequiredDISPCLK[i][j];
5379
-
myPipe.PixelClock = v->PixelClock[k];
5380
-
myPipe.DCFCLKDeepSleep = v->ProjectedDCFCLKDeepSleep[i][j];
5381
-
myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
5382
-
myPipe.ScalerEnabled = v->ScalerEnabled[k];
5383
-
myPipe.SourceScan = v->SourceScan[k];
5384
-
myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
5385
-
myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
5386
-
myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
5387
-
myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
5388
-
myPipe.InterlaceEnable = v->Interlace[k];
5389
-
myPipe.NumberOfCursors = v->NumberOfCursors[k];
5390
-
myPipe.VBlank = v->VTotal[k] - v->VActive[k];
5391
-
myPipe.HTotal = v->HTotal[k];
5392
-
myPipe.DCCEnable = v->DCCEnable[k];
5393
-
myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
5394
-
|| v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1;
5395
-
myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
5396
-
myPipe.BytePerPixelY = v->BytePerPixelY[k];
5397
-
myPipe.BytePerPixelC = v->BytePerPixelC[k];
5398
-
myPipe.ProgressiveToInterlaceUnitInOPP = v->ProgressiveToInterlaceUnitInOPP;
5399
-
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
5400
-
mode_lib,
5401
-
HostVMInefficiencyFactor,
5402
-
&myPipe,
5403
-
v->DSCDelayPerState[i][k],
5404
-
v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
5405
-
v->DPPCLKDelaySCL,
5406
-
v->DPPCLKDelaySCLLBOnly,
5407
-
v->DPPCLKDelayCNVCCursor,
5408
-
v->DISPCLKDelaySubtotal,
5409
-
v->SwathWidthYThisState[k] / v->HRatio[k],
5410
-
v->OutputFormat[k],
5411
-
v->MaxInterDCNTileRepeaters,
5412
-
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
5413
-
v->MaximumVStartup[i][j][k],
5414
-
v->GPUVMMaxPageTableLevels,
5415
-
v->GPUVMEnable,
5416
-
v->HostVMEnable,
5417
-
v->HostVMMaxNonCachedPageTableLevels,
5418
-
v->HostVMMinPageSize,
5419
-
v->DynamicMetadataEnable[k],
5420
-
v->DynamicMetadataVMEnabled,
5421
-
v->DynamicMetadataLinesBeforeActiveRequired[k],
5422
-
v->DynamicMetadataTransmittedBytes[k],
5423
-
v->UrgLatency[i],
5424
-
v->ExtraLatency,
5425
-
v->TimeCalc,
5426
-
v->PDEAndMetaPTEBytesPerFrame[i][j][k],
5427
-
v->MetaRowBytes[i][j][k],
5428
-
v->DPTEBytesPerRow[i][j][k],
5429
-
v->PrefetchLinesY[i][j][k],
5430
-
v->SwathWidthYThisState[k],
5431
-
v->PrefillY[k],
5432
-
v->MaxNumSwY[k],
5433
-
v->PrefetchLinesC[i][j][k],
5434
-
v->SwathWidthCThisState[k],
5435
-
v->PrefillC[k],
5436
-
v->MaxNumSwC[k],
5437
-
v->swath_width_luma_ub_this_state[k],
5438
-
v->swath_width_chroma_ub_this_state[k],
5439
-
v->SwathHeightYThisState[k],
5440
-
v->SwathHeightCThisState[k],
5441
-
v->TWait,
5442
-
&v->DSTXAfterScaler[k],
5443
-
&v->DSTYAfterScaler[k],
5444
-
&v->LineTimesForPrefetch[k],
5445
-
&v->PrefetchBW[k],
5446
-
&v->LinesForMetaPTE[k],
5447
-
&v->LinesForMetaAndDPTERow[k],
5448
-
&v->VRatioPreY[i][j][k],
5449
-
&v->VRatioPreC[i][j][k],
5450
-
&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
5451
-
&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
5452
-
&v->NoTimeForDynamicMetadata[i][j][k],
5453
-
&v->Tno_bw[k],
5454
-
&v->prefetch_vmrow_bw[k],
5455
-
&v->dummy7[k],
5456
-
&v->dummy8[k],
5457
-
&v->dummy13[k],
5458
-
&v->VUpdateOffsetPix[k],
5459
-
&v->VUpdateWidthPix[k],
5460
-
&v->VReadyOffsetPix[k]);
5279
+
CalculatePrefetchSchedulePerPlane(mode_lib,
5280
+
HostVMInefficiencyFactor,
5281
+
i, j, k);
5461
5282
}
5462
5283
5463
5284
for (k = 0; k < v->NumberOfActivePlanes; k++) {