Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Peter Anvin:
"Quite a varied little collection of fixes. Most of them are
relatively small or isolated; the biggest one is Mel Gorman's fixes
for TLB range flushing.
A couple of AMD-related fixes (including not crashing when given an
invalid microcode image) and fix a crash when compiled with gcov"
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86, microcode, AMD: Unify valid container checks
x86, hweight: Fix BUG when booting with CONFIG_GCOV_PROFILE_ALL=y
x86/efi: Allow mapping BGRT on x86-32
x86: Fix the initialization of physnode_map
x86, cpu hotplug: Fix stack frame warning in check_irq_vectors_for_cpu_disable()
x86/intel/mid: Fix X86_INTEL_MID dependencies
arch/x86/mm/srat: Skip NUMA_NO_NODE while parsing SLIT
mm, x86: Revisit tlb_flushall_shift tuning for page flushes except on IvyBridge
x86: mm: change tlb_flushall_shift for IvyBridge
x86/mm: Eliminate redundant page table walk during TLB range flushing
x86/mm: Clean up inconsistencies when flushing TLB ranges
mm, x86: Account for TLB flushes only when debugging
x86/AMD/NB: Fix amd_set_subcaches() parameter type
x86/quirks: Add workaround for AMD F16h Erratum792
x86, doc, kconfig: Fix dud URL for Microcode data
+138
-84
+4
-3
arch/x86/Kconfig
+4
-3
arch/x86/Kconfig
···
444
444
bool "Intel MID platform support"
445
445
depends on X86_32
446
446
depends on X86_EXTENDED_PLATFORM
447
+
depends on X86_PLATFORM_DEVICES
447
448
depends on PCI
448
449
depends on PCI_GOANY
449
450
depends on X86_IO_APIC
···
1052
1051
This options enables microcode patch loading support for Intel
1053
1052
processors.
1054
1053
1055
-
For latest news and information on obtaining all the required
1056
-
Intel ingredients for this driver, check:
1057
-
<http://www.urbanmyth.org/microcode/>.
1054
+
For the current Intel microcode data package go to
1055
+
<https://downloadcenter.intel.com> and search for
1056
+
'Linux Processor Microcode Data File'.
1058
1057
1059
1058
config MICROCODE_AMD
1060
1059
bool "AMD microcode loading support"
+1
-1
arch/x86/include/asm/amd_nb.h
+1
-1
arch/x86/include/asm/amd_nb.h
+3
-3
arch/x86/include/asm/tlbflush.h
+3
-3
arch/x86/include/asm/tlbflush.h
···
62
62
63
63
static inline void __flush_tlb_one(unsigned long addr)
64
64
{
65
-
count_vm_event(NR_TLB_LOCAL_FLUSH_ONE);
65
+
count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
66
66
__flush_tlb_single(addr);
67
67
}
68
68
···
93
93
*/
94
94
static inline void __flush_tlb_up(void)
95
95
{
96
-
count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);
96
+
count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
97
97
__flush_tlb();
98
98
}
99
99
100
100
static inline void flush_tlb_all(void)
101
101
{
102
-
count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);
102
+
count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
103
103
__flush_tlb_all();
104
104
}
105
105
+1
-1
arch/x86/kernel/amd_nb.c
+1
-1
arch/x86/kernel/amd_nb.c
+1
-4
arch/x86/kernel/cpu/amd.c
+1
-4
arch/x86/kernel/cpu/amd.c
+3
-7
arch/x86/kernel/cpu/intel.c
+3
-7
arch/x86/kernel/cpu/intel.c
···
640
640
case 0x61d: /* six-core 45 nm xeon "Dunnington" */
641
641
tlb_flushall_shift = -1;
642
642
break;
643
+
case 0x63a: /* Ivybridge */
644
+
tlb_flushall_shift = 2;
645
+
break;
643
646
case 0x61a: /* 45 nm nehalem, "Bloomfield" */
644
647
case 0x61e: /* 45 nm nehalem, "Lynnfield" */
645
648
case 0x625: /* 32 nm nehalem, "Clarkdale" */
646
649
case 0x62c: /* 32 nm nehalem, "Gulftown" */
647
650
case 0x62e: /* 45 nm nehalem-ex, "Beckton" */
648
651
case 0x62f: /* 32 nm Xeon E7 */
649
-
tlb_flushall_shift = 6;
650
-
break;
651
652
case 0x62a: /* SandyBridge */
652
653
case 0x62d: /* SandyBridge, "Romely-EP" */
653
-
tlb_flushall_shift = 5;
654
-
break;
655
-
case 0x63a: /* Ivybridge */
656
-
tlb_flushall_shift = 1;
657
-
break;
658
654
default:
659
655
tlb_flushall_shift = 6;
660
656
}
+29
-14
arch/x86/kernel/cpu/microcode/amd_early.c
+29
-14
arch/x86/kernel/cpu/microcode/amd_early.c
···
285
285
286
286
uci->cpu_sig.sig = cpuid_eax(0x00000001);
287
287
}
288
+
289
+
static void __init get_bsp_sig(void)
290
+
{
291
+
unsigned int bsp = boot_cpu_data.cpu_index;
292
+
struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
293
+
294
+
if (!uci->cpu_sig.sig)
295
+
smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
296
+
}
288
297
#else
289
298
void load_ucode_amd_ap(void)
290
299
{
···
346
337
347
338
int __init save_microcode_in_initrd_amd(void)
348
339
{
340
+
unsigned long cont;
349
341
enum ucode_state ret;
350
342
u32 eax;
351
343
352
-
#ifdef CONFIG_X86_32
353
-
unsigned int bsp = boot_cpu_data.cpu_index;
354
-
struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
344
+
if (!container)
345
+
return -EINVAL;
355
346
356
-
if (!uci->cpu_sig.sig)
357
-
smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
347
+
#ifdef CONFIG_X86_32
348
+
get_bsp_sig();
349
+
cont = (unsigned long)container;
350
+
#else
351
+
/*
352
+
* We need the physical address of the container for both bitness since
353
+
* boot_params.hdr.ramdisk_image is a physical address.
354
+
*/
355
+
cont = __pa(container);
356
+
#endif
358
357
359
358
/*
360
-
* Take into account the fact that the ramdisk might get relocated
361
-
* and therefore we need to recompute the container's position in
362
-
* virtual memory space.
359
+
* Take into account the fact that the ramdisk might get relocated and
360
+
* therefore we need to recompute the container's position in virtual
361
+
* memory space.
363
362
*/
364
-
container = (u8 *)(__va((u32)relocated_ramdisk) +
365
-
((u32)container - boot_params.hdr.ramdisk_image));
366
-
#endif
363
+
if (relocated_ramdisk)
364
+
container = (u8 *)(__va(relocated_ramdisk) +
365
+
(cont - boot_params.hdr.ramdisk_image));
366
+
367
367
if (ucode_new_rev)
368
368
pr_info("microcode: updated early to new patch_level=0x%08x\n",
369
369
ucode_new_rev);
370
-
371
-
if (!container)
372
-
return -EINVAL;
373
370
374
371
eax = cpuid_eax(0x00000001);
375
372
eax = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
+2
-2
arch/x86/kernel/cpu/mtrr/generic.c
+2
-2
arch/x86/kernel/cpu/mtrr/generic.c
···
683
683
}
684
684
685
685
/* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
686
-
count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);
686
+
count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
687
687
__flush_tlb();
688
688
689
689
/* Save MTRR state */
···
697
697
static void post_set(void) __releases(set_atomicity_lock)
698
698
{
699
699
/* Flush TLBs (no need to flush caches - they are disabled) */
700
-
count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);
700
+
count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
701
701
__flush_tlb();
702
702
703
703
/* Intel (P6) standard MTRRs */
+8
-1
arch/x86/kernel/irq.c
+8
-1
arch/x86/kernel/irq.c
···
266
266
EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
267
267
268
268
#ifdef CONFIG_HOTPLUG_CPU
269
+
270
+
/* These two declarations are only used in check_irq_vectors_for_cpu_disable()
271
+
* below, which is protected by stop_machine(). Putting them on the stack
272
+
* results in a stack frame overflow. Dynamically allocating could result in a
273
+
* failure so declare these two cpumasks as global.
274
+
*/
275
+
static struct cpumask affinity_new, online_new;
276
+
269
277
/*
270
278
* This cpu is going to be removed and its vectors migrated to the remaining
271
279
* online cpus. Check to see if there are enough vectors in the remaining cpus.
···
285
277
unsigned int this_cpu, vector, this_count, count;
286
278
struct irq_desc *desc;
287
279
struct irq_data *data;
288
-
struct cpumask affinity_new, online_new;
289
280
290
281
this_cpu = smp_processor_id();
291
282
cpumask_copy(&online_new, cpu_online_mask);
+37
arch/x86/kernel/quirks.c
+37
arch/x86/kernel/quirks.c
···
571
571
quirk_amd_nb_node);
572
572
573
573
#endif
574
+
575
+
#ifdef CONFIG_PCI
576
+
/*
577
+
* Processor does not ensure DRAM scrub read/write sequence
578
+
* is atomic wrt accesses to CC6 save state area. Therefore
579
+
* if a concurrent scrub read/write access is to same address
580
+
* the entry may appear as if it is not written. This quirk
581
+
* applies to Fam16h models 00h-0Fh
582
+
*
583
+
* See "Revision Guide" for AMD F16h models 00h-0fh,
584
+
* document 51810 rev. 3.04, Nov 2013
585
+
*/
586
+
static void amd_disable_seq_and_redirect_scrub(struct pci_dev *dev)
587
+
{
588
+
u32 val;
589
+
590
+
/*
591
+
* Suggested workaround:
592
+
* set D18F3x58[4:0] = 00h and set D18F3x5C[0] = 0b
593
+
*/
594
+
pci_read_config_dword(dev, 0x58, &val);
595
+
if (val & 0x1F) {
596
+
val &= ~(0x1F);
597
+
pci_write_config_dword(dev, 0x58, val);
598
+
}
599
+
600
+
pci_read_config_dword(dev, 0x5C, &val);
601
+
if (val & BIT(0)) {
602
+
val &= ~BIT(0);
603
+
pci_write_config_dword(dev, 0x5c, val);
604
+
}
605
+
}
606
+
607
+
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3,
608
+
amd_disable_seq_and_redirect_scrub);
609
+
610
+
#endif
+2
arch/x86/mm/numa_32.c
+2
arch/x86/mm/numa_32.c
···
52
52
nid, start, end);
53
53
printk(KERN_DEBUG " Setting physnode_map array to node %d for pfns:\n", nid);
54
54
printk(KERN_DEBUG " ");
55
+
start = round_down(start, PAGES_PER_SECTION);
56
+
end = round_up(end, PAGES_PER_SECTION);
55
57
for (pfn = start; pfn < end; pfn += PAGES_PER_SECTION) {
56
58
physnode_map[pfn / PAGES_PER_SECTION] = nid;
57
59
printk(KERN_CONT "%lx ", pfn);
+13
-3
arch/x86/mm/srat.c
+13
-3
arch/x86/mm/srat.c
···
42
42
return acpi_numa < 0;
43
43
}
44
44
45
-
/* Callback for SLIT parsing */
45
+
/*
46
+
* Callback for SLIT parsing. pxm_to_node() returns NUMA_NO_NODE for
47
+
* I/O localities since SRAT does not list them. I/O localities are
48
+
* not supported at this point.
49
+
*/
46
50
void __init acpi_numa_slit_init(struct acpi_table_slit *slit)
47
51
{
48
52
int i, j;
49
53
50
-
for (i = 0; i < slit->locality_count; i++)
51
-
for (j = 0; j < slit->locality_count; j++)
54
+
for (i = 0; i < slit->locality_count; i++) {
55
+
if (pxm_to_node(i) == NUMA_NO_NODE)
56
+
continue;
57
+
for (j = 0; j < slit->locality_count; j++) {
58
+
if (pxm_to_node(j) == NUMA_NO_NODE)
59
+
continue;
52
60
numa_set_distance(pxm_to_node(i), pxm_to_node(j),
53
61
slit->entry[slit->locality_count * i + j]);
62
+
}
63
+
}
54
64
}
55
65
56
66
/* Callback for Proximity Domain -> x2APIC mapping */
+13
-39
arch/x86/mm/tlb.c
+13
-39
arch/x86/mm/tlb.c
···
103
103
if (f->flush_mm != this_cpu_read(cpu_tlbstate.active_mm))
104
104
return;
105
105
106
-
count_vm_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
106
+
count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
107
107
if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
108
108
if (f->flush_end == TLB_FLUSH_ALL)
109
109
local_flush_tlb();
···
131
131
info.flush_start = start;
132
132
info.flush_end = end;
133
133
134
-
count_vm_event(NR_TLB_REMOTE_FLUSH);
134
+
count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
135
135
if (is_uv_system()) {
136
136
unsigned int cpu;
137
137
···
151
151
152
152
preempt_disable();
153
153
154
-
count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);
154
+
count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
155
155
local_flush_tlb();
156
156
if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
157
157
flush_tlb_others(mm_cpumask(mm), mm, 0UL, TLB_FLUSH_ALL);
158
158
preempt_enable();
159
-
}
160
-
161
-
/*
162
-
* It can find out the THP large page, or
163
-
* HUGETLB page in tlb_flush when THP disabled
164
-
*/
165
-
static inline unsigned long has_large_page(struct mm_struct *mm,
166
-
unsigned long start, unsigned long end)
167
-
{
168
-
pgd_t *pgd;
169
-
pud_t *pud;
170
-
pmd_t *pmd;
171
-
unsigned long addr = ALIGN(start, HPAGE_SIZE);
172
-
for (; addr < end; addr += HPAGE_SIZE) {
173
-
pgd = pgd_offset(mm, addr);
174
-
if (likely(!pgd_none(*pgd))) {
175
-
pud = pud_offset(pgd, addr);
176
-
if (likely(!pud_none(*pud))) {
177
-
pmd = pmd_offset(pud, addr);
178
-
if (likely(!pmd_none(*pmd)))
179
-
if (pmd_large(*pmd))
180
-
return addr;
181
-
}
182
-
}
183
-
}
184
-
return 0;
185
159
}
186
160
187
161
void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
···
163
189
{
164
190
unsigned long addr;
165
191
unsigned act_entries, tlb_entries = 0;
192
+
unsigned long nr_base_pages;
166
193
167
194
preempt_disable();
168
195
if (current->active_mm != mm)
···
185
210
tlb_entries = tlb_lli_4k[ENTRIES];
186
211
else
187
212
tlb_entries = tlb_lld_4k[ENTRIES];
213
+
188
214
/* Assume all of TLB entries was occupied by this task */
189
-
act_entries = mm->total_vm > tlb_entries ? tlb_entries : mm->total_vm;
215
+
act_entries = tlb_entries >> tlb_flushall_shift;
216
+
act_entries = mm->total_vm > act_entries ? act_entries : mm->total_vm;
217
+
nr_base_pages = (end - start) >> PAGE_SHIFT;
190
218
191
219
/* tlb_flushall_shift is on balance point, details in commit log */
192
-
if ((end - start) >> PAGE_SHIFT > act_entries >> tlb_flushall_shift) {
193
-
count_vm_event(NR_TLB_LOCAL_FLUSH_ALL);
220
+
if (nr_base_pages > act_entries) {
221
+
count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
194
222
local_flush_tlb();
195
223
} else {
196
-
if (has_large_page(mm, start, end)) {
197
-
local_flush_tlb();
198
-
goto flush_all;
199
-
}
200
224
/* flush range by one by one 'invlpg' */
201
225
for (addr = start; addr < end; addr += PAGE_SIZE) {
202
-
count_vm_event(NR_TLB_LOCAL_FLUSH_ONE);
226
+
count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
203
227
__flush_tlb_single(addr);
204
228
}
205
229
···
236
262
237
263
static void do_flush_tlb_all(void *info)
238
264
{
239
-
count_vm_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
265
+
count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
240
266
__flush_tlb_all();
241
267
if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
242
268
leave_mm(smp_processor_id());
···
244
270
245
271
void flush_tlb_all(void)
246
272
{
247
-
count_vm_event(NR_TLB_REMOTE_FLUSH);
273
+
count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
248
274
on_each_cpu(do_flush_tlb_all, NULL, 1);
249
275
}
250
276
+6
-4
arch/x86/platform/efi/efi-bgrt.c
+6
-4
arch/x86/platform/efi/efi-bgrt.c
···
49
49
50
50
image = efi_lookup_mapped_addr(bgrt_tab->image_address);
51
51
if (!image) {
52
-
image = ioremap(bgrt_tab->image_address, sizeof(bmp_header));
52
+
image = early_memremap(bgrt_tab->image_address,
53
+
sizeof(bmp_header));
53
54
ioremapped = true;
54
55
if (!image)
55
56
return;
···
58
57
59
58
memcpy_fromio(&bmp_header, image, sizeof(bmp_header));
60
59
if (ioremapped)
61
-
iounmap(image);
60
+
early_iounmap(image, sizeof(bmp_header));
62
61
bgrt_image_size = bmp_header.size;
63
62
64
63
bgrt_image = kmalloc(bgrt_image_size, GFP_KERNEL);
···
66
65
return;
67
66
68
67
if (ioremapped) {
69
-
image = ioremap(bgrt_tab->image_address, bmp_header.size);
68
+
image = early_memremap(bgrt_tab->image_address,
69
+
bmp_header.size);
70
70
if (!image) {
71
71
kfree(bgrt_image);
72
72
bgrt_image = NULL;
···
77
75
78
76
memcpy_fromio(bgrt_image, image, bgrt_image_size);
79
77
if (ioremapped)
80
-
iounmap(image);
78
+
early_iounmap(image, bmp_header.size);
81
79
}
+3
-1
include/linux/vm_event_item.h
+3
-1
include/linux/vm_event_item.h
···
71
71
THP_ZERO_PAGE_ALLOC,
72
72
THP_ZERO_PAGE_ALLOC_FAILED,
73
73
#endif
74
+
#ifdef CONFIG_DEBUG_TLBFLUSH
74
75
#ifdef CONFIG_SMP
75
76
NR_TLB_REMOTE_FLUSH, /* cpu tried to flush others' tlbs */
76
77
NR_TLB_REMOTE_FLUSH_RECEIVED,/* cpu received ipi for flush */
77
-
#endif
78
+
#endif /* CONFIG_SMP */
78
79
NR_TLB_LOCAL_FLUSH_ALL,
79
80
NR_TLB_LOCAL_FLUSH_ONE,
81
+
#endif /* CONFIG_DEBUG_TLBFLUSH */
80
82
NR_VM_EVENT_ITEMS
81
83
};
82
84
+8
include/linux/vmstat.h
+8
include/linux/vmstat.h
···
83
83
#define count_vm_numa_events(x, y) do { (void)(y); } while (0)
84
84
#endif /* CONFIG_NUMA_BALANCING */
85
85
86
+
#ifdef CONFIG_DEBUG_TLBFLUSH
87
+
#define count_vm_tlb_event(x) count_vm_event(x)
88
+
#define count_vm_tlb_events(x, y) count_vm_events(x, y)
89
+
#else
90
+
#define count_vm_tlb_event(x) do {} while (0)
91
+
#define count_vm_tlb_events(x, y) do { (void)(y); } while (0)
92
+
#endif
93
+
86
94
#define __count_zone_vm_events(item, zone, delta) \
87
95
__count_vm_events(item##_NORMAL - ZONE_NORMAL + \
88
96
zone_idx(zone), delta)
+1
lib/Makefile
+1
lib/Makefile
+3
-1
mm/vmstat.c
+3
-1
mm/vmstat.c
···
851
851
"thp_zero_page_alloc",
852
852
"thp_zero_page_alloc_failed",
853
853
#endif
854
+
#ifdef CONFIG_DEBUG_TLBFLUSH
854
855
#ifdef CONFIG_SMP
855
856
"nr_tlb_remote_flush",
856
857
"nr_tlb_remote_flush_received",
857
-
#endif
858
+
#endif /* CONFIG_SMP */
858
859
"nr_tlb_local_flush_all",
859
860
"nr_tlb_local_flush_one",
861
+
#endif /* CONFIG_DEBUG_TLBFLUSH */
860
862
861
863
#endif /* CONFIG_VM_EVENTS_COUNTERS */
862
864
};