tjh.dev / kernel
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clk: fsl-sai: Add i.MX8M support with 8 byte register offset

The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers
shifted by +8 bytes and requires additional bus clock. Add support for
the i.MX8M variant of the IP with this register shift and additional
clock.

Reviewed-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@nabladev.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Marek Vasut and committed by
Stephen Boyd c206085b d0a4d582

+25 -5
+1 -1
drivers/clk/Kconfig
··· 255 255 256 256 config COMMON_CLK_FSL_SAI 257 257 bool "Clock driver for BCLK of Freescale SAI cores" 258 - depends on ARCH_LAYERSCAPE || COMPILE_TEST 258 + depends on ARCH_LAYERSCAPE || ARCH_MXC || COMPILE_TEST 259 259 help 260 260 This driver supports the Freescale SAI (Synchronous Audio Interface) 261 261 to be used as a generic clock output. Some SoCs have restrictions
+24 -4
drivers/clk/clk-fsl-sai.c
··· 6 6 */ 7 7 8 8 #include <linux/clk-provider.h> 9 + #include <linux/clk.h> 9 10 #include <linux/err.h> 10 11 #include <linux/module.h> 11 12 #include <linux/of.h> ··· 21 20 #define CR2_DIV_SHIFT 0 22 21 #define CR2_DIV_WIDTH 8 23 22 23 + struct fsl_sai_data { 24 + unsigned int offset; /* Register offset */ 25 + }; 26 + 24 27 struct fsl_sai_clk { 25 28 struct clk_divider div; 26 29 struct clk_gate gate; ··· 34 29 static int fsl_sai_clk_probe(struct platform_device *pdev) 35 30 { 36 31 struct device *dev = &pdev->dev; 32 + const struct fsl_sai_data *data = device_get_match_data(dev); 37 33 struct fsl_sai_clk *sai_clk; 38 34 struct clk_parent_data pdata = { .index = 0 }; 35 + struct clk *clk_bus; 39 36 void __iomem *base; 40 37 struct clk_hw *hw; 41 38 ··· 49 42 if (IS_ERR(base)) 50 43 return PTR_ERR(base); 51 44 45 + clk_bus = devm_clk_get_optional_enabled(dev, "bus"); 46 + if (IS_ERR(clk_bus)) 47 + return PTR_ERR(clk_bus); 48 + 52 49 spin_lock_init(&sai_clk->lock); 53 50 54 - sai_clk->gate.reg = base + I2S_CSR; 51 + sai_clk->gate.reg = base + data->offset + I2S_CSR; 55 52 sai_clk->gate.bit_idx = CSR_BCE_BIT; 56 53 sai_clk->gate.lock = &sai_clk->lock; 57 54 58 - sai_clk->div.reg = base + I2S_CR2; 55 + sai_clk->div.reg = base + data->offset + I2S_CR2; 59 56 sai_clk->div.shift = CR2_DIV_SHIFT; 60 57 sai_clk->div.width = CR2_DIV_WIDTH; 61 58 sai_clk->div.lock = &sai_clk->lock; 62 59 63 60 /* set clock direction, we are the BCLK master */ 64 - writel(CR2_BCD, base + I2S_CR2); 61 + writel(CR2_BCD, base + data->offset + I2S_CR2); 65 62 66 63 hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name, 67 64 &pdata, 1, NULL, NULL, ··· 80 69 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 81 70 } 82 71 72 + static const struct fsl_sai_data fsl_sai_vf610_data = { 73 + .offset = 0, 74 + }; 75 + 76 + static const struct fsl_sai_data fsl_sai_imx8mq_data = { 77 + .offset = 8, 78 + }; 79 + 83 80 static const struct of_device_id of_fsl_sai_clk_ids[] = { 84 - { .compatible = "fsl,vf610-sai-clock" }, 81 + { .compatible = "fsl,vf610-sai-clock", .data = &fsl_sai_vf610_data }, 82 + { .compatible = "fsl,imx8mq-sai-clock", .data = &fsl_sai_imx8mq_data }, 85 83 { } 86 84 }; 87 85 MODULE_DEVICE_TABLE(of, of_fsl_sai_clk_ids);