+1 -1

tools/perf/Documentation/perf-config.txt

reviewed

··· 669 669 "$CLANG_OPTIONS $PERF_BPF_INC_OPTIONS $KERNEL_INC_OPTIONS " \ 670 670 "-Wno-unused-value -Wno-pointer-sign " \ 671 671 "-working-directory $WORKING_DIR " \ 672 672 - "-c \"$CLANG_SOURCE\" -target bpf $CLANG_EMIT_LLVM -O2 -o - $LLVM_OPTIONS_PIPE" 672 672 + "-c \"$CLANG_SOURCE\" --target=bpf $CLANG_EMIT_LLVM -O2 -o - $LLVM_OPTIONS_PIPE" 673 673 674 674 llvm.clang-opt:: 675 675 Options passed to clang.

+8

tools/perf/Documentation/perf-lock.txt

reviewed

··· 36 36 --input=<file>:: 37 37 Input file name. (default: perf.data unless stdin is a fifo) 38 38 39 39 + --output=<file>:: 40 40 + Output file name for perf lock contention and report. 41 41 + 39 42 -v:: 40 43 --verbose:: 41 44 Be more verbose (show symbol address, etc). ··· 202 199 Show lock contention only if the callstack contains the given string. 203 200 Note that it matches the substring so 'rq' would match both 'raw_spin_rq_lock' 204 201 and 'irq_enter_rcu'. 202 202 + 203 203 + -x:: 204 204 + --field-separator=<SEP>:: 205 205 + Show results using a CSV-style output to make it easy to import directly 206 206 + into spreadsheets. Columns are separated by the string specified in SEP. 205 207 206 208 207 209 SEE ALSO

+14 -3

tools/perf/Makefile.config

reviewed

··· 315 315 316 316 FEATURE_CHECK_LDFLAGS-libaio = -lrt 317 317 318 318 + FEATURE_CHECK_LDFLAGS-disassembler-four-args = -lbfd -lopcodes -ldl 319 319 + FEATURE_CHECK_LDFLAGS-disassembler-init-styled = -lbfd -lopcodes -ldl 320 320 + 318 321 CORE_CFLAGS += -fno-omit-frame-pointer 319 322 CORE_CFLAGS += -ggdb3 320 323 CORE_CFLAGS += -funwind-tables ··· 347 344 endif 348 345 349 346 ifeq ($(FEATURES_DUMP),) 350 350 - # We will display at the end of this Makefile.config, using $(call feature_display_entries), 351 351 - # as we may retry some feature detection here. 347 347 + # We will display at the end of this Makefile.config, using $(call feature_display_entries) 348 348 + # As we may retry some feature detection here, see the disassembler-four-args case, for instance 352 349 FEATURE_DISPLAY_DEFERRED := 1 353 350 include $(srctree)/tools/build/Makefile.feature 354 351 else ··· 683 680 CFLAGS += -DHAVE_BPF_SKEL 684 681 endif 685 682 683 683 + ifndef GEN_VMLINUX_H 684 684 + VMLINUX_H=$(src-perf)/util/bpf_skel/vmlinux/vmlinux.h 685 685 + endif 686 686 + 686 687 dwarf-post-unwind := 1 687 688 dwarf-post-unwind-text := BUG 688 689 ··· 910 903 911 904 ifeq ($(feature-libbfd-liberty), 1) 912 905 EXTLIBS += -lbfd -lopcodes -liberty 906 906 + FEATURE_CHECK_LDFLAGS-disassembler-four-args += -liberty -ldl 907 907 + FEATURE_CHECK_LDFLAGS-disassembler-init-styled += -liberty -ldl 913 908 else 914 909 ifeq ($(feature-libbfd-liberty-z), 1) 915 910 EXTLIBS += -lbfd -lopcodes -liberty -lz 911 911 + FEATURE_CHECK_LDFLAGS-disassembler-four-args += -liberty -lz -ldl 912 912 + FEATURE_CHECK_LDFLAGS-disassembler-init-styled += -liberty -lz -ldl 916 913 endif 917 914 endif 918 915 $(call feature_check,disassembler-four-args) ··· 1340 1329 1341 1330 # re-generate FEATURE-DUMP as we may have called feature_check, found out 1342 1331 # extra libraries to add to LDFLAGS of some other test and then redo those 1343 1343 - # tests. 1332 1332 + # tests, see the block about libbfd, disassembler-four-args, for instance. 1344 1333 $(shell rm -f $(FEATURE_DUMP_FILENAME)) 1345 1334 $(foreach feat,$(FEATURE_TESTS),$(shell echo "$(call feature_assign,$(feat))" >> $(FEATURE_DUMP_FILENAME)))

+42 -3

tools/perf/Makefile.perf

reviewed

··· 132 132 # Define EXTRA_TESTS to enable building extra tests useful mainly to perf 133 133 # developers, such as: 134 134 # x86 instruction decoder - new instructions test 135 135 + # 136 136 + # Define GEN_VMLINUX_H to generate vmlinux.h from the BTF. 135 137 136 138 # As per kernel Makefile, avoid funny character set dependencies 137 139 unexport LC_ALL ··· 199 197 BISON ?= bison 200 198 STRIP = strip 201 199 AWK = awk 200 200 + READELF ?= readelf 202 201 203 202 # include Makefile.config by default and rule out 204 203 # non-config cases ··· 1064 1061 ifdef BUILD_BPF_SKEL 1065 1062 BPFTOOL := $(SKEL_TMP_OUT)/bootstrap/bpftool 1066 1063 # Get Clang's default includes on this system, as opposed to those seen by 1067 1067 - # '-target bpf'. This fixes "missing" files on some architectures/distros, 1064 1064 + # '--target=bpf'. This fixes "missing" files on some architectures/distros, 1068 1065 # such as asm/byteorder.h, asm/socket.h, asm/sockios.h, sys/cdefs.h etc. 1069 1066 # 1070 1067 # Use '-idirafter': Don't interfere with include mechanics except where the ··· 1087 1084 $(Q)CFLAGS= $(MAKE) -C ../bpf/bpftool \ 1088 1085 OUTPUT=$(SKEL_TMP_OUT)/ bootstrap 1089 1086 1090 1090 - $(SKEL_TMP_OUT)/%.bpf.o: util/bpf_skel/%.bpf.c $(LIBBPF) | $(SKEL_TMP_OUT) 1091 1091 - $(QUIET_CLANG)$(CLANG) -g -O2 -target bpf -Wall -Werror $(BPF_INCLUDE) $(TOOLS_UAPI_INCLUDE) \ 1087 1087 + # Paths to search for a kernel to generate vmlinux.h from. 1088 1088 + VMLINUX_BTF_ELF_PATHS ?= $(if $(O),$(O)/vmlinux) \ 1089 1089 + $(if $(KBUILD_OUTPUT),$(KBUILD_OUTPUT)/vmlinux) \ 1090 1090 + ../../vmlinux \ 1091 1091 + /boot/vmlinux-$(shell uname -r) 1092 1092 + 1093 1093 + # Paths to BTF information. 1094 1094 + VMLINUX_BTF_BTF_PATHS ?= /sys/kernel/btf/vmlinux 1095 1095 + 1096 1096 + # Filter out kernels that don't exist or without a BTF section. 1097 1097 + VMLINUX_BTF_ELF_ABSPATHS ?= $(abspath $(wildcard $(VMLINUX_BTF_ELF_PATHS))) 1098 1098 + VMLINUX_BTF_PATHS ?= $(shell for file in $(VMLINUX_BTF_ELF_ABSPATHS); \ 1099 1099 + do \ 1100 1100 + if [ -f $$file ] && ($(READELF) -S "$$file" | grep -q .BTF); \ 1101 1101 + then \ 1102 1102 + echo "$$file"; \ 1103 1103 + fi; \ 1104 1104 + done) \ 1105 1105 + $(wildcard $(VMLINUX_BTF_BTF_PATHS)) 1106 1106 + 1107 1107 + # Select the first as the source of vmlinux.h. 1108 1108 + VMLINUX_BTF ?= $(firstword $(VMLINUX_BTF_PATHS)) 1109 1109 + 1110 1110 + ifeq ($(VMLINUX_H),) 1111 1111 + ifeq ($(VMLINUX_BTF),) 1112 1112 + $(error Missing bpftool input for generating vmlinux.h) 1113 1113 + endif 1114 1114 + endif 1115 1115 + 1116 1116 + $(SKEL_OUT)/vmlinux.h: $(VMLINUX_BTF) $(BPFTOOL) 1117 1117 + ifeq ($(VMLINUX_H),) 1118 1118 + $(QUIET_GEN)$(BPFTOOL) btf dump file $< format c > $@ 1119 1119 + else 1120 1120 + $(Q)cp "$(VMLINUX_H)" $@ 1121 1121 + endif 1122 1122 + 1123 1123 + $(SKEL_TMP_OUT)/%.bpf.o: util/bpf_skel/%.bpf.c $(LIBBPF) $(SKEL_OUT)/vmlinux.h | $(SKEL_TMP_OUT) 1124 1124 + $(QUIET_CLANG)$(CLANG) -g -O2 --target=bpf -Wall -Werror $(BPF_INCLUDE) $(TOOLS_UAPI_INCLUDE) \ 1092 1125 -c $(filter util/bpf_skel/%.bpf.c,$^) -o $@ 1093 1126 1094 1127 $(SKEL_OUT)/%.skel.h: $(SKEL_TMP_OUT)/%.bpf.o | $(BPFTOOL)

+20

tools/perf/arch/x86/util/evsel.c

reviewed

··· 102 102 } 103 103 } 104 104 } 105 105 + 106 106 + int arch_evsel__open_strerror(struct evsel *evsel, char *msg, size_t size) 107 107 + { 108 108 + if (!x86__is_amd_cpu()) 109 109 + return 0; 110 110 + 111 111 + if (!evsel->core.attr.precise_ip && 112 112 + !(evsel->pmu_name && !strncmp(evsel->pmu_name, "ibs", 3))) 113 113 + return 0; 114 114 + 115 115 + /* More verbose IBS errors. */ 116 116 + if (evsel->core.attr.exclude_kernel || evsel->core.attr.exclude_user || 117 117 + evsel->core.attr.exclude_hv || evsel->core.attr.exclude_idle || 118 118 + evsel->core.attr.exclude_host || evsel->core.attr.exclude_guest) { 119 119 + return scnprintf(msg, size, "AMD IBS doesn't support privilege filtering. Try " 120 120 + "again without the privilege modifiers (like 'k') at the end."); 121 121 + } 122 122 + 123 123 + return 0; 124 124 + }

+1 -1

tools/perf/builtin-daemon.c

reviewed

··· 1524 1524 if (argc) { 1525 1525 if (!strcmp(argv[0], "start")) 1526 1526 ret = __cmd_start(&__daemon, daemon_options, argc, argv); 1527 1527 - if (!strcmp(argv[0], "signal")) 1527 1527 + else if (!strcmp(argv[0], "signal")) 1528 1528 ret = __cmd_signal(&__daemon, daemon_options, argc, argv); 1529 1529 else if (!strcmp(argv[0], "stop")) 1530 1530 ret = __cmd_stop(&__daemon, daemon_options, argc, argv);

-1

tools/perf/builtin-kallsyms.c

reviewed

··· 62 62 if (argc < 1) 63 63 usage_with_options(kallsyms_usage, options); 64 64 65 65 - symbol_conf.sort_by_name = true; 66 65 symbol_conf.try_vmlinux_path = (symbol_conf.vmlinux_name == NULL); 67 66 if (symbol__init(NULL) < 0) 68 67 return -1;

+287 -98

tools/perf/builtin-lock.c

reviewed

··· 27 27 #include "util/map.h" 28 28 #include "util/util.h" 29 29 30 30 + #include <stdio.h> 30 31 #include <sys/types.h> 31 32 #include <sys/prctl.h> 32 33 #include <semaphore.h> ··· 66 65 static int stack_skip = CONTENTION_STACK_SKIP; 67 66 static int print_nr_entries = INT_MAX / 2; 68 67 static LIST_HEAD(callstack_filters); 68 68 + static const char *output_name = NULL; 69 69 + static FILE *lock_output; 69 70 70 71 struct callstack_filter { 71 72 struct list_head list; ··· 228 225 { 0, NULL }, 229 226 }; 230 227 228 228 + /* for CSV output */ 229 229 + if (len == 0) { 230 230 + fprintf(lock_output, "%llu", nsec); 231 231 + return; 232 232 + } 233 233 + 231 234 for (int i = 0; table[i].unit; i++) { 232 235 if (nsec < table[i].base) 233 236 continue; 234 237 235 235 - pr_info("%*.2f %s", len - 3, nsec / table[i].base, table[i].unit); 238 238 + fprintf(lock_output, "%*.2f %s", len - 3, nsec / table[i].base, table[i].unit); 236 239 return; 237 240 } 238 241 239 239 - pr_info("%*llu %s", len - 3, nsec, "ns"); 242 242 + fprintf(lock_output, "%*llu %s", len - 3, nsec, "ns"); 240 243 } 241 244 242 245 #define PRINT_KEY(member) \ 243 246 static void lock_stat_key_print_ ## member(struct lock_key *key, \ 244 247 struct lock_stat *ls) \ 245 248 { \ 246 246 - pr_info("%*llu", key->len, (unsigned long long)ls->member); \ 249 249 + fprintf(lock_output, "%*llu", key->len, (unsigned long long)ls->member);\ 247 250 } 248 251 249 252 #define PRINT_TIME(member) \ ··· 1338 1329 if (quiet || total == 0 || (broken == 0 && verbose <= 0)) 1339 1330 return; 1340 1331 1341 1341 - pr_info("\n=== output for debug ===\n\n"); 1342 1342 - pr_info("bad: %d, total: %d\n", bad, total); 1343 1343 - pr_info("bad rate: %.2f %%\n", (double)bad / (double)total * 100); 1344 1344 - pr_info("histogram of events caused bad sequence\n"); 1332 1332 + fprintf(lock_output, "\n=== output for debug ===\n\n"); 1333 1333 + fprintf(lock_output, "bad: %d, total: %d\n", bad, total); 1334 1334 + fprintf(lock_output, "bad rate: %.2f %%\n", (double)bad / (double)total * 100); 1335 1335 + fprintf(lock_output, "histogram of events caused bad sequence\n"); 1345 1336 for (i = 0; i < BROKEN_MAX; i++) 1346 1346 - pr_info(" %10s: %d\n", name[i], bad_hist[i]); 1337 1337 + fprintf(lock_output, " %10s: %d\n", name[i], bad_hist[i]); 1347 1338 } 1348 1339 1349 1340 /* TODO: various way to print, coloring, nano or milli sec */ ··· 1355 1346 int bad, total, printed; 1356 1347 1357 1348 if (!quiet) { 1358 1358 - pr_info("%20s ", "Name"); 1349 1349 + fprintf(lock_output, "%20s ", "Name"); 1359 1350 list_for_each_entry(key, &lock_keys, list) 1360 1360 - pr_info("%*s ", key->len, key->header); 1361 1361 - pr_info("\n\n"); 1351 1351 + fprintf(lock_output, "%*s ", key->len, key->header); 1352 1352 + fprintf(lock_output, "\n\n"); 1362 1353 } 1363 1354 1364 1355 bad = total = printed = 0; ··· 1383 1374 name = thread__comm_str(t); 1384 1375 } 1385 1376 1386 1386 - pr_info("%20s ", name); 1377 1377 + fprintf(lock_output, "%20s ", name); 1387 1378 } else { 1388 1379 strncpy(cut_name, st->name, 16); 1389 1380 cut_name[16] = '.'; ··· 1391 1382 cut_name[18] = '.'; 1392 1383 cut_name[19] = '\0'; 1393 1384 /* cut off name for saving output style */ 1394 1394 - pr_info("%20s ", cut_name); 1385 1385 + fprintf(lock_output, "%20s ", cut_name); 1395 1386 } 1396 1387 1397 1388 list_for_each_entry(key, &lock_keys, list) { 1398 1389 key->print(key, st); 1399 1399 - pr_info(" "); 1390 1390 + fprintf(lock_output, " "); 1400 1391 } 1401 1401 - pr_info("\n"); 1392 1392 + fprintf(lock_output, "\n"); 1402 1393 1403 1394 if (++printed >= print_nr_entries) 1404 1395 break; ··· 1415 1406 struct rb_node *node; 1416 1407 struct thread *t; 1417 1408 1418 1418 - pr_info("%10s: comm\n", "Thread ID"); 1409 1409 + fprintf(lock_output, "%10s: comm\n", "Thread ID"); 1419 1410 1420 1411 node = rb_first(&thread_stats); 1421 1412 while (node) { 1422 1413 st = container_of(node, struct thread_stat, rb); 1423 1414 t = perf_session__findnew(session, st->tid); 1424 1424 - pr_info("%10d: %s\n", st->tid, thread__comm_str(t)); 1415 1415 + fprintf(lock_output, "%10d: %s\n", st->tid, thread__comm_str(t)); 1425 1416 node = rb_next(node); 1426 1417 thread__put(t); 1427 1418 } ··· 1447 1438 unsigned int i; 1448 1439 struct lock_stat *st; 1449 1440 1450 1450 - pr_info("Address of instance: name of class\n"); 1441 1441 + fprintf(lock_output, "Address of instance: name of class\n"); 1451 1442 for (i = 0; i < LOCKHASH_SIZE; i++) { 1452 1443 hlist_for_each_entry(st, &lockhash_table[i], hash_entry) { 1453 1444 insert_to_result(st, compare_maps); ··· 1455 1446 } 1456 1447 1457 1448 while ((st = pop_from_result())) 1458 1458 - pr_info(" %#llx: %s\n", (unsigned long long)st->addr, st->name); 1449 1449 + fprintf(lock_output, " %#llx: %s\n", (unsigned long long)st->addr, st->name); 1459 1450 } 1460 1451 1461 1452 static int dump_info(void) ··· 1635 1626 sort_result(); 1636 1627 } 1637 1628 1638 1638 - static void print_bpf_events(int total, struct lock_contention_fails *fails) 1629 1629 + static void print_header_stdio(void) 1630 1630 + { 1631 1631 + struct lock_key *key; 1632 1632 + 1633 1633 + list_for_each_entry(key, &lock_keys, list) 1634 1634 + fprintf(lock_output, "%*s ", key->len, key->header); 1635 1635 + 1636 1636 + switch (aggr_mode) { 1637 1637 + case LOCK_AGGR_TASK: 1638 1638 + fprintf(lock_output, " %10s %s\n\n", "pid", 1639 1639 + show_lock_owner ? "owner" : "comm"); 1640 1640 + break; 1641 1641 + case LOCK_AGGR_CALLER: 1642 1642 + fprintf(lock_output, " %10s %s\n\n", "type", "caller"); 1643 1643 + break; 1644 1644 + case LOCK_AGGR_ADDR: 1645 1645 + fprintf(lock_output, " %16s %s\n\n", "address", "symbol"); 1646 1646 + break; 1647 1647 + default: 1648 1648 + break; 1649 1649 + } 1650 1650 + } 1651 1651 + 1652 1652 + static void print_header_csv(const char *sep) 1653 1653 + { 1654 1654 + struct lock_key *key; 1655 1655 + 1656 1656 + fprintf(lock_output, "# output: "); 1657 1657 + list_for_each_entry(key, &lock_keys, list) 1658 1658 + fprintf(lock_output, "%s%s ", key->header, sep); 1659 1659 + 1660 1660 + switch (aggr_mode) { 1661 1661 + case LOCK_AGGR_TASK: 1662 1662 + fprintf(lock_output, "%s%s %s\n", "pid", sep, 1663 1663 + show_lock_owner ? "owner" : "comm"); 1664 1664 + break; 1665 1665 + case LOCK_AGGR_CALLER: 1666 1666 + fprintf(lock_output, "%s%s %s", "type", sep, "caller"); 1667 1667 + if (verbose > 0) 1668 1668 + fprintf(lock_output, "%s %s", sep, "stacktrace"); 1669 1669 + fprintf(lock_output, "\n"); 1670 1670 + break; 1671 1671 + case LOCK_AGGR_ADDR: 1672 1672 + fprintf(lock_output, "%s%s %s%s %s\n", "address", sep, "symbol", sep, "type"); 1673 1673 + break; 1674 1674 + default: 1675 1675 + break; 1676 1676 + } 1677 1677 + } 1678 1678 + 1679 1679 + static void print_header(void) 1680 1680 + { 1681 1681 + if (!quiet) { 1682 1682 + if (symbol_conf.field_sep) 1683 1683 + print_header_csv(symbol_conf.field_sep); 1684 1684 + else 1685 1685 + print_header_stdio(); 1686 1686 + } 1687 1687 + } 1688 1688 + 1689 1689 + static void print_lock_stat_stdio(struct lock_contention *con, struct lock_stat *st) 1690 1690 + { 1691 1691 + struct lock_key *key; 1692 1692 + struct thread *t; 1693 1693 + int pid; 1694 1694 + 1695 1695 + list_for_each_entry(key, &lock_keys, list) { 1696 1696 + key->print(key, st); 1697 1697 + fprintf(lock_output, " "); 1698 1698 + } 1699 1699 + 1700 1700 + switch (aggr_mode) { 1701 1701 + case LOCK_AGGR_CALLER: 1702 1702 + fprintf(lock_output, " %10s %s\n", get_type_str(st->flags), st->name); 1703 1703 + break; 1704 1704 + case LOCK_AGGR_TASK: 1705 1705 + pid = st->addr; 1706 1706 + t = perf_session__findnew(session, pid); 1707 1707 + fprintf(lock_output, " %10d %s\n", 1708 1708 + pid, pid == -1 ? "Unknown" : thread__comm_str(t)); 1709 1709 + break; 1710 1710 + case LOCK_AGGR_ADDR: 1711 1711 + fprintf(lock_output, " %016llx %s (%s)\n", (unsigned long long)st->addr, 1712 1712 + st->name, get_type_name(st->flags)); 1713 1713 + break; 1714 1714 + default: 1715 1715 + break; 1716 1716 + } 1717 1717 + 1718 1718 + if (aggr_mode == LOCK_AGGR_CALLER && verbose > 0) { 1719 1719 + struct map *kmap; 1720 1720 + struct symbol *sym; 1721 1721 + char buf[128]; 1722 1722 + u64 ip; 1723 1723 + 1724 1724 + for (int i = 0; i < max_stack_depth; i++) { 1725 1725 + if (!st->callstack || !st->callstack[i]) 1726 1726 + break; 1727 1727 + 1728 1728 + ip = st->callstack[i]; 1729 1729 + sym = machine__find_kernel_symbol(con->machine, ip, &kmap); 1730 1730 + get_symbol_name_offset(kmap, sym, ip, buf, sizeof(buf)); 1731 1731 + fprintf(lock_output, "\t\t\t%#lx %s\n", (unsigned long)ip, buf); 1732 1732 + } 1733 1733 + } 1734 1734 + } 1735 1735 + 1736 1736 + static void print_lock_stat_csv(struct lock_contention *con, struct lock_stat *st, 1737 1737 + const char *sep) 1738 1738 + { 1739 1739 + struct lock_key *key; 1740 1740 + struct thread *t; 1741 1741 + int pid; 1742 1742 + 1743 1743 + list_for_each_entry(key, &lock_keys, list) { 1744 1744 + key->print(key, st); 1745 1745 + fprintf(lock_output, "%s ", sep); 1746 1746 + } 1747 1747 + 1748 1748 + switch (aggr_mode) { 1749 1749 + case LOCK_AGGR_CALLER: 1750 1750 + fprintf(lock_output, "%s%s %s", get_type_str(st->flags), sep, st->name); 1751 1751 + if (verbose <= 0) 1752 1752 + fprintf(lock_output, "\n"); 1753 1753 + break; 1754 1754 + case LOCK_AGGR_TASK: 1755 1755 + pid = st->addr; 1756 1756 + t = perf_session__findnew(session, pid); 1757 1757 + fprintf(lock_output, "%d%s %s\n", pid, sep, 1758 1758 + pid == -1 ? "Unknown" : thread__comm_str(t)); 1759 1759 + break; 1760 1760 + case LOCK_AGGR_ADDR: 1761 1761 + fprintf(lock_output, "%llx%s %s%s %s\n", (unsigned long long)st->addr, sep, 1762 1762 + st->name, sep, get_type_name(st->flags)); 1763 1763 + break; 1764 1764 + default: 1765 1765 + break; 1766 1766 + } 1767 1767 + 1768 1768 + if (aggr_mode == LOCK_AGGR_CALLER && verbose > 0) { 1769 1769 + struct map *kmap; 1770 1770 + struct symbol *sym; 1771 1771 + char buf[128]; 1772 1772 + u64 ip; 1773 1773 + 1774 1774 + for (int i = 0; i < max_stack_depth; i++) { 1775 1775 + if (!st->callstack || !st->callstack[i]) 1776 1776 + break; 1777 1777 + 1778 1778 + ip = st->callstack[i]; 1779 1779 + sym = machine__find_kernel_symbol(con->machine, ip, &kmap); 1780 1780 + get_symbol_name_offset(kmap, sym, ip, buf, sizeof(buf)); 1781 1781 + fprintf(lock_output, "%s %#lx %s", i ? ":" : sep, (unsigned long) ip, buf); 1782 1782 + } 1783 1783 + fprintf(lock_output, "\n"); 1784 1784 + } 1785 1785 + } 1786 1786 + 1787 1787 + static void print_lock_stat(struct lock_contention *con, struct lock_stat *st) 1788 1788 + { 1789 1789 + if (symbol_conf.field_sep) 1790 1790 + print_lock_stat_csv(con, st, symbol_conf.field_sep); 1791 1791 + else 1792 1792 + print_lock_stat_stdio(con, st); 1793 1793 + } 1794 1794 + 1795 1795 + static void print_footer_stdio(int total, int bad, struct lock_contention_fails *fails) 1639 1796 { 1640 1797 /* Output for debug, this have to be removed */ 1641 1798 int broken = fails->task + fails->stack + fails->time + fails->data; 1799 1799 + 1800 1800 + if (!use_bpf) 1801 1801 + print_bad_events(bad, total); 1642 1802 1643 1803 if (quiet || total == 0 || (broken == 0 && verbose <= 0)) 1644 1804 return; 1645 1805 1646 1806 total += broken; 1647 1647 - pr_info("\n=== output for debug ===\n\n"); 1648 1648 - pr_info("bad: %d, total: %d\n", broken, total); 1649 1649 - pr_info("bad rate: %.2f %%\n", (double)broken / (double)total * 100); 1807 1807 + fprintf(lock_output, "\n=== output for debug ===\n\n"); 1808 1808 + fprintf(lock_output, "bad: %d, total: %d\n", broken, total); 1809 1809 + fprintf(lock_output, "bad rate: %.2f %%\n", 100.0 * broken / total); 1650 1810 1651 1651 - pr_info("histogram of failure reasons\n"); 1652 1652 - pr_info(" %10s: %d\n", "task", fails->task); 1653 1653 - pr_info(" %10s: %d\n", "stack", fails->stack); 1654 1654 - pr_info(" %10s: %d\n", "time", fails->time); 1655 1655 - pr_info(" %10s: %d\n", "data", fails->data); 1811 1811 + fprintf(lock_output, "histogram of failure reasons\n"); 1812 1812 + fprintf(lock_output, " %10s: %d\n", "task", fails->task); 1813 1813 + fprintf(lock_output, " %10s: %d\n", "stack", fails->stack); 1814 1814 + fprintf(lock_output, " %10s: %d\n", "time", fails->time); 1815 1815 + fprintf(lock_output, " %10s: %d\n", "data", fails->data); 1816 1816 + } 1817 1817 + 1818 1818 + static void print_footer_csv(int total, int bad, struct lock_contention_fails *fails, 1819 1819 + const char *sep) 1820 1820 + { 1821 1821 + /* Output for debug, this have to be removed */ 1822 1822 + if (use_bpf) 1823 1823 + bad = fails->task + fails->stack + fails->time + fails->data; 1824 1824 + 1825 1825 + if (quiet || total == 0 || (bad == 0 && verbose <= 0)) 1826 1826 + return; 1827 1827 + 1828 1828 + total += bad; 1829 1829 + fprintf(lock_output, "# debug: total=%d%s bad=%d", total, sep, bad); 1830 1830 + 1831 1831 + if (use_bpf) { 1832 1832 + fprintf(lock_output, "%s bad_%s=%d", sep, "task", fails->task); 1833 1833 + fprintf(lock_output, "%s bad_%s=%d", sep, "stack", fails->stack); 1834 1834 + fprintf(lock_output, "%s bad_%s=%d", sep, "time", fails->time); 1835 1835 + fprintf(lock_output, "%s bad_%s=%d", sep, "data", fails->data); 1836 1836 + } else { 1837 1837 + int i; 1838 1838 + const char *name[4] = { "acquire", "acquired", "contended", "release" }; 1839 1839 + 1840 1840 + for (i = 0; i < BROKEN_MAX; i++) 1841 1841 + fprintf(lock_output, "%s bad_%s=%d", sep, name[i], bad_hist[i]); 1842 1842 + } 1843 1843 + fprintf(lock_output, "\n"); 1844 1844 + } 1845 1845 + 1846 1846 + static void print_footer(int total, int bad, struct lock_contention_fails *fails) 1847 1847 + { 1848 1848 + if (symbol_conf.field_sep) 1849 1849 + print_footer_csv(total, bad, fails, symbol_conf.field_sep); 1850 1850 + else 1851 1851 + print_footer_stdio(total, bad, fails); 1656 1852 } 1657 1853 1658 1854 static void print_contention_result(struct lock_contention *con) 1659 1855 { 1660 1856 struct lock_stat *st; 1661 1661 - struct lock_key *key; 1662 1857 int bad, total, printed; 1663 1858 1664 1664 - if (!quiet) { 1665 1665 - list_for_each_entry(key, &lock_keys, list) 1666 1666 - pr_info("%*s ", key->len, key->header); 1667 1667 - 1668 1668 - switch (aggr_mode) { 1669 1669 - case LOCK_AGGR_TASK: 1670 1670 - pr_info(" %10s %s\n\n", "pid", 1671 1671 - show_lock_owner ? "owner" : "comm"); 1672 1672 - break; 1673 1673 - case LOCK_AGGR_CALLER: 1674 1674 - pr_info(" %10s %s\n\n", "type", "caller"); 1675 1675 - break; 1676 1676 - case LOCK_AGGR_ADDR: 1677 1677 - pr_info(" %16s %s\n\n", "address", "symbol"); 1678 1678 - break; 1679 1679 - default: 1680 1680 - break; 1681 1681 - } 1682 1682 - } 1859 1859 + if (!quiet) 1860 1860 + print_header(); 1683 1861 1684 1862 bad = total = printed = 0; 1685 1863 1686 1864 while ((st = pop_from_result())) { 1687 1687 - struct thread *t; 1688 1688 - int pid; 1689 1689 - 1690 1865 total += use_bpf ? st->nr_contended : 1; 1691 1866 if (st->broken) 1692 1867 bad++; ··· 1878 1685 if (!st->wait_time_total) 1879 1686 continue; 1880 1687 1881 1881 - list_for_each_entry(key, &lock_keys, list) { 1882 1882 - key->print(key, st); 1883 1883 - pr_info(" "); 1884 1884 - } 1885 1885 - 1886 1886 - switch (aggr_mode) { 1887 1887 - case LOCK_AGGR_CALLER: 1888 1888 - pr_info(" %10s %s\n", get_type_str(st->flags), st->name); 1889 1889 - break; 1890 1890 - case LOCK_AGGR_TASK: 1891 1891 - pid = st->addr; 1892 1892 - t = perf_session__findnew(session, pid); 1893 1893 - pr_info(" %10d %s\n", 1894 1894 - pid, pid == -1 ? "Unknown" : thread__comm_str(t)); 1895 1895 - break; 1896 1896 - case LOCK_AGGR_ADDR: 1897 1897 - pr_info(" %016llx %s (%s)\n", (unsigned long long)st->addr, 1898 1898 - st->name, get_type_name(st->flags)); 1899 1899 - break; 1900 1900 - default: 1901 1901 - break; 1902 1902 - } 1903 1903 - 1904 1904 - if (aggr_mode == LOCK_AGGR_CALLER && verbose > 0) { 1905 1905 - struct map *kmap; 1906 1906 - struct symbol *sym; 1907 1907 - char buf[128]; 1908 1908 - u64 ip; 1909 1909 - 1910 1910 - for (int i = 0; i < max_stack_depth; i++) { 1911 1911 - if (!st->callstack || !st->callstack[i]) 1912 1912 - break; 1913 1913 - 1914 1914 - ip = st->callstack[i]; 1915 1915 - sym = machine__find_kernel_symbol(con->machine, ip, &kmap); 1916 1916 - get_symbol_name_offset(kmap, sym, ip, buf, sizeof(buf)); 1917 1917 - pr_info("\t\t\t%#lx %s\n", (unsigned long)ip, buf); 1918 1918 - } 1919 1919 - } 1688 1688 + print_lock_stat(con, st); 1920 1689 1921 1690 if (++printed >= print_nr_entries) 1922 1691 break; ··· 1895 1740 /* some entries are collected but hidden by the callstack filter */ 1896 1741 total += con->nr_filtered; 1897 1742 1898 1898 - if (use_bpf) 1899 1899 - print_bpf_events(total, &con->fails); 1900 1900 - else 1901 1901 - print_bad_events(bad, total); 1743 1743 + print_footer(total, bad, &con->fails); 1902 1744 } 1903 1745 1904 1746 static bool force; ··· 1925 1773 return PTR_ERR(session); 1926 1774 } 1927 1775 1928 1928 - /* for lock function check */ 1929 1929 - symbol_conf.sort_by_name = true; 1930 1776 symbol_conf.allow_aliases = true; 1931 1777 symbol__init(&session->header.env); 1932 1778 ··· 1999 1849 return -1; 2000 1850 } 2001 1851 1852 1852 + if (symbol_conf.field_sep) { 1853 1853 + if (strstr(symbol_conf.field_sep, ":") || /* part of type flags */ 1854 1854 + strstr(symbol_conf.field_sep, "+") || /* part of caller offset */ 1855 1855 + strstr(symbol_conf.field_sep, ".")) { /* can be in a symbol name */ 1856 1856 + pr_err("Cannot use the separator that is already used\n"); 1857 1857 + parse_options_usage(usage, options, "x", 1); 1858 1858 + return -1; 1859 1859 + } 1860 1860 + } 1861 1861 + 2002 1862 if (show_lock_owner) 2003 1863 show_thread_stats = true; 2004 1864 ··· 2063 1903 if (con.aggr_mode == LOCK_AGGR_CALLER) 2064 1904 con.save_callstack = true; 2065 1905 2066 2066 - /* for lock function check */ 2067 2067 - symbol_conf.sort_by_name = true; 2068 1906 symbol_conf.allow_aliases = true; 2069 1907 symbol__init(&session->header.env); 2070 1908 ··· 2123 1965 2124 1966 if (select_key(true)) 2125 1967 goto out_delete; 1968 1968 + 1969 1969 + if (symbol_conf.field_sep) { 1970 1970 + int i; 1971 1971 + struct lock_key *keys = contention_keys; 1972 1972 + 1973 1973 + /* do not align output in CSV format */ 1974 1974 + for (i = 0; keys[i].name; i++) 1975 1975 + keys[i].len = 0; 1976 1976 + } 2126 1977 2127 1978 if (use_bpf) { 2128 1979 lock_contention_start(); ··· 2431 2264 return ret; 2432 2265 } 2433 2266 2267 2267 + static int parse_output(const struct option *opt __maybe_unused, const char *str, 2268 2268 + int unset __maybe_unused) 2269 2269 + { 2270 2270 + const char **name = (const char **)opt->value; 2271 2271 + 2272 2272 + if (str == NULL) 2273 2273 + return -1; 2274 2274 + 2275 2275 + lock_output = fopen(str, "w"); 2276 2276 + if (lock_output == NULL) { 2277 2277 + pr_err("Cannot open %s\n", str); 2278 2278 + return -1; 2279 2279 + } 2280 2280 + 2281 2281 + *name = str; 2282 2282 + return 0; 2283 2283 + } 2284 2284 + 2434 2285 int cmd_lock(int argc, const char **argv) 2435 2286 { 2436 2287 const struct option lock_options[] = { 2437 2288 OPT_STRING('i', "input", &input_name, "file", "input file name"), 2289 2289 + OPT_CALLBACK(0, "output", &output_name, "file", "output file name", parse_output), 2438 2290 OPT_INCR('v', "verbose", &verbose, "be more verbose (show symbol address, etc)"), 2439 2291 OPT_BOOLEAN('D', "dump-raw-trace", &dump_trace, "dump raw trace in ASCII"), 2440 2292 OPT_BOOLEAN('f', "force", &force, "don't complain, do it"), ··· 2520 2334 OPT_CALLBACK('S', "callstack-filter", NULL, "NAMES", 2521 2335 "Filter specific function in the callstack", parse_call_stack), 2522 2336 OPT_BOOLEAN('o', "lock-owner", &show_lock_owner, "show lock owners instead of waiters"), 2337 2337 + OPT_STRING_NOEMPTY('x', "field-separator", &symbol_conf.field_sep, "separator", 2338 2338 + "print result in CSV format with custom separator"), 2523 2339 OPT_PARENT(lock_options) 2524 2340 }; 2525 2341 ··· 2553 2365 for (i = 0; i < LOCKHASH_SIZE; i++) 2554 2366 INIT_HLIST_HEAD(lockhash_table + i); 2555 2367 2368 2368 + lock_output = stderr; 2556 2369 argc = parse_options_subcommand(argc, argv, lock_options, lock_subcommands, 2557 2370 lock_usage, PARSE_OPT_STOP_AT_NON_OPTION); 2558 2371 if (!argc)

-1

tools/perf/builtin-report.c

reviewed

··· 1676 1676 * See symbol__browser_index. 1677 1677 */ 1678 1678 symbol_conf.priv_size += sizeof(u32); 1679 1679 - symbol_conf.sort_by_name = true; 1680 1679 } 1681 1680 annotation_config__init(&report.annotation_opts); 1682 1681 }

+4 -4

tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json

reviewed

··· 92 92 }, 93 93 { 94 94 "BriefDescription": "Percentage of cycles in aborted transactions.", 95 95 - "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", 95 95 + "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)", 96 96 "MetricGroup": "transaction", 97 97 "MetricName": "tsx_aborted_cycles", 98 98 "ScaleUnit": "100%" 99 99 }, 100 100 { 101 101 "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", 102 102 - "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", 102 102 + "MetricExpr": "(cycles\\-t / el\\-start if has_event(cycles\\-t) else 0)", 103 103 "MetricGroup": "transaction", 104 104 "MetricName": "tsx_cycles_per_elision", 105 105 "ScaleUnit": "1cycles / elision" 106 106 }, 107 107 { 108 108 "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", 109 109 - "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", 109 109 + "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)", 110 110 "MetricGroup": "transaction", 111 111 "MetricName": "tsx_cycles_per_transaction", 112 112 "ScaleUnit": "1cycles / transaction" 113 113 }, 114 114 { 115 115 "BriefDescription": "Percentage of cycles within a transaction region.", 116 116 - "MetricExpr": "cpu@cycles\\-t@ / cycles", 116 116 + "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)", 117 117 "MetricGroup": "transaction", 118 118 "MetricName": "tsx_transactional_cycles", 119 119 "ScaleUnit": "100%"

+4 -4

tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json

reviewed

··· 1830 1830 }, 1831 1831 { 1832 1832 "BriefDescription": "Percentage of cycles in aborted transactions.", 1833 1833 - "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", 1833 1833 + "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)", 1834 1834 "MetricGroup": "transaction", 1835 1835 "MetricName": "tsx_aborted_cycles", 1836 1836 "ScaleUnit": "100%" 1837 1837 }, 1838 1838 { 1839 1839 "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", 1840 1840 - "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", 1840 1840 + "MetricExpr": "(cycles\\-t / el\\-start if has_event(cycles\\-t) else 0)", 1841 1841 "MetricGroup": "transaction", 1842 1842 "MetricName": "tsx_cycles_per_elision", 1843 1843 "ScaleUnit": "1cycles / elision" 1844 1844 }, 1845 1845 { 1846 1846 "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", 1847 1847 - "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", 1847 1847 + "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)", 1848 1848 "MetricGroup": "transaction", 1849 1849 "MetricName": "tsx_cycles_per_transaction", 1850 1850 "ScaleUnit": "1cycles / transaction" 1851 1851 }, 1852 1852 { 1853 1853 "BriefDescription": "Percentage of cycles within a transaction region.", 1854 1854 - "MetricExpr": "cpu@cycles\\-t@ / cycles", 1854 1854 + "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)", 1855 1855 "MetricGroup": "transaction", 1856 1856 "MetricName": "tsx_transactional_cycles", 1857 1857 "ScaleUnit": "100%"

+38 -5

tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json

reviewed

··· 8 8 "UMask": "0x1" 9 9 }, 10 10 { 11 11 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]", 12 12 + "EventCode": "0x87", 13 13 + "EventName": "DECODE.LCP", 14 14 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]", 15 15 + "SampleAfterValue": "2000003", 16 16 + "UMask": "0x1" 17 17 + }, 18 18 + { 11 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 12 20 "EventCode": "0xAB", 13 21 "EventName": "DSB2MITE_SWITCHES.COUNT", ··· 253 245 "UMask": "0x2" 254 246 }, 255 247 { 256 256 - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 248 248 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", 257 249 "EventCode": "0x83", 258 250 "EventName": "ICACHE_64B.IFTAG_STALL", 259 251 "SampleAfterValue": "200003", 260 252 "UMask": "0x4" 261 253 }, 262 254 { 263 263 - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 255 255 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", 256 256 + "EventCode": "0x83", 257 257 + "EventName": "ICACHE_TAG.STALLS", 258 258 + "SampleAfterValue": "200003", 259 259 + "UMask": "0x4" 260 260 + }, 261 261 + { 262 262 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.DSB_CYCLES_OK]", 264 263 "CounterMask": "4", 265 264 "EventCode": "0x79", 266 265 "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", 267 267 - "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.", 266 266 + "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK]", 268 267 "SampleAfterValue": "2000003", 269 268 "UMask": "0x18" 270 269 }, 271 270 { 272 272 - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 271 271 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.DSB_CYCLES_ANY]", 273 272 "CounterMask": "1", 274 273 "EventCode": "0x79", 275 274 "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", 276 276 - "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.", 275 275 + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_ANY]", 277 276 "SampleAfterValue": "2000003", 278 277 "UMask": "0x18" 279 278 }, ··· 310 295 "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", 311 296 "SampleAfterValue": "2000003", 312 297 "UMask": "0x8" 298 298 + }, 299 299 + { 300 300 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]", 301 301 + "CounterMask": "1", 302 302 + "EventCode": "0x79", 303 303 + "EventName": "IDQ.DSB_CYCLES_ANY", 304 304 + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]", 305 305 + "SampleAfterValue": "2000003", 306 306 + "UMask": "0x18" 307 307 + }, 308 308 + { 309 309 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]", 310 310 + "CounterMask": "4", 311 311 + "EventCode": "0x79", 312 312 + "EventName": "IDQ.DSB_CYCLES_OK", 313 313 + "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]", 314 314 + "SampleAfterValue": "2000003", 315 315 + "UMask": "0x18" 313 316 }, 314 317 { 315 318 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+13 -4

tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json

reviewed

··· 361 361 "UMask": "0x1" 362 362 }, 363 363 { 364 364 - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", 364 364 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]", 365 365 "EventCode": "0x87", 366 366 "EventName": "ILD_STALL.LCP", 367 367 - "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", 367 367 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]", 368 368 "SampleAfterValue": "2000003", 369 369 "UMask": "0x1" 370 370 }, ··· 488 488 "UMask": "0x1" 489 489 }, 490 490 { 491 491 - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", 491 491 + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_OK]", 492 492 "CounterMask": "4", 493 493 "EventCode": "0xA8", 494 494 "EventName": "LSD.CYCLES_4_UOPS", 495 495 - "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector).", 495 495 + "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_OK]", 496 496 "SampleAfterValue": "2000003", 497 497 "UMask": "0x1" 498 498 }, ··· 502 502 "EventCode": "0xA8", 503 503 "EventName": "LSD.CYCLES_ACTIVE", 504 504 "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", 505 505 + "SampleAfterValue": "2000003", 506 506 + "UMask": "0x1" 507 507 + }, 508 508 + { 509 509 + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS]", 510 510 + "CounterMask": "4", 511 511 + "EventCode": "0xA8", 512 512 + "EventName": "LSD.CYCLES_OK", 513 513 + "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_4_UOPS]", 505 514 "SampleAfterValue": "2000003", 506 515 "UMask": "0x1" 507 516 },

+1 -1

tools/perf/pmu-events/arch/x86/cascadelakex/uncore-interconnect.json

reviewed

··· 6606 6606 "EventCode": "0x52", 6607 6607 "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", 6608 6608 "PerPkg": "1", 6609 6609 - "PublicDescription": "ad and bl messages were actually slotted into the same flit in paralle", 6609 6609 + "PublicDescription": "ad and bl messages were actually slotted into the same flit in parallel", 6610 6610 "UMask": "0x8", 6611 6611 "Unit": "M3UPI" 6612 6612 },

+1 -1

tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json

reviewed

··· 2735 2735 "EventCode": "0x81", 2736 2736 "EventName": "UNC_M_WPQ_OCCUPANCY", 2737 2737 "PerPkg": "1", 2738 2738 - "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts?", 2738 2738 + "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", 2739 2739 "Unit": "iMC" 2740 2740 }, 2741 2741 {

+4 -4

tools/perf/pmu-events/arch/x86/icelake/cache.json

reviewed

··· 155 155 "UMask": "0x21" 156 156 }, 157 157 { 158 158 - "BriefDescription": "All requests that miss L2 cache. This event is not supported on ICL and ICX products, only supported on RKL products.", 158 158 + "BriefDescription": "This event is deprecated.", 159 159 + "Deprecated": "1", 159 160 "EventCode": "0x24", 160 161 "EventName": "L2_RQSTS.MISS", 161 161 - "PublicDescription": "Counts all requests that miss L2 cache. This event is not supported on ICL and ICX products, only supported on RKL products.", 162 162 "SampleAfterValue": "200003", 163 163 "UMask": "0x3f" 164 164 }, 165 165 { 166 166 - "BriefDescription": "All L2 requests. This event is not supported on ICL and ICX products, only supported on RKL products.", 166 166 + "BriefDescription": "This event is deprecated.", 167 167 + "Deprecated": "1", 167 168 "EventCode": "0x24", 168 169 "EventName": "L2_RQSTS.REFERENCES", 169 169 - "PublicDescription": "Counts all L2 requests. This event is not supported on ICL and ICX products, only supported on RKL products.", 170 170 "SampleAfterValue": "200003", 171 171 "UMask": "0xff" 172 172 },

+28 -4

tools/perf/pmu-events/arch/x86/icelake/frontend.json

reviewed

··· 8 8 "UMask": "0x1" 9 9 }, 10 10 { 11 11 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]", 12 12 + "EventCode": "0x87", 13 13 + "EventName": "DECODE.LCP", 14 14 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]", 15 15 + "SampleAfterValue": "500009", 16 16 + "UMask": "0x1" 17 17 + }, 18 18 + { 11 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 12 20 "CounterMask": "1", 13 21 "EdgeDetect": "1", ··· 221 213 "UMask": "0x1" 222 214 }, 223 215 { 224 224 - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", 216 216 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]", 225 217 "EventCode": "0x80", 226 218 "EventName": "ICACHE_16B.IFDATA_STALL", 227 227 - "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.", 219 219 + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]", 228 220 "SampleAfterValue": "500009", 229 221 "UMask": "0x4" 230 222 }, ··· 245 237 "UMask": "0x2" 246 238 }, 247 239 { 248 248 - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 240 240 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", 249 241 "EventCode": "0x83", 250 242 "EventName": "ICACHE_64B.IFTAG_STALL", 251 251 - "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 243 243 + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", 244 244 + "SampleAfterValue": "200003", 245 245 + "UMask": "0x4" 246 246 + }, 247 247 + { 248 248 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]", 249 249 + "EventCode": "0x80", 250 250 + "EventName": "ICACHE_DATA.STALLS", 251 251 + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]", 252 252 + "SampleAfterValue": "500009", 253 253 + "UMask": "0x4" 254 254 + }, 255 255 + { 256 256 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", 257 257 + "EventCode": "0x83", 258 258 + "EventName": "ICACHE_TAG.STALLS", 259 259 + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", 252 260 "SampleAfterValue": "200003", 253 261 "UMask": "0x4" 254 262 },

+4 -4

tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json

reviewed

··· 1516 1516 }, 1517 1517 { 1518 1518 "BriefDescription": "Percentage of cycles in aborted transactions.", 1519 1519 - "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", 1519 1519 + "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)", 1520 1520 "MetricGroup": "transaction", 1521 1521 "MetricName": "tsx_aborted_cycles", 1522 1522 "ScaleUnit": "100%" 1523 1523 }, 1524 1524 { 1525 1525 "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", 1526 1526 - "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", 1526 1526 + "MetricExpr": "(cycles\\-t / el\\-start if has_event(cycles\\-t) else 0)", 1527 1527 "MetricGroup": "transaction", 1528 1528 "MetricName": "tsx_cycles_per_elision", 1529 1529 "ScaleUnit": "1cycles / elision" 1530 1530 }, 1531 1531 { 1532 1532 "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", 1533 1533 - "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", 1533 1533 + "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)", 1534 1534 "MetricGroup": "transaction", 1535 1535 "MetricName": "tsx_cycles_per_transaction", 1536 1536 "ScaleUnit": "1cycles / transaction" 1537 1537 }, 1538 1538 { 1539 1539 "BriefDescription": "Percentage of cycles within a transaction region.", 1540 1540 - "MetricExpr": "cpu@cycles\\-t@ / cycles", 1540 1540 + "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)", 1541 1541 "MetricGroup": "transaction", 1542 1542 "MetricName": "tsx_transactional_cycles", 1543 1543 "ScaleUnit": "100%"

+3 -3

tools/perf/pmu-events/arch/x86/icelake/pipeline.json

reviewed

··· 318 318 "UMask": "0x40" 319 319 }, 320 320 { 321 321 - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", 321 321 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]", 322 322 "EventCode": "0x87", 323 323 "EventName": "ILD_STALL.LCP", 324 324 - "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", 324 324 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]", 325 325 "SampleAfterValue": "500009", 326 326 "UMask": "0x1" 327 327 }, ··· 556 556 "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", 557 557 "EventCode": "0xa4", 558 558 "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", 559 559 - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", 559 559 + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the speculative path as well as the out-of-order engine recovery past a branch misprediction.", 560 560 "SampleAfterValue": "10000003", 561 561 "UMask": "0x8" 562 562 },

+28 -4

tools/perf/pmu-events/arch/x86/icelakex/frontend.json

reviewed

··· 8 8 "UMask": "0x1" 9 9 }, 10 10 { 11 11 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]", 12 12 + "EventCode": "0x87", 13 13 + "EventName": "DECODE.LCP", 14 14 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]", 15 15 + "SampleAfterValue": "500009", 16 16 + "UMask": "0x1" 17 17 + }, 18 18 + { 11 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 12 20 "CounterMask": "1", 13 21 "EdgeDetect": "1", ··· 221 213 "UMask": "0x1" 222 214 }, 223 215 { 224 224 - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", 216 216 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]", 225 217 "EventCode": "0x80", 226 218 "EventName": "ICACHE_16B.IFDATA_STALL", 227 227 - "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.", 219 219 + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]", 228 220 "SampleAfterValue": "500009", 229 221 "UMask": "0x4" 230 222 }, ··· 245 237 "UMask": "0x2" 246 238 }, 247 239 { 248 248 - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 240 240 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", 249 241 "EventCode": "0x83", 250 242 "EventName": "ICACHE_64B.IFTAG_STALL", 251 251 - "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 243 243 + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", 244 244 + "SampleAfterValue": "200003", 245 245 + "UMask": "0x4" 246 246 + }, 247 247 + { 248 248 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]", 249 249 + "EventCode": "0x80", 250 250 + "EventName": "ICACHE_DATA.STALLS", 251 251 + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]", 252 252 + "SampleAfterValue": "500009", 253 253 + "UMask": "0x4" 254 254 + }, 255 255 + { 256 256 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", 257 257 + "EventCode": "0x83", 258 258 + "EventName": "ICACHE_TAG.STALLS", 259 259 + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", 252 260 "SampleAfterValue": "200003", 253 261 "UMask": "0x4" 254 262 },

+4 -4

tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json

reviewed

··· 1812 1812 }, 1813 1813 { 1814 1814 "BriefDescription": "Percentage of cycles in aborted transactions.", 1815 1815 - "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", 1815 1815 + "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)", 1816 1816 "MetricGroup": "transaction", 1817 1817 "MetricName": "tsx_aborted_cycles", 1818 1818 "ScaleUnit": "100%" 1819 1819 }, 1820 1820 { 1821 1821 "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", 1822 1822 - "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", 1822 1822 + "MetricExpr": "(cycles\\-t / el\\-start if has_event(cycles\\-t) else 0)", 1823 1823 "MetricGroup": "transaction", 1824 1824 "MetricName": "tsx_cycles_per_elision", 1825 1825 "ScaleUnit": "1cycles / elision" 1826 1826 }, 1827 1827 { 1828 1828 "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", 1829 1829 - "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", 1829 1829 + "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)", 1830 1830 "MetricGroup": "transaction", 1831 1831 "MetricName": "tsx_cycles_per_transaction", 1832 1832 "ScaleUnit": "1cycles / transaction" 1833 1833 }, 1834 1834 { 1835 1835 "BriefDescription": "Percentage of cycles within a transaction region.", 1836 1836 - "MetricExpr": "cpu@cycles\\-t@ / cycles", 1836 1836 + "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)", 1837 1837 "MetricGroup": "transaction", 1838 1838 "MetricName": "tsx_transactional_cycles", 1839 1839 "ScaleUnit": "100%"

+2 -2

tools/perf/pmu-events/arch/x86/icelakex/pipeline.json

reviewed

··· 318 318 "UMask": "0x40" 319 319 }, 320 320 { 321 321 - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", 321 321 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]", 322 322 "EventCode": "0x87", 323 323 "EventName": "ILD_STALL.LCP", 324 324 - "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", 324 324 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]", 325 325 "SampleAfterValue": "500009", 326 326 "UMask": "0x1" 327 327 },

+1 -1

tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json

reviewed

··· 9311 9311 "EventCode": "0x50", 9312 9312 "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", 9313 9313 "PerPkg": "1", 9314 9314 - "PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in paralle", 9314 9314 + "PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in parallel", 9315 9315 "UMask": "0x8", 9316 9316 "Unit": "M3UPI" 9317 9317 },

+9 -8

tools/perf/pmu-events/arch/x86/mapfile.csv

reviewed

··· 5 5 GenuineIntel-6-(3D|47),v28,broadwell,core 6 6 GenuineIntel-6-56,v10,broadwellde,core 7 7 GenuineIntel-6-4F,v21,broadwellx,core 8 8 - GenuineIntel-6-55-[56789ABCDEF],v1.18,cascadelakex,core 8 8 + GenuineIntel-6-55-[56789ABCDEF],v1.19,cascadelakex,core 9 9 GenuineIntel-6-9[6C],v1.04,elkhartlake,core 10 10 GenuineIntel-6-5[CF],v13,goldmont,core 11 11 GenuineIntel-6-7A,v1.01,goldmontplus,core ··· 13 13 GenuineIntel-6-A[DE],v1.01,graniterapids,core 14 14 GenuineIntel-6-(3C|45|46),v33,haswell,core 15 15 GenuineIntel-6-3F,v27,haswellx,core 16 16 - GenuineIntel-6-(7D|7E|A7),v1.18,icelake,core 17 17 - GenuineIntel-6-6[AC],v1.20,icelakex,core 16 16 + GenuineIntel-6-7[DE],v1.19,icelake,core 17 17 + GenuineIntel-6-6[AC],v1.21,icelakex,core 18 18 GenuineIntel-6-3A,v24,ivybridge,core 19 19 GenuineIntel-6-3E,v23,ivytown,core 20 20 GenuineIntel-6-2D,v23,jaketown,core 21 21 GenuineIntel-6-(57|85),v10,knightslanding,core 22 22 - GenuineIntel-6-A[AC],v1.01,meteorlake,core 22 22 + GenuineIntel-6-A[AC],v1.03,meteorlake,core 23 23 GenuineIntel-6-1[AEF],v3,nehalemep,core 24 24 GenuineIntel-6-2E,v3,nehalemex,core 25 25 + GenuineIntel-6-A7,v1.01,rocketlake,core 25 26 GenuineIntel-6-2A,v19,sandybridge,core 26 26 - GenuineIntel-6-(8F|CF),v1.13,sapphirerapids,core 27 27 + GenuineIntel-6-(8F|CF),v1.14,sapphirerapids,core 27 28 GenuineIntel-6-AF,v1.00,sierraforest,core 28 29 GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core 29 29 - GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v56,skylake,core 30 30 - GenuineIntel-6-55-[01234],v1.30,skylakex,core 30 30 + GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v57,skylake,core 31 31 + GenuineIntel-6-55-[01234],v1.31,skylakex,core 31 32 GenuineIntel-6-86,v1.21,snowridgex,core 32 32 - GenuineIntel-6-8[CD],v1.12,tigerlake,core 33 33 + GenuineIntel-6-8[CD],v1.13,tigerlake,core 33 34 GenuineIntel-6-2C,v4,westmereep-dp,core 34 35 GenuineIntel-6-25,v3,westmereep-sp,core 35 36 GenuineIntel-6-2F,v3,westmereex,core

+811

tools/perf/pmu-events/arch/x86/meteorlake/cache.json

reviewed

··· 1 1 [ 2 2 { 3 3 + "BriefDescription": "L1D.HWPF_MISS", 4 4 + "EventCode": "0x51", 5 5 + "EventName": "L1D.HWPF_MISS", 6 6 + "SampleAfterValue": "1000003", 7 7 + "UMask": "0x20", 8 8 + "Unit": "cpu_core" 9 9 + }, 10 10 + { 11 11 + "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", 12 12 + "EventCode": "0x51", 13 13 + "EventName": "L1D.REPLACEMENT", 14 14 + "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 15 15 + "SampleAfterValue": "100003", 16 16 + "UMask": "0x1", 17 17 + "Unit": "cpu_core" 18 18 + }, 19 19 + { 20 20 + "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", 21 21 + "EventCode": "0x48", 22 22 + "EventName": "L1D_PEND_MISS.FB_FULL", 23 23 + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 24 24 + "SampleAfterValue": "1000003", 25 25 + "UMask": "0x2", 26 26 + "Unit": "cpu_core" 27 27 + }, 28 28 + { 29 29 + "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.", 30 30 + "CounterMask": "1", 31 31 + "EdgeDetect": "1", 32 32 + "EventCode": "0x48", 33 33 + "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", 34 34 + "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 35 35 + "SampleAfterValue": "1000003", 36 36 + "UMask": "0x2", 37 37 + "Unit": "cpu_core" 38 38 + }, 39 39 + { 40 40 + "BriefDescription": "Number of L1D misses that are outstanding", 41 41 + "EventCode": "0x48", 42 42 + "EventName": "L1D_PEND_MISS.PENDING", 43 43 + "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 44 44 + "SampleAfterValue": "1000003", 45 45 + "UMask": "0x1", 46 46 + "Unit": "cpu_core" 47 47 + }, 48 48 + { 49 49 + "BriefDescription": "Cycles with L1D load Misses outstanding.", 50 50 + "CounterMask": "1", 51 51 + "EventCode": "0x48", 52 52 + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 53 53 + "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", 54 54 + "SampleAfterValue": "1000003", 55 55 + "UMask": "0x1", 56 56 + "Unit": "cpu_core" 57 57 + }, 58 58 + { 59 59 + "BriefDescription": "L2 cache lines filling L2", 60 60 + "EventCode": "0x25", 61 61 + "EventName": "L2_LINES_IN.ALL", 62 62 + "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", 63 63 + "SampleAfterValue": "100003", 64 64 + "UMask": "0x1f", 65 65 + "Unit": "cpu_core" 66 66 + }, 67 67 + { 68 68 + "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", 69 69 + "EventCode": "0x26", 70 70 + "EventName": "L2_LINES_OUT.NON_SILENT", 71 71 + "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", 72 72 + "SampleAfterValue": "200003", 73 73 + "UMask": "0x2", 74 74 + "Unit": "cpu_core" 75 75 + }, 76 76 + { 77 77 + "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.", 78 78 + "EventCode": "0x26", 79 79 + "EventName": "L2_LINES_OUT.SILENT", 80 80 + "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", 81 81 + "SampleAfterValue": "200003", 82 82 + "UMask": "0x1", 83 83 + "Unit": "cpu_core" 84 84 + }, 85 85 + { 86 86 + "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]", 87 87 + "EventCode": "0x24", 88 88 + "EventName": "L2_REQUEST.ALL", 89 89 + "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", 90 90 + "SampleAfterValue": "200003", 91 91 + "UMask": "0xff", 92 92 + "Unit": "cpu_core" 93 93 + }, 94 94 + { 95 95 + "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]", 96 96 + "EventCode": "0x24", 97 97 + "EventName": "L2_REQUEST.HIT", 98 98 + "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]", 99 99 + "SampleAfterValue": "200003", 100 100 + "UMask": "0xdf", 101 101 + "Unit": "cpu_core" 102 102 + }, 103 103 + { 104 104 + "BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MISS]", 105 105 + "EventCode": "0x24", 106 106 + "EventName": "L2_REQUEST.MISS", 107 107 + "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]", 108 108 + "SampleAfterValue": "200003", 109 109 + "UMask": "0x3f", 110 110 + "Unit": "cpu_core" 111 111 + }, 112 112 + { 3 113 "BriefDescription": "L2 code requests", 4 114 "EventCode": "0x24", 5 115 "EventName": "L2_RQSTS.ALL_CODE_RD", ··· 125 15 "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.", 126 16 "SampleAfterValue": "200003", 127 17 "UMask": "0xe1", 18 18 + "Unit": "cpu_core" 19 19 + }, 20 20 + { 21 21 + "BriefDescription": "Demand requests that miss L2 cache", 22 22 + "EventCode": "0x24", 23 23 + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", 24 24 + "PublicDescription": "Counts demand requests that miss L2 cache.", 25 25 + "SampleAfterValue": "200003", 26 26 + "UMask": "0x27", 27 27 + "Unit": "cpu_core" 28 28 + }, 29 29 + { 30 30 + "BriefDescription": "Demand requests to L2 cache", 31 31 + "EventCode": "0x24", 32 32 + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", 33 33 + "PublicDescription": "Counts demand requests to L2 cache.", 34 34 + "SampleAfterValue": "200003", 35 35 + "UMask": "0xe7", 36 36 + "Unit": "cpu_core" 37 37 + }, 38 38 + { 39 39 + "BriefDescription": "L2_RQSTS.ALL_HWPF", 40 40 + "EventCode": "0x24", 41 41 + "EventName": "L2_RQSTS.ALL_HWPF", 42 42 + "SampleAfterValue": "200003", 43 43 + "UMask": "0xf0", 44 44 + "Unit": "cpu_core" 45 45 + }, 46 46 + { 47 47 + "BriefDescription": "RFO requests to L2 cache", 48 48 + "EventCode": "0x24", 49 49 + "EventName": "L2_RQSTS.ALL_RFO", 50 50 + "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", 51 51 + "SampleAfterValue": "200003", 52 52 + "UMask": "0xe2", 53 53 + "Unit": "cpu_core" 54 54 + }, 55 55 + { 56 56 + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 57 57 + "EventCode": "0x24", 58 58 + "EventName": "L2_RQSTS.CODE_RD_HIT", 59 59 + "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", 60 60 + "SampleAfterValue": "200003", 61 61 + "UMask": "0xc4", 62 62 + "Unit": "cpu_core" 63 63 + }, 64 64 + { 65 65 + "BriefDescription": "L2 cache misses when fetching instructions", 66 66 + "EventCode": "0x24", 67 67 + "EventName": "L2_RQSTS.CODE_RD_MISS", 68 68 + "PublicDescription": "Counts L2 cache misses when fetching instructions.", 69 69 + "SampleAfterValue": "200003", 70 70 + "UMask": "0x24", 71 71 + "Unit": "cpu_core" 72 72 + }, 73 73 + { 74 74 + "BriefDescription": "Demand Data Read requests that hit L2 cache", 75 75 + "EventCode": "0x24", 76 76 + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 77 77 + "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 78 78 + "SampleAfterValue": "200003", 79 79 + "UMask": "0xc1", 80 80 + "Unit": "cpu_core" 81 81 + }, 82 82 + { 83 83 + "BriefDescription": "Demand Data Read miss L2 cache", 84 84 + "EventCode": "0x24", 85 85 + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", 86 86 + "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.", 87 87 + "SampleAfterValue": "200003", 88 88 + "UMask": "0x21", 89 89 + "Unit": "cpu_core" 90 90 + }, 91 91 + { 92 92 + "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]", 93 93 + "EventCode": "0x24", 94 94 + "EventName": "L2_RQSTS.HIT", 95 95 + "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]", 96 96 + "SampleAfterValue": "200003", 97 97 + "UMask": "0xdf", 98 98 + "Unit": "cpu_core" 99 99 + }, 100 100 + { 101 101 + "BriefDescription": "L2_RQSTS.HWPF_MISS", 102 102 + "EventCode": "0x24", 103 103 + "EventName": "L2_RQSTS.HWPF_MISS", 104 104 + "SampleAfterValue": "200003", 105 105 + "UMask": "0x30", 106 106 + "Unit": "cpu_core" 107 107 + }, 108 108 + { 109 109 + "BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS]", 110 110 + "EventCode": "0x24", 111 111 + "EventName": "L2_RQSTS.MISS", 112 112 + "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]", 113 113 + "SampleAfterValue": "200003", 114 114 + "UMask": "0x3f", 115 115 + "Unit": "cpu_core" 116 116 + }, 117 117 + { 118 118 + "BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]", 119 119 + "EventCode": "0x24", 120 120 + "EventName": "L2_RQSTS.REFERENCES", 121 121 + "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]", 122 122 + "SampleAfterValue": "200003", 123 123 + "UMask": "0xff", 124 124 + "Unit": "cpu_core" 125 125 + }, 126 126 + { 127 127 + "BriefDescription": "RFO requests that hit L2 cache", 128 128 + "EventCode": "0x24", 129 129 + "EventName": "L2_RQSTS.RFO_HIT", 130 130 + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 131 131 + "SampleAfterValue": "200003", 132 132 + "UMask": "0xc2", 133 133 + "Unit": "cpu_core" 134 134 + }, 135 135 + { 136 136 + "BriefDescription": "RFO requests that miss L2 cache", 137 137 + "EventCode": "0x24", 138 138 + "EventName": "L2_RQSTS.RFO_MISS", 139 139 + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 140 140 + "SampleAfterValue": "200003", 141 141 + "UMask": "0x22", 142 142 + "Unit": "cpu_core" 143 143 + }, 144 144 + { 145 145 + "BriefDescription": "L2 writebacks that access L2 cache", 146 146 + "EventCode": "0x23", 147 147 + "EventName": "L2_TRANS.L2_WB", 148 148 + "PublicDescription": "Counts L2 writebacks that access L2 cache.", 149 149 + "SampleAfterValue": "200003", 150 150 + "UMask": "0x40", 128 151 "Unit": "cpu_core" 129 152 }, 130 153 { ··· 297 54 "Unit": "cpu_core" 298 55 }, 299 56 { 57 57 + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss.", 58 58 + "EventCode": "0x35", 59 59 + "EventName": "MEM_BOUND_STALLS_IFETCH.ALL", 60 60 + "SampleAfterValue": "1000003", 61 61 + "UMask": "0x6f", 62 62 + "Unit": "cpu_atom" 63 63 + }, 64 64 + { 65 65 + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", 66 66 + "EventCode": "0x35", 67 67 + "EventName": "MEM_BOUND_STALLS_IFETCH.L2_HIT", 68 68 + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", 69 69 + "SampleAfterValue": "1000003", 70 70 + "UMask": "0x1", 71 71 + "Unit": "cpu_atom" 72 72 + }, 73 73 + { 74 74 + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which hit in the LLC.", 75 75 + "EventCode": "0x35", 76 76 + "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT", 77 77 + "SampleAfterValue": "1000003", 78 78 + "UMask": "0x6", 79 79 + "Unit": "cpu_atom" 80 80 + }, 81 81 + { 82 82 + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches.", 83 83 + "EventCode": "0x35", 84 84 + "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS", 85 85 + "SampleAfterValue": "1000003", 86 86 + "UMask": "0x68", 87 87 + "Unit": "cpu_atom" 88 88 + }, 89 89 + { 90 90 + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.", 91 91 + "EventCode": "0x34", 92 92 + "EventName": "MEM_BOUND_STALLS_LOAD.ALL", 93 93 + "SampleAfterValue": "1000003", 94 94 + "UMask": "0x6f", 95 95 + "Unit": "cpu_atom" 96 96 + }, 97 97 + { 98 98 + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", 99 99 + "EventCode": "0x34", 100 100 + "EventName": "MEM_BOUND_STALLS_LOAD.L2_HIT", 101 101 + "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.", 102 102 + "SampleAfterValue": "1000003", 103 103 + "UMask": "0x1", 104 104 + "Unit": "cpu_atom" 105 105 + }, 106 106 + { 107 107 + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC.", 108 108 + "EventCode": "0x34", 109 109 + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT", 110 110 + "SampleAfterValue": "1000003", 111 111 + "UMask": "0x6", 112 112 + "Unit": "cpu_atom" 113 113 + }, 114 114 + { 115 115 + "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches.", 116 116 + "EventCode": "0x34", 117 117 + "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS", 118 118 + "SampleAfterValue": "1000003", 119 119 + "UMask": "0x68", 120 120 + "Unit": "cpu_atom" 121 121 + }, 122 122 + { 300 123 "BriefDescription": "Retired load instructions.", 301 124 "Data_LA": "1", 302 125 "EventCode": "0xd0", ··· 383 74 "SampleAfterValue": "1000003", 384 75 "UMask": "0x82", 385 76 "Unit": "cpu_core" 77 77 + }, 78 78 + { 79 79 + "BriefDescription": "All retired memory instructions.", 80 80 + "Data_LA": "1", 81 81 + "EventCode": "0xd0", 82 82 + "EventName": "MEM_INST_RETIRED.ANY", 83 83 + "PEBS": "1", 84 84 + "PublicDescription": "Counts all retired memory instructions - loads and stores.", 85 85 + "SampleAfterValue": "1000003", 86 86 + "UMask": "0x83", 87 87 + "Unit": "cpu_core" 88 88 + }, 89 89 + { 90 90 + "BriefDescription": "Retired load instructions with locked access.", 91 91 + "Data_LA": "1", 92 92 + "EventCode": "0xd0", 93 93 + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", 94 94 + "PEBS": "1", 95 95 + "PublicDescription": "Counts retired load instructions with locked access.", 96 96 + "SampleAfterValue": "100007", 97 97 + "UMask": "0x21", 98 98 + "Unit": "cpu_core" 99 99 + }, 100 100 + { 101 101 + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", 102 102 + "Data_LA": "1", 103 103 + "EventCode": "0xd0", 104 104 + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", 105 105 + "PEBS": "1", 106 106 + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", 107 107 + "SampleAfterValue": "100003", 108 108 + "UMask": "0x41", 109 109 + "Unit": "cpu_core" 110 110 + }, 111 111 + { 112 112 + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", 113 113 + "Data_LA": "1", 114 114 + "EventCode": "0xd0", 115 115 + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", 116 116 + "PEBS": "1", 117 117 + "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", 118 118 + "SampleAfterValue": "100003", 119 119 + "UMask": "0x42", 120 120 + "Unit": "cpu_core" 121 121 + }, 122 122 + { 123 123 + "BriefDescription": "Retired load instructions that hit the STLB.", 124 124 + "Data_LA": "1", 125 125 + "EventCode": "0xd0", 126 126 + "EventName": "MEM_INST_RETIRED.STLB_HIT_LOADS", 127 127 + "PEBS": "1", 128 128 + "PublicDescription": "Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB).", 129 129 + "SampleAfterValue": "100003", 130 130 + "UMask": "0x9", 131 131 + "Unit": "cpu_core" 132 132 + }, 133 133 + { 134 134 + "BriefDescription": "Retired store instructions that hit the STLB.", 135 135 + "Data_LA": "1", 136 136 + "EventCode": "0xd0", 137 137 + "EventName": "MEM_INST_RETIRED.STLB_HIT_STORES", 138 138 + "PEBS": "1", 139 139 + "PublicDescription": "Number of retired store instructions that hit in the 2nd-level TLB (STLB).", 140 140 + "SampleAfterValue": "100003", 141 141 + "UMask": "0xa", 142 142 + "Unit": "cpu_core" 143 143 + }, 144 144 + { 145 145 + "BriefDescription": "Retired load instructions that miss the STLB.", 146 146 + "Data_LA": "1", 147 147 + "EventCode": "0xd0", 148 148 + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", 149 149 + "PEBS": "1", 150 150 + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", 151 151 + "SampleAfterValue": "100003", 152 152 + "UMask": "0x11", 153 153 + "Unit": "cpu_core" 154 154 + }, 155 155 + { 156 156 + "BriefDescription": "Retired store instructions that miss the STLB.", 157 157 + "Data_LA": "1", 158 158 + "EventCode": "0xd0", 159 159 + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", 160 160 + "PEBS": "1", 161 161 + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", 162 162 + "SampleAfterValue": "100003", 163 163 + "UMask": "0x12", 164 164 + "Unit": "cpu_core" 165 165 + }, 166 166 + { 167 167 + "BriefDescription": "Completed demand load uops that miss the L1 d-cache.", 168 168 + "EventCode": "0x43", 169 169 + "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", 170 170 + "PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)", 171 171 + "SampleAfterValue": "1000003", 172 172 + "UMask": "0xfd", 173 173 + "Unit": "cpu_core" 174 174 + }, 175 175 + { 176 176 + "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 177 177 + "Data_LA": "1", 178 178 + "EventCode": "0xd2", 179 179 + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", 180 180 + "PEBS": "1", 181 181 + "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", 182 182 + "SampleAfterValue": "20011", 183 183 + "UMask": "0x4", 184 184 + "Unit": "cpu_core" 185 185 + }, 186 186 + { 187 187 + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", 188 188 + "Data_LA": "1", 189 189 + "EventCode": "0xd2", 190 190 + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", 191 191 + "PEBS": "1", 192 192 + "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", 193 193 + "SampleAfterValue": "20011", 194 194 + "UMask": "0x2", 195 195 + "Unit": "cpu_core" 196 196 + }, 197 197 + { 198 198 + "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 199 199 + "Data_LA": "1", 200 200 + "EventCode": "0xd2", 201 201 + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", 202 202 + "PEBS": "1", 203 203 + "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", 204 204 + "SampleAfterValue": "20011", 205 205 + "UMask": "0x4", 206 206 + "Unit": "cpu_core" 207 207 + }, 208 208 + { 209 209 + "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", 210 210 + "Data_LA": "1", 211 211 + "EventCode": "0xd2", 212 212 + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", 213 213 + "PEBS": "1", 214 214 + "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.", 215 215 + "SampleAfterValue": "100003", 216 216 + "UMask": "0x8", 217 217 + "Unit": "cpu_core" 218 218 + }, 219 219 + { 220 220 + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", 221 221 + "Data_LA": "1", 222 222 + "EventCode": "0xd2", 223 223 + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", 224 224 + "PEBS": "1", 225 225 + "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", 226 226 + "SampleAfterValue": "20011", 227 227 + "UMask": "0x2", 228 228 + "Unit": "cpu_core" 229 229 + }, 230 230 + { 231 231 + "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", 232 232 + "Data_LA": "1", 233 233 + "EventCode": "0xd3", 234 234 + "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", 235 235 + "PEBS": "1", 236 236 + "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.", 237 237 + "SampleAfterValue": "100007", 238 238 + "UMask": "0x1", 239 239 + "Unit": "cpu_core" 240 240 + }, 241 241 + { 242 242 + "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", 243 243 + "Data_LA": "1", 244 244 + "EventCode": "0xd4", 245 245 + "EventName": "MEM_LOAD_MISC_RETIRED.UC", 246 246 + "PEBS": "1", 247 247 + "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).", 248 248 + "SampleAfterValue": "100007", 249 249 + "UMask": "0x4", 250 250 + "Unit": "cpu_core" 251 251 + }, 252 252 + { 253 253 + "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", 254 254 + "Data_LA": "1", 255 255 + "EventCode": "0xd1", 256 256 + "EventName": "MEM_LOAD_RETIRED.FB_HIT", 257 257 + "PEBS": "1", 258 258 + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", 259 259 + "SampleAfterValue": "100007", 260 260 + "UMask": "0x40", 261 261 + "Unit": "cpu_core" 262 262 + }, 263 263 + { 264 264 + "BriefDescription": "Retired load instructions with L1 cache hits as data sources", 265 265 + "Data_LA": "1", 266 266 + "EventCode": "0xd1", 267 267 + "EventName": "MEM_LOAD_RETIRED.L1_HIT", 268 268 + "PEBS": "1", 269 269 + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", 270 270 + "SampleAfterValue": "1000003", 271 271 + "UMask": "0x1", 272 272 + "Unit": "cpu_core" 273 273 + }, 274 274 + { 275 275 + "BriefDescription": "Retired load instructions missed L1 cache as data sources", 276 276 + "Data_LA": "1", 277 277 + "EventCode": "0xd1", 278 278 + "EventName": "MEM_LOAD_RETIRED.L1_MISS", 279 279 + "PEBS": "1", 280 280 + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", 281 281 + "SampleAfterValue": "200003", 282 282 + "UMask": "0x8", 283 283 + "Unit": "cpu_core" 284 284 + }, 285 285 + { 286 286 + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", 287 287 + "Data_LA": "1", 288 288 + "EventCode": "0xd1", 289 289 + "EventName": "MEM_LOAD_RETIRED.L2_HIT", 290 290 + "PEBS": "1", 291 291 + "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", 292 292 + "SampleAfterValue": "200003", 293 293 + "UMask": "0x2", 294 294 + "Unit": "cpu_core" 295 295 + }, 296 296 + { 297 297 + "BriefDescription": "Retired load instructions missed L2 cache as data sources", 298 298 + "Data_LA": "1", 299 299 + "EventCode": "0xd1", 300 300 + "EventName": "MEM_LOAD_RETIRED.L2_MISS", 301 301 + "PEBS": "1", 302 302 + "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", 303 303 + "SampleAfterValue": "100021", 304 304 + "UMask": "0x10", 305 305 + "Unit": "cpu_core" 306 306 + }, 307 307 + { 308 308 + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", 309 309 + "Data_LA": "1", 310 310 + "EventCode": "0xd1", 311 311 + "EventName": "MEM_LOAD_RETIRED.L3_HIT", 312 312 + "PEBS": "1", 313 313 + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", 314 314 + "SampleAfterValue": "100021", 315 315 + "UMask": "0x4", 316 316 + "Unit": "cpu_core" 317 317 + }, 318 318 + { 319 319 + "BriefDescription": "Retired load instructions missed L3 cache as data sources", 320 320 + "Data_LA": "1", 321 321 + "EventCode": "0xd1", 322 322 + "EventName": "MEM_LOAD_RETIRED.L3_MISS", 323 323 + "PEBS": "1", 324 324 + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", 325 325 + "SampleAfterValue": "50021", 326 326 + "UMask": "0x20", 327 327 + "Unit": "cpu_core" 328 328 + }, 329 329 + { 330 330 + "BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM", 331 331 + "EventCode": "0xd4", 332 332 + "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LOCAL_DRAM", 333 333 + "PEBS": "1", 334 334 + "SampleAfterValue": "1000003", 335 335 + "UMask": "0x2", 336 336 + "Unit": "cpu_atom" 337 337 + }, 338 338 + { 339 339 + "BriefDescription": "Counts the number of load ops retired that hit the L1 data cache.", 340 340 + "EventCode": "0xd1", 341 341 + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", 342 342 + "PEBS": "1", 343 343 + "SampleAfterValue": "200003", 344 344 + "UMask": "0x1", 345 345 + "Unit": "cpu_atom" 346 346 + }, 347 347 + { 348 348 + "BriefDescription": "Counts the number of load ops retired that miss in the L1 data cache.", 349 349 + "EventCode": "0xd1", 350 350 + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", 351 351 + "PEBS": "1", 352 352 + "SampleAfterValue": "200003", 353 353 + "UMask": "0x40", 354 354 + "Unit": "cpu_atom" 355 355 + }, 356 356 + { 357 357 + "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.", 358 358 + "EventCode": "0xd1", 359 359 + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", 360 360 + "PEBS": "1", 361 361 + "SampleAfterValue": "200003", 362 362 + "UMask": "0x2", 363 363 + "Unit": "cpu_atom" 364 364 + }, 365 365 + { 366 366 + "BriefDescription": "Counts the number of load ops retired that miss in the L2 cache.", 367 367 + "EventCode": "0xd1", 368 368 + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", 369 369 + "PEBS": "1", 370 370 + "SampleAfterValue": "200003", 371 371 + "UMask": "0x80", 372 372 + "Unit": "cpu_atom" 373 373 + }, 374 374 + { 375 375 + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.", 376 376 + "EventCode": "0xd1", 377 377 + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", 378 378 + "PEBS": "1", 379 379 + "SampleAfterValue": "200003", 380 380 + "UMask": "0x1c", 381 381 + "Unit": "cpu_atom" 382 382 + }, 383 383 + { 384 384 + "BriefDescription": "Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate.", 385 385 + "EventCode": "0xd1", 386 386 + "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", 387 387 + "PEBS": "1", 388 388 + "SampleAfterValue": "200003", 389 389 + "UMask": "0x20", 390 390 + "Unit": "cpu_atom" 391 391 + }, 392 392 + { 393 393 + "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.", 394 394 + "EventCode": "0x04", 395 395 + "EventName": "MEM_SCHEDULER_BLOCK.ALL", 396 396 + "SampleAfterValue": "20003", 397 397 + "UMask": "0x7", 398 398 + "Unit": "cpu_atom" 399 399 + }, 400 400 + { 401 401 + "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.", 402 402 + "EventCode": "0x04", 403 403 + "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", 404 404 + "SampleAfterValue": "20003", 405 405 + "UMask": "0x2", 406 406 + "Unit": "cpu_atom" 407 407 + }, 408 408 + { 409 409 + "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.", 410 410 + "EventCode": "0x04", 411 411 + "EventName": "MEM_SCHEDULER_BLOCK.RSV", 412 412 + "SampleAfterValue": "20003", 413 413 + "UMask": "0x4", 414 414 + "Unit": "cpu_atom" 415 415 + }, 416 416 + { 417 417 + "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.", 418 418 + "EventCode": "0x04", 419 419 + "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", 420 420 + "SampleAfterValue": "20003", 421 421 + "UMask": "0x1", 422 422 + "Unit": "cpu_atom" 386 423 }, 387 424 { 388 425 "BriefDescription": "Counts the number of load ops retired.", ··· 754 99 "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 755 100 "Data_LA": "1", 756 101 "EventCode": "0xd0", 102 102 + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", 103 103 + "MSRIndex": "0x3F6", 104 104 + "MSRValue": "0x400", 105 105 + "PEBS": "2", 106 106 + "SampleAfterValue": "1000003", 107 107 + "UMask": "0x5", 108 108 + "Unit": "cpu_atom" 109 109 + }, 110 110 + { 111 111 + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 112 112 + "Data_LA": "1", 113 113 + "EventCode": "0xd0", 757 114 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", 758 115 "MSRIndex": "0x3F6", 759 116 "MSRValue": "0x80", ··· 781 114 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", 782 115 "MSRIndex": "0x3F6", 783 116 "MSRValue": "0x10", 117 117 + "PEBS": "2", 118 118 + "SampleAfterValue": "1000003", 119 119 + "UMask": "0x5", 120 120 + "Unit": "cpu_atom" 121 121 + }, 122 122 + { 123 123 + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", 124 124 + "Data_LA": "1", 125 125 + "EventCode": "0xd0", 126 126 + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", 127 127 + "MSRIndex": "0x3F6", 128 128 + "MSRValue": "0x800", 784 129 "PEBS": "2", 785 130 "SampleAfterValue": "1000003", 786 131 "UMask": "0x5", ··· 871 192 "Unit": "cpu_atom" 872 193 }, 873 194 { 195 195 + "BriefDescription": "Counts the number of load uops retired that performed one or more locks", 196 196 + "Data_LA": "1", 197 197 + "EventCode": "0xd0", 198 198 + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", 199 199 + "PEBS": "1", 200 200 + "SampleAfterValue": "200003", 201 201 + "UMask": "0x21", 202 202 + "Unit": "cpu_atom" 203 203 + }, 204 204 + { 205 205 + "BriefDescription": "Counts the number of memory uops retired that were splits.", 206 206 + "Data_LA": "1", 207 207 + "EventCode": "0xd0", 208 208 + "EventName": "MEM_UOPS_RETIRED.SPLIT", 209 209 + "PEBS": "1", 210 210 + "SampleAfterValue": "200003", 211 211 + "UMask": "0x43", 212 212 + "Unit": "cpu_atom" 213 213 + }, 214 214 + { 215 215 + "BriefDescription": "Counts the number of retired split load uops.", 216 216 + "Data_LA": "1", 217 217 + "EventCode": "0xd0", 218 218 + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", 219 219 + "PEBS": "1", 220 220 + "SampleAfterValue": "200003", 221 221 + "UMask": "0x41", 222 222 + "Unit": "cpu_atom" 223 223 + }, 224 224 + { 225 225 + "BriefDescription": "Counts the number of retired split store uops.", 226 226 + "Data_LA": "1", 227 227 + "EventCode": "0xd0", 228 228 + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", 229 229 + "PEBS": "1", 230 230 + "SampleAfterValue": "200003", 231 231 + "UMask": "0x42", 232 232 + "Unit": "cpu_atom" 233 233 + }, 234 234 + { 874 235 "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", 875 236 "Data_LA": "1", 876 237 "EventCode": "0xd0", ··· 918 199 "PEBS": "2", 919 200 "SampleAfterValue": "1000003", 920 201 "UMask": "0x6", 202 202 + "Unit": "cpu_atom" 203 203 + }, 204 204 + { 205 205 + "BriefDescription": "Retired memory uops for any access", 206 206 + "EventCode": "0xe5", 207 207 + "EventName": "MEM_UOP_RETIRED.ANY", 208 208 + "PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses", 209 209 + "SampleAfterValue": "1000003", 210 210 + "UMask": "0x3", 211 211 + "Unit": "cpu_core" 212 212 + }, 213 213 + { 214 214 + "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", 215 215 + "EventCode": "0x2A,0x2B", 216 216 + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", 217 217 + "MSRIndex": "0x1a6,0x1a7", 218 218 + "MSRValue": "0x10003C0001", 219 219 + "SampleAfterValue": "100003", 220 220 + "UMask": "0x1", 221 221 + "Unit": "cpu_core" 222 222 + }, 223 223 + { 224 224 + "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.", 225 225 + "EventCode": "0x2A,0x2B", 226 226 + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", 227 227 + "MSRIndex": "0x1a6,0x1a7", 228 228 + "MSRValue": "0x8003C0001", 229 229 + "SampleAfterValue": "100003", 230 230 + "UMask": "0x1", 231 231 + "Unit": "cpu_core" 232 232 + }, 233 233 + { 234 234 + "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", 235 235 + "EventCode": "0x2A,0x2B", 236 236 + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 237 237 + "MSRIndex": "0x1a6,0x1a7", 238 238 + "MSRValue": "0x10003C0002", 239 239 + "SampleAfterValue": "100003", 240 240 + "UMask": "0x1", 241 241 + "Unit": "cpu_core" 242 242 + }, 243 243 + { 244 244 + "BriefDescription": "Any memory transaction that reached the SQ.", 245 245 + "EventCode": "0x21", 246 246 + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", 247 247 + "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..", 248 248 + "SampleAfterValue": "100003", 249 249 + "UMask": "0x80", 250 250 + "Unit": "cpu_core" 251 251 + }, 252 252 + { 253 253 + "BriefDescription": "Demand and prefetch data reads", 254 254 + "EventCode": "0x21", 255 255 + "EventName": "OFFCORE_REQUESTS.DATA_RD", 256 256 + "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", 257 257 + "SampleAfterValue": "100003", 258 258 + "UMask": "0x8", 259 259 + "Unit": "cpu_core" 260 260 + }, 261 261 + { 262 262 + "BriefDescription": "Demand Data Read requests sent to uncore", 263 263 + "EventCode": "0x21", 264 264 + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 265 265 + "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", 266 266 + "SampleAfterValue": "100003", 267 267 + "UMask": "0x1", 268 268 + "Unit": "cpu_core" 269 269 + }, 270 270 + { 271 271 + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 272 272 + "EventCode": "0x21", 273 273 + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 274 274 + "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", 275 275 + "SampleAfterValue": "100003", 276 276 + "UMask": "0x4", 277 277 + "Unit": "cpu_core" 278 278 + }, 279 279 + { 280 280 + "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.", 281 281 + "EventCode": "0x2c", 282 282 + "EventName": "SQ_MISC.BUS_LOCK", 283 283 + "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.", 284 284 + "SampleAfterValue": "100003", 285 285 + "UMask": "0x10", 286 286 + "Unit": "cpu_core" 287 287 + }, 288 288 + { 289 289 + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss", 290 290 + "EventCode": "0x71", 291 291 + "EventName": "TOPDOWN_FE_BOUND.ICACHE", 292 292 + "SampleAfterValue": "1000003", 293 293 + "UMask": "0x20", 921 294 "Unit": "cpu_atom" 922 295 } 923 296 ]

+143

tools/perf/pmu-events/arch/x86/meteorlake/floating-point.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "This event counts the cycles the floating point divider is busy.", 4 4 + "CounterMask": "1", 5 5 + "EventCode": "0xb0", 6 6 + "EventName": "ARITH.FPDIV_ACTIVE", 7 7 + "SampleAfterValue": "1000003", 8 8 + "UMask": "0x1", 9 9 + "Unit": "cpu_core" 10 10 + }, 11 11 + { 12 12 + "BriefDescription": "Counts all microcode FP assists.", 13 13 + "EventCode": "0xc1", 14 14 + "EventName": "ASSISTS.FP", 15 15 + "PublicDescription": "Counts all microcode Floating Point assists.", 16 16 + "SampleAfterValue": "100003", 17 17 + "UMask": "0x2", 18 18 + "Unit": "cpu_core" 19 19 + }, 20 20 + { 21 21 + "BriefDescription": "ASSISTS.SSE_AVX_MIX", 22 22 + "EventCode": "0xc1", 23 23 + "EventName": "ASSISTS.SSE_AVX_MIX", 24 24 + "SampleAfterValue": "1000003", 25 25 + "UMask": "0x10", 26 26 + "Unit": "cpu_core" 27 27 + }, 28 28 + { 29 29 + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0", 30 30 + "EventCode": "0xb3", 31 31 + "EventName": "FP_ARITH_DISPATCHED.PORT_0", 32 32 + "SampleAfterValue": "2000003", 33 33 + "UMask": "0x1", 34 34 + "Unit": "cpu_core" 35 35 + }, 36 36 + { 37 37 + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1", 38 38 + "EventCode": "0xb3", 39 39 + "EventName": "FP_ARITH_DISPATCHED.PORT_1", 40 40 + "SampleAfterValue": "2000003", 41 41 + "UMask": "0x2", 42 42 + "Unit": "cpu_core" 43 43 + }, 44 44 + { 45 45 + "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 46 46 + "EventCode": "0xc7", 47 47 + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 48 48 + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 49 49 + "SampleAfterValue": "100003", 50 50 + "UMask": "0x4", 51 51 + "Unit": "cpu_core" 52 52 + }, 53 53 + { 54 54 + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 55 55 + "EventCode": "0xc7", 56 56 + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 57 57 + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 58 58 + "SampleAfterValue": "100003", 59 59 + "UMask": "0x8", 60 60 + "Unit": "cpu_core" 61 61 + }, 62 62 + { 63 63 + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 64 64 + "EventCode": "0xc7", 65 65 + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 66 66 + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 67 67 + "SampleAfterValue": "100003", 68 68 + "UMask": "0x10", 69 69 + "Unit": "cpu_core" 70 70 + }, 71 71 + { 72 72 + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 73 73 + "EventCode": "0xc7", 74 74 + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 75 75 + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 76 76 + "SampleAfterValue": "100003", 77 77 + "UMask": "0x20", 78 78 + "Unit": "cpu_core" 79 79 + }, 80 80 + { 81 81 + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 82 82 + "EventCode": "0xc7", 83 83 + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 84 84 + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 85 85 + "SampleAfterValue": "100003", 86 86 + "UMask": "0x18", 87 87 + "Unit": "cpu_core" 88 88 + }, 89 89 + { 90 90 + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 91 91 + "EventCode": "0xc7", 92 92 + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 93 93 + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 94 94 + "SampleAfterValue": "1000003", 95 95 + "UMask": "0x3", 96 96 + "Unit": "cpu_core" 97 97 + }, 98 98 + { 99 99 + "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 100 100 + "EventCode": "0xc7", 101 101 + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 102 102 + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 103 103 + "SampleAfterValue": "100003", 104 104 + "UMask": "0x1", 105 105 + "Unit": "cpu_core" 106 106 + }, 107 107 + { 108 108 + "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 109 109 + "EventCode": "0xc7", 110 110 + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 111 111 + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 112 112 + "SampleAfterValue": "100003", 113 113 + "UMask": "0x2", 114 114 + "Unit": "cpu_core" 115 115 + }, 116 116 + { 117 117 + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 118 118 + "EventCode": "0xc7", 119 119 + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 120 120 + "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 121 121 + "SampleAfterValue": "1000003", 122 122 + "UMask": "0xfc", 123 123 + "Unit": "cpu_core" 124 124 + }, 125 125 + { 126 126 + "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 127 127 + "EventCode": "0xc3", 128 128 + "EventName": "MACHINE_CLEARS.FP_ASSIST", 129 129 + "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", 130 130 + "SampleAfterValue": "20003", 131 131 + "UMask": "0x4", 132 132 + "Unit": "cpu_atom" 133 133 + }, 134 134 + { 135 135 + "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).", 136 136 + "EventCode": "0xc2", 137 137 + "EventName": "UOPS_RETIRED.FPDIV", 138 138 + "PEBS": "1", 139 139 + "SampleAfterValue": "2000003", 140 140 + "UMask": "0x8", 141 141 + "Unit": "cpu_atom" 142 142 + } 143 143 + ]

+410

tools/perf/pmu-events/arch/x86/meteorlake/frontend.json

reviewed

··· 1 1 [ 2 2 { 3 3 + "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", 4 4 + "EventCode": "0xe6", 5 5 + "EventName": "BACLEARS.ANY", 6 6 + "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", 7 7 + "SampleAfterValue": "200003", 8 8 + "UMask": "0x1", 9 9 + "Unit": "cpu_atom" 10 10 + }, 11 11 + { 12 12 + "BriefDescription": "Clears due to Unknown Branches.", 13 13 + "EventCode": "0x60", 14 14 + "EventName": "BACLEARS.ANY", 15 15 + "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", 16 16 + "SampleAfterValue": "100003", 17 17 + "UMask": "0x1", 18 18 + "Unit": "cpu_core" 19 19 + }, 20 20 + { 21 21 + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", 22 22 + "EventCode": "0x87", 23 23 + "EventName": "DECODE.LCP", 24 24 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", 25 25 + "SampleAfterValue": "500009", 26 26 + "UMask": "0x1", 27 27 + "Unit": "cpu_core" 28 28 + }, 29 29 + { 30 30 + "BriefDescription": "Cycles the Microcode Sequencer is busy.", 31 31 + "EventCode": "0x87", 32 32 + "EventName": "DECODE.MS_BUSY", 33 33 + "SampleAfterValue": "500009", 34 34 + "UMask": "0x2", 35 35 + "Unit": "cpu_core" 36 36 + }, 37 37 + { 38 38 + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 39 39 + "EventCode": "0x61", 40 40 + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", 41 41 + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", 42 42 + "SampleAfterValue": "100003", 43 43 + "UMask": "0x2", 44 44 + "Unit": "cpu_core" 45 45 + }, 46 46 + { 47 47 + "BriefDescription": "Retired ANT branches", 48 48 + "EventCode": "0xc6", 49 49 + "EventName": "FRONTEND_RETIRED.ANY_ANT", 50 50 + "MSRIndex": "0x3F7", 51 51 + "MSRValue": "0x9", 52 52 + "PEBS": "1", 53 53 + "PublicDescription": "Always Not Taken (ANT) conditional retired branches (no BTB entry and not mispredicted)", 54 54 + "SampleAfterValue": "100007", 55 55 + "UMask": "0x3", 56 56 + "Unit": "cpu_core" 57 57 + }, 58 58 + { 59 59 + "BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss", 60 60 + "EventCode": "0xc6", 61 61 + "EventName": "FRONTEND_RETIRED.ITLB_MISS", 62 62 + "PEBS": "1", 63 63 + "SampleAfterValue": "1000003", 64 64 + "UMask": "0x10", 65 65 + "Unit": "cpu_atom" 66 66 + }, 67 67 + { 68 68 + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", 69 69 + "EventCode": "0xc6", 70 70 + "EventName": "FRONTEND_RETIRED.ITLB_MISS", 71 71 + "MSRIndex": "0x3F7", 72 72 + "MSRValue": "0x14", 73 73 + "PEBS": "1", 74 74 + "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", 75 75 + "SampleAfterValue": "100007", 76 76 + "UMask": "0x3", 77 77 + "Unit": "cpu_core" 78 78 + }, 79 79 + { 80 80 + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 81 81 + "EventCode": "0xc6", 82 82 + "EventName": "FRONTEND_RETIRED.L1I_MISS", 83 83 + "MSRIndex": "0x3F7", 84 84 + "MSRValue": "0x12", 85 85 + "PEBS": "1", 86 86 + "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", 87 87 + "SampleAfterValue": "100007", 88 88 + "UMask": "0x3", 89 89 + "Unit": "cpu_core" 90 90 + }, 91 91 + { 92 92 + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 93 93 + "EventCode": "0xc6", 94 94 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", 95 95 + "MSRIndex": "0x3F7", 96 96 + "MSRValue": "0x600106", 97 97 + "PEBS": "1", 98 98 + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", 99 99 + "SampleAfterValue": "100007", 100 100 + "UMask": "0x3", 101 101 + "Unit": "cpu_core" 102 102 + }, 103 103 + { 104 104 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", 105 105 + "EventCode": "0xc6", 106 106 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", 107 107 + "MSRIndex": "0x3F7", 108 108 + "MSRValue": "0x608006", 109 109 + "PEBS": "1", 110 110 + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", 111 111 + "SampleAfterValue": "100007", 112 112 + "UMask": "0x3", 113 113 + "Unit": "cpu_core" 114 114 + }, 115 115 + { 116 116 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", 117 117 + "EventCode": "0xc6", 118 118 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", 119 119 + "MSRIndex": "0x3F7", 120 120 + "MSRValue": "0x601006", 121 121 + "PEBS": "1", 122 122 + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", 123 123 + "SampleAfterValue": "100007", 124 124 + "UMask": "0x3", 125 125 + "Unit": "cpu_core" 126 126 + }, 127 127 + { 128 128 + "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", 129 129 + "EventCode": "0xc6", 130 130 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", 131 131 + "MSRIndex": "0x3F7", 132 132 + "MSRValue": "0x600206", 133 133 + "PEBS": "1", 134 134 + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", 135 135 + "SampleAfterValue": "100007", 136 136 + "UMask": "0x3", 137 137 + "Unit": "cpu_core" 138 138 + }, 139 139 + { 140 140 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", 141 141 + "EventCode": "0xc6", 142 142 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", 143 143 + "MSRIndex": "0x3F7", 144 144 + "MSRValue": "0x610006", 145 145 + "PEBS": "1", 146 146 + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", 147 147 + "SampleAfterValue": "100007", 148 148 + "UMask": "0x3", 149 149 + "Unit": "cpu_core" 150 150 + }, 151 151 + { 152 152 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", 153 153 + "EventCode": "0xc6", 154 154 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", 155 155 + "MSRIndex": "0x3F7", 156 156 + "MSRValue": "0x100206", 157 157 + "PEBS": "1", 158 158 + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", 159 159 + "SampleAfterValue": "100007", 160 160 + "UMask": "0x3", 161 161 + "Unit": "cpu_core" 162 162 + }, 163 163 + { 164 164 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", 165 165 + "EventCode": "0xc6", 166 166 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", 167 167 + "MSRIndex": "0x3F7", 168 168 + "MSRValue": "0x602006", 169 169 + "PEBS": "1", 170 170 + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", 171 171 + "SampleAfterValue": "100007", 172 172 + "UMask": "0x3", 173 173 + "Unit": "cpu_core" 174 174 + }, 175 175 + { 176 176 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", 177 177 + "EventCode": "0xc6", 178 178 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", 179 179 + "MSRIndex": "0x3F7", 180 180 + "MSRValue": "0x600406", 181 181 + "PEBS": "1", 182 182 + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", 183 183 + "SampleAfterValue": "100007", 184 184 + "UMask": "0x3", 185 185 + "Unit": "cpu_core" 186 186 + }, 187 187 + { 188 188 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", 189 189 + "EventCode": "0xc6", 190 190 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", 191 191 + "MSRIndex": "0x3F7", 192 192 + "MSRValue": "0x620006", 193 193 + "PEBS": "1", 194 194 + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", 195 195 + "SampleAfterValue": "100007", 196 196 + "UMask": "0x3", 197 197 + "Unit": "cpu_core" 198 198 + }, 199 199 + { 200 200 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", 201 201 + "EventCode": "0xc6", 202 202 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", 203 203 + "MSRIndex": "0x3F7", 204 204 + "MSRValue": "0x604006", 205 205 + "PEBS": "1", 206 206 + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", 207 207 + "SampleAfterValue": "100007", 208 208 + "UMask": "0x3", 209 209 + "Unit": "cpu_core" 210 210 + }, 211 211 + { 212 212 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", 213 213 + "EventCode": "0xc6", 214 214 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", 215 215 + "MSRIndex": "0x3F7", 216 216 + "MSRValue": "0x600806", 217 217 + "PEBS": "1", 218 218 + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", 219 219 + "SampleAfterValue": "100007", 220 220 + "UMask": "0x3", 221 221 + "Unit": "cpu_core" 222 222 + }, 223 223 + { 224 224 + "BriefDescription": "Mispredicted Retired ANT branches", 225 225 + "EventCode": "0xc6", 226 226 + "EventName": "FRONTEND_RETIRED.MISP_ANT", 227 227 + "MSRIndex": "0x3F7", 228 228 + "MSRValue": "0x9", 229 229 + "PEBS": "1", 230 230 + "PublicDescription": "ANT retired branches that got just mispredicted", 231 231 + "SampleAfterValue": "100007", 232 232 + "UMask": "0x2", 233 233 + "Unit": "cpu_core" 234 234 + }, 235 235 + { 236 236 + "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS", 237 237 + "EventCode": "0xc6", 238 238 + "EventName": "FRONTEND_RETIRED.MS_FLOWS", 239 239 + "MSRIndex": "0x3F7", 240 240 + "MSRValue": "0x8", 241 241 + "PEBS": "1", 242 242 + "SampleAfterValue": "100007", 243 243 + "UMask": "0x3", 244 244 + "Unit": "cpu_core" 245 245 + }, 246 246 + { 247 247 + "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", 248 248 + "EventCode": "0xc6", 249 249 + "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", 250 250 + "MSRIndex": "0x3F7", 251 251 + "MSRValue": "0x17", 252 252 + "PEBS": "1", 253 253 + "SampleAfterValue": "100007", 254 254 + "UMask": "0x3", 255 255 + "Unit": "cpu_core" 256 256 + }, 257 257 + { 3 258 "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", 4 259 "EventCode": "0x80", 5 260 "EventName": "ICACHE.ACCESSES", ··· 271 16 "Unit": "cpu_atom" 272 17 }, 273 18 { 19 19 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", 20 20 + "EventCode": "0x80", 21 21 + "EventName": "ICACHE_DATA.STALLS", 22 22 + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.", 23 23 + "SampleAfterValue": "500009", 24 24 + "UMask": "0x4", 25 25 + "Unit": "cpu_core" 26 26 + }, 27 27 + { 28 28 + "BriefDescription": "ICACHE_DATA.STALL_PERIODS", 29 29 + "CounterMask": "1", 30 30 + "EdgeDetect": "1", 31 31 + "EventCode": "0x80", 32 32 + "EventName": "ICACHE_DATA.STALL_PERIODS", 33 33 + "SampleAfterValue": "500009", 34 34 + "UMask": "0x4", 35 35 + "Unit": "cpu_core" 36 36 + }, 37 37 + { 38 38 + "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", 39 39 + "EventCode": "0x83", 40 40 + "EventName": "ICACHE_TAG.HIT", 41 41 + "PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", 42 42 + "SampleAfterValue": "200003", 43 43 + "UMask": "0x1", 44 44 + "Unit": "cpu_core" 45 45 + }, 46 46 + { 47 47 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 48 48 + "EventCode": "0x83", 49 49 + "EventName": "ICACHE_TAG.STALLS", 50 50 + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 51 51 + "SampleAfterValue": "200003", 52 52 + "UMask": "0x4", 53 53 + "Unit": "cpu_core" 54 54 + }, 55 55 + { 56 56 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 57 57 + "CounterMask": "1", 58 58 + "EventCode": "0x79", 59 59 + "EventName": "IDQ.DSB_CYCLES_ANY", 60 60 + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", 61 61 + "SampleAfterValue": "2000003", 62 62 + "UMask": "0x8", 63 63 + "Unit": "cpu_core" 64 64 + }, 65 65 + { 66 66 + "BriefDescription": "Cycles DSB is delivering optimal number of Uops", 67 67 + "CounterMask": "6", 68 68 + "EventCode": "0x79", 69 69 + "EventName": "IDQ.DSB_CYCLES_OK", 70 70 + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", 71 71 + "SampleAfterValue": "2000003", 72 72 + "UMask": "0x8", 73 73 + "Unit": "cpu_core" 74 74 + }, 75 75 + { 76 76 + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 77 77 + "EventCode": "0x79", 78 78 + "EventName": "IDQ.DSB_UOPS", 79 79 + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", 80 80 + "SampleAfterValue": "2000003", 81 81 + "UMask": "0x8", 82 82 + "Unit": "cpu_core" 83 83 + }, 84 84 + { 85 85 + "BriefDescription": "Cycles MITE is delivering any Uop", 86 86 + "CounterMask": "1", 87 87 + "EventCode": "0x79", 88 88 + "EventName": "IDQ.MITE_CYCLES_ANY", 89 89 + "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", 90 90 + "SampleAfterValue": "2000003", 91 91 + "UMask": "0x4", 92 92 + "Unit": "cpu_core" 93 93 + }, 94 94 + { 95 95 + "BriefDescription": "Cycles MITE is delivering optimal number of Uops", 96 96 + "CounterMask": "6", 97 97 + "EventCode": "0x79", 98 98 + "EventName": "IDQ.MITE_CYCLES_OK", 99 99 + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", 100 100 + "SampleAfterValue": "2000003", 101 101 + "UMask": "0x4", 102 102 + "Unit": "cpu_core" 103 103 + }, 104 104 + { 105 105 + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 106 106 + "EventCode": "0x79", 107 107 + "EventName": "IDQ.MITE_UOPS", 108 108 + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 109 109 + "SampleAfterValue": "2000003", 110 110 + "UMask": "0x4", 111 111 + "Unit": "cpu_core" 112 112 + }, 113 113 + { 114 114 + "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", 115 115 + "CounterMask": "1", 116 116 + "EventCode": "0x79", 117 117 + "EventName": "IDQ.MS_CYCLES_ANY", 118 118 + "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", 119 119 + "SampleAfterValue": "2000003", 120 120 + "UMask": "0x20", 121 121 + "Unit": "cpu_core" 122 122 + }, 123 123 + { 124 124 + "BriefDescription": "Number of switches from DSB or MITE to the MS", 125 125 + "CounterMask": "1", 126 126 + "EdgeDetect": "1", 127 127 + "EventCode": "0x79", 128 128 + "EventName": "IDQ.MS_SWITCHES", 129 129 + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", 130 130 + "SampleAfterValue": "100003", 131 131 + "UMask": "0x20", 132 132 + "Unit": "cpu_core" 133 133 + }, 134 134 + { 135 135 + "BriefDescription": "Uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", 136 136 + "EventCode": "0x79", 137 137 + "EventName": "IDQ.MS_UOPS", 138 138 + "PublicDescription": "Counts the number of uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", 139 139 + "SampleAfterValue": "1000003", 140 140 + "UMask": "0x20", 141 141 + "Unit": "cpu_core" 142 142 + }, 143 143 + { 274 144 "BriefDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.", 275 145 "EventCode": "0x9c", 276 146 "EventName": "IDQ_BUBBLES.CORE", 277 147 "PublicDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.\nThe count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", 148 148 + "SampleAfterValue": "1000003", 149 149 + "UMask": "0x1", 150 150 + "Unit": "cpu_core" 151 151 + }, 152 152 + { 153 153 + "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled", 154 154 + "EventCode": "0x9c", 155 155 + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", 156 156 + "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", 157 157 + "SampleAfterValue": "1000003", 158 158 + "UMask": "0x1", 159 159 + "Unit": "cpu_core" 160 160 + }, 161 161 + { 162 162 + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled", 163 163 + "CounterMask": "6", 164 164 + "EventCode": "0x9c", 165 165 + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", 166 166 + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", 167 167 + "SampleAfterValue": "1000003", 168 168 + "UMask": "0x1", 169 169 + "Unit": "cpu_core" 170 170 + }, 171 171 + { 172 172 + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", 173 173 + "CounterMask": "1", 174 174 + "EventCode": "0x9c", 175 175 + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", 176 176 + "Invert": "1", 177 177 + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", 278 178 "SampleAfterValue": "1000003", 279 179 "UMask": "0x1", 280 180 "Unit": "cpu_core"

+112 -30

tools/perf/pmu-events/arch/x86/meteorlake/memory.json

reviewed

··· 1 1 [ 2 2 { 3 3 + "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 4 4 + "CounterMask": "2", 5 5 + "EventCode": "0xa3", 6 6 + "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 7 7 + "SampleAfterValue": "1000003", 8 8 + "UMask": "0x2", 9 9 + "Unit": "cpu_core" 10 10 + }, 11 11 + { 12 12 + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 13 13 + "CounterMask": "6", 14 14 + "EventCode": "0xa3", 15 15 + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 16 16 + "SampleAfterValue": "1000003", 17 17 + "UMask": "0x6", 18 18 + "Unit": "cpu_core" 19 19 + }, 20 20 + { 21 21 + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.", 22 22 + "EventCode": "0x05", 23 23 + "EventName": "LD_HEAD.ANY_AT_RET", 24 24 + "SampleAfterValue": "1000003", 25 25 + "UMask": "0xff", 26 26 + "Unit": "cpu_atom" 27 27 + }, 28 28 + { 29 29 + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.", 30 30 + "EventCode": "0x05", 31 31 + "EventName": "LD_HEAD.L1_BOUND_AT_RET", 32 32 + "SampleAfterValue": "1000003", 33 33 + "UMask": "0xf4", 34 34 + "Unit": "cpu_atom" 35 35 + }, 36 36 + { 37 37 + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.", 38 38 + "EventCode": "0x05", 39 39 + "EventName": "LD_HEAD.L1_MISS_AT_RET", 40 40 + "SampleAfterValue": "1000003", 41 41 + "UMask": "0x81", 42 42 + "Unit": "cpu_atom" 43 43 + }, 44 44 + { 45 45 + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.", 46 46 + "EventCode": "0x05", 47 47 + "EventName": "LD_HEAD.OTHER_AT_RET", 48 48 + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.", 49 49 + "SampleAfterValue": "1000003", 50 50 + "UMask": "0xc0", 51 51 + "Unit": "cpu_atom" 52 52 + }, 53 53 + { 54 54 + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.", 55 55 + "EventCode": "0x05", 56 56 + "EventName": "LD_HEAD.PGWALK_AT_RET", 57 57 + "SampleAfterValue": "1000003", 58 58 + "UMask": "0xa0", 59 59 + "Unit": "cpu_atom" 60 60 + }, 61 61 + { 62 62 + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.", 63 63 + "EventCode": "0x05", 64 64 + "EventName": "LD_HEAD.ST_ADDR_AT_RET", 65 65 + "SampleAfterValue": "1000003", 66 66 + "UMask": "0x84", 67 67 + "Unit": "cpu_atom" 68 68 + }, 69 69 + { 70 70 + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 71 71 + "CounterMask": "3", 72 72 + "EventCode": "0x47", 73 73 + "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", 74 74 + "SampleAfterValue": "1000003", 75 75 + "UMask": "0x3", 76 76 + "Unit": "cpu_core" 77 77 + }, 78 78 + { 79 79 + "BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding.", 80 80 + "CounterMask": "5", 81 81 + "EventCode": "0x47", 82 82 + "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", 83 83 + "PublicDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).", 84 84 + "SampleAfterValue": "1000003", 85 85 + "UMask": "0x5", 86 86 + "Unit": "cpu_core" 87 87 + }, 88 88 + { 89 89 + "BriefDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding.", 90 90 + "CounterMask": "9", 91 91 + "EventCode": "0x47", 92 92 + "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", 93 93 + "PublicDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).", 94 94 + "SampleAfterValue": "1000003", 95 95 + "UMask": "0x9", 96 96 + "Unit": "cpu_core" 97 97 + }, 98 98 + { 3 99 "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 4 100 "Data_LA": "1", 5 101 "EventCode": "0xcd", ··· 211 115 "Unit": "cpu_core" 212 116 }, 213 117 { 214 214 - "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", 215 215 - "EventCode": "0xB7", 216 216 - "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 217 217 - "MSRIndex": "0x1a6,0x1a7", 218 218 - "MSRValue": "0x3FBFC00001", 219 219 - "SampleAfterValue": "100003", 220 220 - "UMask": "0x1", 118 118 + "BriefDescription": "Counts misaligned loads that are 4K page splits.", 119 119 + "EventCode": "0x13", 120 120 + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", 121 121 + "PEBS": "1", 122 122 + "SampleAfterValue": "200003", 123 123 + "UMask": "0x2", 221 124 "Unit": "cpu_atom" 222 125 }, 223 126 { 224 224 - "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", 225 225 - "EventCode": "0x2A,0x2B", 226 226 - "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 227 227 - "MSRIndex": "0x1a6,0x1a7", 228 228 - "MSRValue": "0x3FBFC00001", 229 229 - "SampleAfterValue": "100003", 230 230 - "UMask": "0x1", 231 231 - "Unit": "cpu_core" 232 232 - }, 233 233 - { 234 234 - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 235 235 - "EventCode": "0xB7", 236 236 - "EventName": "OCR.DEMAND_RFO.L3_MISS", 237 237 - "MSRIndex": "0x1a6,0x1a7", 238 238 - "MSRValue": "0x3FBFC00002", 239 239 - "SampleAfterValue": "100003", 240 240 - "UMask": "0x1", 127 127 + "BriefDescription": "Counts misaligned stores that are 4K page splits.", 128 128 + "EventCode": "0x13", 129 129 + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", 130 130 + "PEBS": "1", 131 131 + "SampleAfterValue": "200003", 132 132 + "UMask": "0x4", 241 133 "Unit": "cpu_atom" 242 134 }, 243 135 { 244 244 - "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", 245 245 - "EventCode": "0x2A,0x2B", 246 246 - "EventName": "OCR.DEMAND_RFO.L3_MISS", 247 247 - "MSRIndex": "0x1a6,0x1a7", 248 248 - "MSRValue": "0x3FBFC00002", 136 136 + "BriefDescription": "Counts demand data read requests that miss the L3 cache.", 137 137 + "EventCode": "0x21", 138 138 + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 249 139 "SampleAfterValue": "100003", 250 250 - "UMask": "0x1", 140 140 + "UMask": "0x10", 251 141 "Unit": "cpu_core" 252 142 } 253 143 ]

+34 -25

tools/perf/pmu-events/arch/x86/meteorlake/other.json

reviewed

··· 1 1 [ 2 2 { 3 3 - "BriefDescription": "Counts demand data reads that have any type of response.", 4 4 - "EventCode": "0xB7", 5 5 - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 6 6 - "MSRIndex": "0x1a6,0x1a7", 7 7 - "MSRValue": "0x10001", 8 8 - "SampleAfterValue": "100003", 9 9 - "UMask": "0x1", 10 10 - "Unit": "cpu_atom" 11 11 - }, 12 12 - { 13 13 - "BriefDescription": "Counts demand data reads that have any type of response.", 3 3 + "BriefDescription": "Counts streaming stores that have any type of response.", 14 4 "EventCode": "0x2A,0x2B", 15 15 - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 5 5 + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 16 6 "MSRIndex": "0x1a6,0x1a7", 17 17 - "MSRValue": "0x10001", 7 7 + "MSRValue": "0x10800", 18 8 "SampleAfterValue": "100003", 19 9 "UMask": "0x1", 20 10 "Unit": "cpu_core" 21 11 }, 22 12 { 23 23 - "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 24 24 - "EventCode": "0xB7", 25 25 - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 26 26 - "MSRIndex": "0x1a6,0x1a7", 27 27 - "MSRValue": "0x10002", 13 13 + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", 14 14 + "EventCode": "0xa5", 15 15 + "EventName": "RS.EMPTY", 16 16 + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)", 17 17 + "SampleAfterValue": "1000003", 18 18 + "UMask": "0x7", 19 19 + "Unit": "cpu_core" 20 20 + }, 21 21 + { 22 22 + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", 23 23 + "CounterMask": "1", 24 24 + "EdgeDetect": "1", 25 25 + "EventCode": "0xa5", 26 26 + "EventName": "RS.EMPTY_COUNT", 27 27 + "Invert": "1", 28 28 + "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", 28 29 "SampleAfterValue": "100003", 29 29 - "UMask": "0x1", 30 30 + "UMask": "0x7", 31 31 + "Unit": "cpu_core" 32 32 + }, 33 33 + { 34 34 + "BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state)", 35 35 + "EventCode": "0x75", 36 36 + "EventName": "SERIALIZATION.C01_MS_SCB", 37 37 + "SampleAfterValue": "200003", 38 38 + "UMask": "0x4", 30 39 "Unit": "cpu_atom" 31 40 }, 32 41 { 33 33 - "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 34 34 - "EventCode": "0x2A,0x2B", 35 35 - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 36 36 - "MSRIndex": "0x1a6,0x1a7", 37 37 - "MSRValue": "0x10002", 38 38 - "SampleAfterValue": "100003", 42 42 + "BriefDescription": "Cycles the uncore cannot take further requests", 43 43 + "CounterMask": "1", 44 44 + "EventCode": "0x2d", 45 45 + "EventName": "XQ.FULL_CYCLES", 46 46 + "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).", 47 47 + "SampleAfterValue": "1000003", 39 48 "UMask": "0x1", 40 49 "Unit": "cpu_core" 41 50 }

+1118 -3

tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json

reviewed

··· 1 1 [ 2 2 { 3 3 + "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", 4 4 + "CounterMask": "1", 5 5 + "EventCode": "0xb0", 6 6 + "EventName": "ARITH.DIV_ACTIVE", 7 7 + "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", 8 8 + "SampleAfterValue": "1000003", 9 9 + "UMask": "0x9", 10 10 + "Unit": "cpu_core" 11 11 + }, 12 12 + { 13 13 + "BriefDescription": "This event counts the cycles the integer divider is busy.", 14 14 + "CounterMask": "1", 15 15 + "EventCode": "0xb0", 16 16 + "EventName": "ARITH.IDIV_ACTIVE", 17 17 + "SampleAfterValue": "1000003", 18 18 + "UMask": "0x8", 19 19 + "Unit": "cpu_core" 20 20 + }, 21 21 + { 22 22 + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", 23 23 + "EventCode": "0xc1", 24 24 + "EventName": "ASSISTS.ANY", 25 25 + "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.", 26 26 + "SampleAfterValue": "100003", 27 27 + "UMask": "0x1b", 28 28 + "Unit": "cpu_core" 29 29 + }, 30 30 + { 3 31 "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", 4 32 "EventCode": "0xc4", 5 33 "EventName": "BR_INST_RETIRED.ALL_BRANCHES", ··· 43 15 "PEBS": "1", 44 16 "PublicDescription": "Counts all branch instructions retired.", 45 17 "SampleAfterValue": "400009", 18 18 + "Unit": "cpu_core" 19 19 + }, 20 20 + { 21 21 + "BriefDescription": "Conditional branch instructions retired.", 22 22 + "EventCode": "0xc4", 23 23 + "EventName": "BR_INST_RETIRED.COND", 24 24 + "PEBS": "1", 25 25 + "PublicDescription": "Counts conditional branch instructions retired.", 26 26 + "SampleAfterValue": "400009", 27 27 + "UMask": "0x11", 28 28 + "Unit": "cpu_core" 29 29 + }, 30 30 + { 31 31 + "BriefDescription": "Not taken branch instructions retired.", 32 32 + "EventCode": "0xc4", 33 33 + "EventName": "BR_INST_RETIRED.COND_NTAKEN", 34 34 + "PEBS": "1", 35 35 + "PublicDescription": "Counts not taken branch instructions retired.", 36 36 + "SampleAfterValue": "400009", 37 37 + "UMask": "0x10", 38 38 + "Unit": "cpu_core" 39 39 + }, 40 40 + { 41 41 + "BriefDescription": "Taken conditional branch instructions retired.", 42 42 + "EventCode": "0xc4", 43 43 + "EventName": "BR_INST_RETIRED.COND_TAKEN", 44 44 + "PEBS": "1", 45 45 + "PublicDescription": "Counts taken conditional branch instructions retired.", 46 46 + "SampleAfterValue": "400009", 47 47 + "UMask": "0x1", 48 48 + "Unit": "cpu_core" 49 49 + }, 50 50 + { 51 51 + "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.", 52 52 + "EventCode": "0xc4", 53 53 + "EventName": "BR_INST_RETIRED.FAR_BRANCH", 54 54 + "PEBS": "1", 55 55 + "SampleAfterValue": "200003", 56 56 + "UMask": "0xbf", 57 57 + "Unit": "cpu_atom" 58 58 + }, 59 59 + { 60 60 + "BriefDescription": "Far branch instructions retired.", 61 61 + "EventCode": "0xc4", 62 62 + "EventName": "BR_INST_RETIRED.FAR_BRANCH", 63 63 + "PEBS": "1", 64 64 + "PublicDescription": "Counts far branch instructions retired.", 65 65 + "SampleAfterValue": "100007", 66 66 + "UMask": "0x40", 67 67 + "Unit": "cpu_core" 68 68 + }, 69 69 + { 70 70 + "BriefDescription": "Indirect near branch instructions retired (excluding returns)", 71 71 + "EventCode": "0xc4", 72 72 + "EventName": "BR_INST_RETIRED.INDIRECT", 73 73 + "PEBS": "1", 74 74 + "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", 75 75 + "SampleAfterValue": "100003", 76 76 + "UMask": "0x80", 77 77 + "Unit": "cpu_core" 78 78 + }, 79 79 + { 80 80 + "BriefDescription": "Counts the number of near CALL branch instructions retired.", 81 81 + "EventCode": "0xc4", 82 82 + "EventName": "BR_INST_RETIRED.NEAR_CALL", 83 83 + "PEBS": "1", 84 84 + "SampleAfterValue": "200003", 85 85 + "UMask": "0xf9", 86 86 + "Unit": "cpu_atom" 87 87 + }, 88 88 + { 89 89 + "BriefDescription": "Direct and indirect near call instructions retired.", 90 90 + "EventCode": "0xc4", 91 91 + "EventName": "BR_INST_RETIRED.NEAR_CALL", 92 92 + "PEBS": "1", 93 93 + "PublicDescription": "Counts both direct and indirect near call instructions retired.", 94 94 + "SampleAfterValue": "100007", 95 95 + "UMask": "0x2", 96 96 + "Unit": "cpu_core" 97 97 + }, 98 98 + { 99 99 + "BriefDescription": "Return instructions retired.", 100 100 + "EventCode": "0xc4", 101 101 + "EventName": "BR_INST_RETIRED.NEAR_RETURN", 102 102 + "PEBS": "1", 103 103 + "PublicDescription": "Counts return instructions retired.", 104 104 + "SampleAfterValue": "100007", 105 105 + "UMask": "0x8", 106 106 + "Unit": "cpu_core" 107 107 + }, 108 108 + { 109 109 + "BriefDescription": "Taken branch instructions retired.", 110 110 + "EventCode": "0xc4", 111 111 + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", 112 112 + "PEBS": "1", 113 113 + "PublicDescription": "Counts taken branch instructions retired.", 114 114 + "SampleAfterValue": "400009", 115 115 + "UMask": "0x20", 46 116 "Unit": "cpu_core" 47 117 }, 48 118 { ··· 162 36 "Unit": "cpu_core" 163 37 }, 164 38 { 39 39 + "BriefDescription": "All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", 40 40 + "EventCode": "0xc5", 41 41 + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_COST", 42 42 + "PEBS": "1", 43 43 + "SampleAfterValue": "400009", 44 44 + "UMask": "0x44", 45 45 + "Unit": "cpu_core" 46 46 + }, 47 47 + { 48 48 + "BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.", 49 49 + "EventCode": "0xc5", 50 50 + "EventName": "BR_MISP_RETIRED.COND", 51 51 + "PEBS": "1", 52 52 + "SampleAfterValue": "200003", 53 53 + "UMask": "0x7e", 54 54 + "Unit": "cpu_atom" 55 55 + }, 56 56 + { 57 57 + "BriefDescription": "Mispredicted conditional branch instructions retired.", 58 58 + "EventCode": "0xc5", 59 59 + "EventName": "BR_MISP_RETIRED.COND", 60 60 + "PEBS": "1", 61 61 + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", 62 62 + "SampleAfterValue": "400009", 63 63 + "UMask": "0x11", 64 64 + "Unit": "cpu_core" 65 65 + }, 66 66 + { 67 67 + "BriefDescription": "Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", 68 68 + "EventCode": "0xc5", 69 69 + "EventName": "BR_MISP_RETIRED.COND_COST", 70 70 + "PEBS": "1", 71 71 + "SampleAfterValue": "400009", 72 72 + "UMask": "0x51", 73 73 + "Unit": "cpu_core" 74 74 + }, 75 75 + { 76 76 + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", 77 77 + "EventCode": "0xc5", 78 78 + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", 79 79 + "PEBS": "1", 80 80 + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", 81 81 + "SampleAfterValue": "400009", 82 82 + "UMask": "0x10", 83 83 + "Unit": "cpu_core" 84 84 + }, 85 85 + { 86 86 + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", 87 87 + "EventCode": "0xc5", 88 88 + "EventName": "BR_MISP_RETIRED.COND_NTAKEN_COST", 89 89 + "PEBS": "1", 90 90 + "SampleAfterValue": "400009", 91 91 + "UMask": "0x50", 92 92 + "Unit": "cpu_core" 93 93 + }, 94 94 + { 95 95 + "BriefDescription": "number of branch instructions retired that were mispredicted and taken.", 96 96 + "EventCode": "0xc5", 97 97 + "EventName": "BR_MISP_RETIRED.COND_TAKEN", 98 98 + "PEBS": "1", 99 99 + "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", 100 100 + "SampleAfterValue": "400009", 101 101 + "UMask": "0x1", 102 102 + "Unit": "cpu_core" 103 103 + }, 104 104 + { 105 105 + "BriefDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", 106 106 + "EventCode": "0xc5", 107 107 + "EventName": "BR_MISP_RETIRED.COND_TAKEN_COST", 108 108 + "PEBS": "1", 109 109 + "SampleAfterValue": "400009", 110 110 + "UMask": "0x41", 111 111 + "Unit": "cpu_core" 112 112 + }, 113 113 + { 114 114 + "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.", 115 115 + "EventCode": "0xc5", 116 116 + "EventName": "BR_MISP_RETIRED.INDIRECT", 117 117 + "PEBS": "1", 118 118 + "SampleAfterValue": "200003", 119 119 + "UMask": "0xeb", 120 120 + "Unit": "cpu_atom" 121 121 + }, 122 122 + { 123 123 + "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)", 124 124 + "EventCode": "0xc5", 125 125 + "EventName": "BR_MISP_RETIRED.INDIRECT", 126 126 + "PEBS": "1", 127 127 + "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", 128 128 + "SampleAfterValue": "100003", 129 129 + "UMask": "0x80", 130 130 + "Unit": "cpu_core" 131 131 + }, 132 132 + { 133 133 + "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.", 134 134 + "EventCode": "0xc5", 135 135 + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", 136 136 + "PEBS": "1", 137 137 + "SampleAfterValue": "200003", 138 138 + "UMask": "0xfb", 139 139 + "Unit": "cpu_atom" 140 140 + }, 141 141 + { 142 142 + "BriefDescription": "Mispredicted indirect CALL retired.", 143 143 + "EventCode": "0xc5", 144 144 + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", 145 145 + "PEBS": "1", 146 146 + "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", 147 147 + "SampleAfterValue": "400009", 148 148 + "UMask": "0x2", 149 149 + "Unit": "cpu_core" 150 150 + }, 151 151 + { 152 152 + "BriefDescription": "Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", 153 153 + "EventCode": "0xc5", 154 154 + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL_COST", 155 155 + "PEBS": "1", 156 156 + "SampleAfterValue": "400009", 157 157 + "UMask": "0x42", 158 158 + "Unit": "cpu_core" 159 159 + }, 160 160 + { 161 161 + "BriefDescription": "Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", 162 162 + "EventCode": "0xc5", 163 163 + "EventName": "BR_MISP_RETIRED.INDIRECT_COST", 164 164 + "PEBS": "1", 165 165 + "SampleAfterValue": "100003", 166 166 + "UMask": "0xc0", 167 167 + "Unit": "cpu_core" 168 168 + }, 169 169 + { 170 170 + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", 171 171 + "EventCode": "0xc5", 172 172 + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", 173 173 + "PEBS": "1", 174 174 + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", 175 175 + "SampleAfterValue": "400009", 176 176 + "UMask": "0x20", 177 177 + "Unit": "cpu_core" 178 178 + }, 179 179 + { 180 180 + "BriefDescription": "Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", 181 181 + "EventCode": "0xc5", 182 182 + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN_COST", 183 183 + "PEBS": "1", 184 184 + "SampleAfterValue": "400009", 185 185 + "UMask": "0x60", 186 186 + "Unit": "cpu_core" 187 187 + }, 188 188 + { 189 189 + "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.", 190 190 + "EventCode": "0xc5", 191 191 + "EventName": "BR_MISP_RETIRED.RETURN", 192 192 + "PEBS": "1", 193 193 + "SampleAfterValue": "200003", 194 194 + "UMask": "0xf7", 195 195 + "Unit": "cpu_atom" 196 196 + }, 197 197 + { 198 198 + "BriefDescription": "Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.", 199 199 + "EventCode": "0xc5", 200 200 + "EventName": "BR_MISP_RETIRED.RET_COST", 201 201 + "PEBS": "1", 202 202 + "SampleAfterValue": "100007", 203 203 + "UMask": "0x48", 204 204 + "Unit": "cpu_core" 205 205 + }, 206 206 + { 165 207 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", 166 208 "EventName": "CPU_CLK_UNHALTED.CORE", 167 209 "SampleAfterValue": "2000003", ··· 342 48 "EventName": "CPU_CLK_UNHALTED.CORE_P", 343 49 "SampleAfterValue": "2000003", 344 50 "Unit": "cpu_atom" 51 51 + }, 52 52 + { 53 53 + "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", 54 54 + "EventCode": "0xec", 55 55 + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", 56 56 + "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", 57 57 + "SampleAfterValue": "2000003", 58 58 + "UMask": "0x2", 59 59 + "Unit": "cpu_core" 60 60 + }, 61 61 + { 62 62 + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", 63 63 + "EventCode": "0x3c", 64 64 + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", 65 65 + "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.", 66 66 + "SampleAfterValue": "25003", 67 67 + "UMask": "0x2", 68 68 + "Unit": "cpu_core" 69 69 + }, 70 70 + { 71 71 + "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", 72 72 + "EventCode": "0x3c", 73 73 + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", 74 74 + "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", 75 75 + "SampleAfterValue": "2000003", 76 76 + "UMask": "0x8", 77 77 + "Unit": "cpu_core" 345 78 }, 346 79 { 347 80 "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", ··· 384 63 "SampleAfterValue": "2000003", 385 64 "UMask": "0x3", 386 65 "Unit": "cpu_core" 66 66 + }, 67 67 + { 68 68 + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", 69 69 + "EventCode": "0x3c", 70 70 + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", 71 71 + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.", 72 72 + "SampleAfterValue": "2000003", 73 73 + "UMask": "0x1", 74 74 + "Unit": "cpu_atom" 387 75 }, 388 76 { 389 77 "BriefDescription": "Reference cycles when the core is not in halt state.", ··· 434 104 "Unit": "cpu_core" 435 105 }, 436 106 { 107 107 + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", 108 108 + "CounterMask": "8", 109 109 + "EventCode": "0xa3", 110 110 + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", 111 111 + "SampleAfterValue": "1000003", 112 112 + "UMask": "0x8", 113 113 + "Unit": "cpu_core" 114 114 + }, 115 115 + { 116 116 + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", 117 117 + "CounterMask": "1", 118 118 + "EventCode": "0xa3", 119 119 + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", 120 120 + "SampleAfterValue": "1000003", 121 121 + "UMask": "0x1", 122 122 + "Unit": "cpu_core" 123 123 + }, 124 124 + { 125 125 + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", 126 126 + "CounterMask": "16", 127 127 + "EventCode": "0xa3", 128 128 + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", 129 129 + "SampleAfterValue": "1000003", 130 130 + "UMask": "0x10", 131 131 + "Unit": "cpu_core" 132 132 + }, 133 133 + { 134 134 + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 135 135 + "CounterMask": "12", 136 136 + "EventCode": "0xa3", 137 137 + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", 138 138 + "SampleAfterValue": "1000003", 139 139 + "UMask": "0xc", 140 140 + "Unit": "cpu_core" 141 141 + }, 142 142 + { 143 143 + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", 144 144 + "CounterMask": "5", 145 145 + "EventCode": "0xa3", 146 146 + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", 147 147 + "SampleAfterValue": "1000003", 148 148 + "UMask": "0x5", 149 149 + "Unit": "cpu_core" 150 150 + }, 151 151 + { 152 152 + "BriefDescription": "Total execution stalls.", 153 153 + "CounterMask": "4", 154 154 + "EventCode": "0xa3", 155 155 + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", 156 156 + "SampleAfterValue": "1000003", 157 157 + "UMask": "0x4", 158 158 + "Unit": "cpu_core" 159 159 + }, 160 160 + { 161 161 + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", 162 162 + "EventCode": "0xa6", 163 163 + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", 164 164 + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", 165 165 + "SampleAfterValue": "2000003", 166 166 + "UMask": "0x2", 167 167 + "Unit": "cpu_core" 168 168 + }, 169 169 + { 170 170 + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", 171 171 + "EventCode": "0xa6", 172 172 + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", 173 173 + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", 174 174 + "SampleAfterValue": "2000003", 175 175 + "UMask": "0x4", 176 176 + "Unit": "cpu_core" 177 177 + }, 178 178 + { 179 179 + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", 180 180 + "EventCode": "0xa6", 181 181 + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", 182 182 + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", 183 183 + "SampleAfterValue": "2000003", 184 184 + "UMask": "0x8", 185 185 + "Unit": "cpu_core" 186 186 + }, 187 187 + { 188 188 + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", 189 189 + "EventCode": "0xa6", 190 190 + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", 191 191 + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", 192 192 + "SampleAfterValue": "2000003", 193 193 + "UMask": "0x10", 194 194 + "Unit": "cpu_core" 195 195 + }, 196 196 + { 197 197 + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", 198 198 + "CounterMask": "5", 199 199 + "EventCode": "0xa6", 200 200 + "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", 201 201 + "SampleAfterValue": "2000003", 202 202 + "UMask": "0x21", 203 203 + "Unit": "cpu_core" 204 204 + }, 205 205 + { 206 206 + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", 207 207 + "CounterMask": "2", 208 208 + "EventCode": "0xa6", 209 209 + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", 210 210 + "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", 211 211 + "SampleAfterValue": "1000003", 212 212 + "UMask": "0x40", 213 213 + "Unit": "cpu_core" 214 214 + }, 215 215 + { 216 216 + "BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.", 217 217 + "EventCode": "0xa6", 218 218 + "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", 219 219 + "PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.", 220 220 + "SampleAfterValue": "1000003", 221 221 + "UMask": "0x80", 222 222 + "Unit": "cpu_core" 223 223 + }, 224 224 + { 225 225 + "BriefDescription": "Instruction decoders utilized in a cycle", 226 226 + "EventCode": "0x75", 227 227 + "EventName": "INST_DECODED.DECODERS", 228 228 + "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.", 229 229 + "SampleAfterValue": "2000003", 230 230 + "UMask": "0x1", 231 231 + "Unit": "cpu_core" 232 232 + }, 233 233 + { 437 234 "BriefDescription": "Fixed Counter: Counts the number of instructions retired", 438 235 "EventName": "INST_RETIRED.ANY", 439 236 "PEBS": "1", ··· 595 138 "Unit": "cpu_core" 596 139 }, 597 140 { 598 598 - "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", 141 141 + "BriefDescription": "INST_RETIRED.MACRO_FUSED", 142 142 + "EventCode": "0xc0", 143 143 + "EventName": "INST_RETIRED.MACRO_FUSED", 144 144 + "SampleAfterValue": "2000003", 145 145 + "UMask": "0x10", 146 146 + "Unit": "cpu_core" 147 147 + }, 148 148 + { 149 149 + "BriefDescription": "Precise instruction retired with PEBS precise-distribution", 150 150 + "EventName": "INST_RETIRED.PREC_DIST", 151 151 + "PEBS": "1", 152 152 + "PublicDescription": "A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0.", 153 153 + "SampleAfterValue": "2000003", 154 154 + "UMask": "0x1", 155 155 + "Unit": "cpu_core" 156 156 + }, 157 157 + { 158 158 + "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", 159 159 + "CounterMask": "1", 160 160 + "EventCode": "0xad", 161 161 + "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", 162 162 + "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", 163 163 + "SampleAfterValue": "2000003", 164 164 + "UMask": "0x3", 165 165 + "Unit": "cpu_core" 166 166 + }, 167 167 + { 168 168 + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", 169 169 + "EventCode": "0xad", 170 170 + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", 171 171 + "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", 172 172 + "SampleAfterValue": "500009", 173 173 + "UMask": "0x80", 174 174 + "Unit": "cpu_core" 175 175 + }, 176 176 + { 177 177 + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", 178 178 + "EventCode": "0xad", 179 179 + "EventName": "INT_MISC.RECOVERY_CYCLES", 180 180 + "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", 181 181 + "SampleAfterValue": "500009", 182 182 + "UMask": "0x1", 183 183 + "Unit": "cpu_core" 184 184 + }, 185 185 + { 186 186 + "BriefDescription": "INT_MISC.UNKNOWN_BRANCH_CYCLES", 187 187 + "EventCode": "0xad", 188 188 + "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES", 189 189 + "MSRIndex": "0x3F7", 190 190 + "MSRValue": "0x7", 191 191 + "SampleAfterValue": "1000003", 192 192 + "UMask": "0x40", 193 193 + "Unit": "cpu_core" 194 194 + }, 195 195 + { 196 196 + "BriefDescription": "TMA slots where uops got dropped", 197 197 + "EventCode": "0xad", 198 198 + "EventName": "INT_MISC.UOP_DROPPING", 199 199 + "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", 200 200 + "SampleAfterValue": "1000003", 201 201 + "UMask": "0x10", 202 202 + "Unit": "cpu_core" 203 203 + }, 204 204 + { 205 205 + "BriefDescription": "INT_VEC_RETIRED.128BIT", 206 206 + "EventCode": "0xe7", 207 207 + "EventName": "INT_VEC_RETIRED.128BIT", 208 208 + "SampleAfterValue": "1000003", 209 209 + "UMask": "0x13", 210 210 + "Unit": "cpu_core" 211 211 + }, 212 212 + { 213 213 + "BriefDescription": "INT_VEC_RETIRED.256BIT", 214 214 + "EventCode": "0xe7", 215 215 + "EventName": "INT_VEC_RETIRED.256BIT", 216 216 + "SampleAfterValue": "1000003", 217 217 + "UMask": "0xac", 218 218 + "Unit": "cpu_core" 219 219 + }, 220 220 + { 221 221 + "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.", 222 222 + "EventCode": "0xe7", 223 223 + "EventName": "INT_VEC_RETIRED.ADD_128", 224 224 + "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions.", 225 225 + "SampleAfterValue": "1000003", 226 226 + "UMask": "0x3", 227 227 + "Unit": "cpu_core" 228 228 + }, 229 229 + { 230 230 + "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.", 231 231 + "EventCode": "0xe7", 232 232 + "EventName": "INT_VEC_RETIRED.ADD_256", 233 233 + "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions.", 234 234 + "SampleAfterValue": "1000003", 235 235 + "UMask": "0xc", 236 236 + "Unit": "cpu_core" 237 237 + }, 238 238 + { 239 239 + "BriefDescription": "INT_VEC_RETIRED.MUL_256", 240 240 + "EventCode": "0xe7", 241 241 + "EventName": "INT_VEC_RETIRED.MUL_256", 242 242 + "SampleAfterValue": "1000003", 243 243 + "UMask": "0x80", 244 244 + "Unit": "cpu_core" 245 245 + }, 246 246 + { 247 247 + "BriefDescription": "INT_VEC_RETIRED.SHUFFLES", 248 248 + "EventCode": "0xe7", 249 249 + "EventName": "INT_VEC_RETIRED.SHUFFLES", 250 250 + "SampleAfterValue": "1000003", 251 251 + "UMask": "0x40", 252 252 + "Unit": "cpu_core" 253 253 + }, 254 254 + { 255 255 + "BriefDescription": "INT_VEC_RETIRED.VNNI_128", 256 256 + "EventCode": "0xe7", 257 257 + "EventName": "INT_VEC_RETIRED.VNNI_128", 258 258 + "SampleAfterValue": "1000003", 259 259 + "UMask": "0x10", 260 260 + "Unit": "cpu_core" 261 261 + }, 262 262 + { 263 263 + "BriefDescription": "INT_VEC_RETIRED.VNNI_256", 264 264 + "EventCode": "0xe7", 265 265 + "EventName": "INT_VEC_RETIRED.VNNI_256", 266 266 + "SampleAfterValue": "1000003", 267 267 + "UMask": "0x20", 268 268 + "Unit": "cpu_core" 269 269 + }, 270 270 + { 271 271 + "BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.", 272 272 + "EventCode": "0x03", 273 273 + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", 274 274 + "PEBS": "1", 275 275 + "SampleAfterValue": "1000003", 276 276 + "UMask": "0x4", 277 277 + "Unit": "cpu_atom" 278 278 + }, 279 279 + { 280 280 + "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", 281 281 + "EventCode": "0x03", 282 282 + "EventName": "LD_BLOCKS.DATA_UNKNOWN", 283 283 + "PEBS": "1", 284 284 + "SampleAfterValue": "1000003", 285 285 + "UMask": "0x1", 286 286 + "Unit": "cpu_atom" 287 287 + }, 288 288 + { 289 289 + "BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.", 599 290 "EventCode": "0x03", 600 291 "EventName": "LD_BLOCKS.STORE_FORWARD", 601 601 - "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", 292 292 + "PEBS": "1", 293 293 + "SampleAfterValue": "1000003", 294 294 + "UMask": "0x2", 295 295 + "Unit": "cpu_atom" 296 296 + }, 297 297 + { 298 298 + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", 299 299 + "CounterMask": "1", 300 300 + "EventCode": "0xa8", 301 301 + "EventName": "LSD.CYCLES_ACTIVE", 302 302 + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", 303 303 + "SampleAfterValue": "2000003", 304 304 + "UMask": "0x1", 305 305 + "Unit": "cpu_core" 306 306 + }, 307 307 + { 308 308 + "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", 309 309 + "CounterMask": "6", 310 310 + "EventCode": "0xa8", 311 311 + "EventName": "LSD.CYCLES_OK", 312 312 + "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", 313 313 + "SampleAfterValue": "2000003", 314 314 + "UMask": "0x1", 315 315 + "Unit": "cpu_core" 316 316 + }, 317 317 + { 318 318 + "BriefDescription": "Number of Uops delivered by the LSD.", 319 319 + "EventCode": "0xa8", 320 320 + "EventName": "LSD.UOPS", 321 321 + "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", 322 322 + "SampleAfterValue": "2000003", 323 323 + "UMask": "0x1", 324 324 + "Unit": "cpu_core" 325 325 + }, 326 326 + { 327 327 + "BriefDescription": "Number of machine clears (nukes) of any type.", 328 328 + "CounterMask": "1", 329 329 + "EdgeDetect": "1", 330 330 + "EventCode": "0xc3", 331 331 + "EventName": "MACHINE_CLEARS.COUNT", 332 332 + "PublicDescription": "Counts the number of machine clears (nukes) of any type.", 602 333 "SampleAfterValue": "100003", 603 603 - "UMask": "0x82", 334 334 + "UMask": "0x1", 335 335 + "Unit": "cpu_core" 336 336 + }, 337 337 + { 338 338 + "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", 339 339 + "EventCode": "0xc3", 340 340 + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", 341 341 + "SampleAfterValue": "20003", 342 342 + "UMask": "0x8", 343 343 + "Unit": "cpu_atom" 344 344 + }, 345 345 + { 346 346 + "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", 347 347 + "EventCode": "0xc3", 348 348 + "EventName": "MACHINE_CLEARS.PAGE_FAULT", 349 349 + "SampleAfterValue": "20003", 350 350 + "UMask": "0x20", 351 351 + "Unit": "cpu_atom" 352 352 + }, 353 353 + { 354 354 + "BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.", 355 355 + "EventCode": "0xc3", 356 356 + "EventName": "MACHINE_CLEARS.SLOW", 357 357 + "SampleAfterValue": "20003", 358 358 + "UMask": "0x6f", 359 359 + "Unit": "cpu_atom" 360 360 + }, 361 361 + { 362 362 + "BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.", 363 363 + "EventCode": "0xc3", 364 364 + "EventName": "MACHINE_CLEARS.SMC", 365 365 + "SampleAfterValue": "20003", 366 366 + "UMask": "0x1", 367 367 + "Unit": "cpu_atom" 368 368 + }, 369 369 + { 370 370 + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", 371 371 + "EventCode": "0xa2", 372 372 + "EventName": "RESOURCE_STALLS.SCOREBOARD", 373 373 + "SampleAfterValue": "100003", 374 374 + "UMask": "0x2", 604 375 "Unit": "cpu_core" 605 376 }, 606 377 { ··· 838 153 "PublicDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.\nThe count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", 839 154 "SampleAfterValue": "10000003", 840 155 "UMask": "0x2", 156 156 + "Unit": "cpu_core" 157 157 + }, 158 158 + { 159 159 + "BriefDescription": "TMA slots wasted due to incorrect speculations.", 160 160 + "EventCode": "0xa4", 161 161 + "EventName": "TOPDOWN.BAD_SPEC_SLOTS", 162 162 + "PublicDescription": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations.", 163 163 + "SampleAfterValue": "10000003", 164 164 + "UMask": "0x4", 165 165 + "Unit": "cpu_core" 166 166 + }, 167 167 + { 168 168 + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", 169 169 + "EventCode": "0xa4", 170 170 + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", 171 171 + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.", 172 172 + "SampleAfterValue": "10000003", 173 173 + "UMask": "0x8", 174 174 + "Unit": "cpu_core" 175 175 + }, 176 176 + { 177 177 + "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", 178 178 + "EventCode": "0xa4", 179 179 + "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", 180 180 + "SampleAfterValue": "10000003", 181 181 + "UMask": "0x10", 841 182 "Unit": "cpu_core" 842 183 }, 843 184 { ··· 892 181 "Unit": "cpu_atom" 893 182 }, 894 183 { 184 184 + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes", 185 185 + "EventCode": "0x73", 186 186 + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", 187 187 + "SampleAfterValue": "1000003", 188 188 + "UMask": "0x2", 189 189 + "Unit": "cpu_atom" 190 190 + }, 191 191 + { 192 192 + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", 193 193 + "EventCode": "0x73", 194 194 + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", 195 195 + "SampleAfterValue": "1000003", 196 196 + "UMask": "0x3", 197 197 + "Unit": "cpu_atom" 198 198 + }, 199 199 + { 200 200 + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", 201 201 + "EventCode": "0x73", 202 202 + "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", 203 203 + "SampleAfterValue": "1000003", 204 204 + "UMask": "0x1", 205 205 + "Unit": "cpu_atom" 206 206 + }, 207 207 + { 895 208 "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls", 896 209 "EventCode": "0x74", 897 210 "EventName": "TOPDOWN_BE_BOUND.ALL", ··· 923 188 "Unit": "cpu_atom" 924 189 }, 925 190 { 191 191 + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions", 192 192 + "EventCode": "0x74", 193 193 + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", 194 194 + "SampleAfterValue": "1000003", 195 195 + "UMask": "0x1", 196 196 + "Unit": "cpu_atom" 197 197 + }, 198 198 + { 199 199 + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).", 200 200 + "EventCode": "0x74", 201 201 + "EventName": "TOPDOWN_BE_BOUND.REGISTER", 202 202 + "SampleAfterValue": "1000003", 203 203 + "UMask": "0x20", 204 204 + "Unit": "cpu_atom" 205 205 + }, 206 206 + { 207 207 + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb", 208 208 + "EventCode": "0x74", 209 209 + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", 210 210 + "SampleAfterValue": "1000003", 211 211 + "UMask": "0x10", 212 212 + "Unit": "cpu_atom" 213 213 + }, 214 214 + { 926 215 "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls", 927 216 "EventCode": "0x71", 928 217 "EventName": "TOPDOWN_FE_BOUND.ALL", 929 218 "SampleAfterValue": "1000003", 219 219 + "Unit": "cpu_atom" 220 220 + }, 221 221 + { 222 222 + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear", 223 223 + "EventCode": "0x71", 224 224 + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", 225 225 + "SampleAfterValue": "1000003", 226 226 + "UMask": "0x2", 227 227 + "Unit": "cpu_atom" 228 228 + }, 229 229 + { 230 230 + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear", 231 231 + "EventCode": "0x71", 232 232 + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", 233 233 + "SampleAfterValue": "1000003", 234 234 + "UMask": "0x40", 235 235 + "Unit": "cpu_atom" 236 236 + }, 237 237 + { 238 238 + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ms", 239 239 + "EventCode": "0x71", 240 240 + "EventName": "TOPDOWN_FE_BOUND.CISC", 241 241 + "SampleAfterValue": "1000003", 242 242 + "UMask": "0x1", 243 243 + "Unit": "cpu_atom" 244 244 + }, 245 245 + { 246 246 + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall", 247 247 + "EventCode": "0x71", 248 248 + "EventName": "TOPDOWN_FE_BOUND.DECODE", 249 249 + "SampleAfterValue": "1000003", 250 250 + "UMask": "0x8", 251 251 + "Unit": "cpu_atom" 252 252 + }, 253 253 + { 254 254 + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", 255 255 + "EventCode": "0x71", 256 256 + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", 257 257 + "SampleAfterValue": "1000003", 258 258 + "UMask": "0x8d", 259 259 + "Unit": "cpu_atom" 260 260 + }, 261 261 + { 262 262 + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", 263 263 + "EventCode": "0x71", 264 264 + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", 265 265 + "SampleAfterValue": "1000003", 266 266 + "UMask": "0x72", 267 267 + "Unit": "cpu_atom" 268 268 + }, 269 269 + { 270 270 + "BriefDescription": "This event is deprecated. [This event is alias to TOPDOWN_FE_BOUND.ITLB_MISS]", 271 271 + "Deprecated": "1", 272 272 + "EventCode": "0x71", 273 273 + "EventName": "TOPDOWN_FE_BOUND.ITLB", 274 274 + "SampleAfterValue": "1000003", 275 275 + "UMask": "0x10", 276 276 + "Unit": "cpu_atom" 277 277 + }, 278 278 + { 279 279 + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss [This event is alias to TOPDOWN_FE_BOUND.ITLB]", 280 280 + "EventCode": "0x71", 281 281 + "EventName": "TOPDOWN_FE_BOUND.ITLB_MISS", 282 282 + "SampleAfterValue": "1000003", 283 283 + "UMask": "0x10", 284 284 + "Unit": "cpu_atom" 285 285 + }, 286 286 + { 287 287 + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong", 288 288 + "EventCode": "0x71", 289 289 + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", 290 290 + "SampleAfterValue": "1000003", 291 291 + "UMask": "0x4", 930 292 "Unit": "cpu_atom" 931 293 }, 932 294 { ··· 1035 203 "Unit": "cpu_atom" 1036 204 }, 1037 205 { 206 206 + "BriefDescription": "Number of non dec-by-all uops decoded by decoder", 207 207 + "EventCode": "0x76", 208 208 + "EventName": "UOPS_DECODED.DEC0_UOPS", 209 209 + "PublicDescription": "This event counts the number of not dec-by-all uops decoded by decoder 0.", 210 210 + "SampleAfterValue": "1000003", 211 211 + "UMask": "0x1", 212 212 + "Unit": "cpu_core" 213 213 + }, 214 214 + { 215 215 + "BriefDescription": "Uops executed on port 0", 216 216 + "EventCode": "0xb2", 217 217 + "EventName": "UOPS_DISPATCHED.PORT_0", 218 218 + "PublicDescription": "Number of uops dispatch to execution port 0.", 219 219 + "SampleAfterValue": "2000003", 220 220 + "UMask": "0x1", 221 221 + "Unit": "cpu_core" 222 222 + }, 223 223 + { 224 224 + "BriefDescription": "Uops executed on port 1", 225 225 + "EventCode": "0xb2", 226 226 + "EventName": "UOPS_DISPATCHED.PORT_1", 227 227 + "PublicDescription": "Number of uops dispatch to execution port 1.", 228 228 + "SampleAfterValue": "2000003", 229 229 + "UMask": "0x2", 230 230 + "Unit": "cpu_core" 231 231 + }, 232 232 + { 233 233 + "BriefDescription": "Uops executed on ports 2, 3 and 10", 234 234 + "EventCode": "0xb2", 235 235 + "EventName": "UOPS_DISPATCHED.PORT_2_3_10", 236 236 + "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10", 237 237 + "SampleAfterValue": "2000003", 238 238 + "UMask": "0x4", 239 239 + "Unit": "cpu_core" 240 240 + }, 241 241 + { 242 242 + "BriefDescription": "Uops executed on ports 4 and 9", 243 243 + "EventCode": "0xb2", 244 244 + "EventName": "UOPS_DISPATCHED.PORT_4_9", 245 245 + "PublicDescription": "Number of uops dispatch to execution ports 4 and 9", 246 246 + "SampleAfterValue": "2000003", 247 247 + "UMask": "0x10", 248 248 + "Unit": "cpu_core" 249 249 + }, 250 250 + { 251 251 + "BriefDescription": "Uops executed on ports 5 and 11", 252 252 + "EventCode": "0xb2", 253 253 + "EventName": "UOPS_DISPATCHED.PORT_5_11", 254 254 + "PublicDescription": "Number of uops dispatch to execution ports 5 and 11", 255 255 + "SampleAfterValue": "2000003", 256 256 + "UMask": "0x20", 257 257 + "Unit": "cpu_core" 258 258 + }, 259 259 + { 260 260 + "BriefDescription": "Uops executed on port 6", 261 261 + "EventCode": "0xb2", 262 262 + "EventName": "UOPS_DISPATCHED.PORT_6", 263 263 + "PublicDescription": "Number of uops dispatch to execution port 6.", 264 264 + "SampleAfterValue": "2000003", 265 265 + "UMask": "0x40", 266 266 + "Unit": "cpu_core" 267 267 + }, 268 268 + { 269 269 + "BriefDescription": "Uops executed on ports 7 and 8", 270 270 + "EventCode": "0xb2", 271 271 + "EventName": "UOPS_DISPATCHED.PORT_7_8", 272 272 + "PublicDescription": "Number of uops dispatch to execution ports 7 and 8.", 273 273 + "SampleAfterValue": "2000003", 274 274 + "UMask": "0x80", 275 275 + "Unit": "cpu_core" 276 276 + }, 277 277 + { 278 278 + "BriefDescription": "Number of uops executed on the core.", 279 279 + "EventCode": "0xb1", 280 280 + "EventName": "UOPS_EXECUTED.CORE", 281 281 + "PublicDescription": "Counts the number of uops executed from any thread.", 282 282 + "SampleAfterValue": "2000003", 283 283 + "UMask": "0x2", 284 284 + "Unit": "cpu_core" 285 285 + }, 286 286 + { 287 287 + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", 288 288 + "CounterMask": "1", 289 289 + "EventCode": "0xb1", 290 290 + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", 291 291 + "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", 292 292 + "SampleAfterValue": "2000003", 293 293 + "UMask": "0x2", 294 294 + "Unit": "cpu_core" 295 295 + }, 296 296 + { 297 297 + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", 298 298 + "CounterMask": "2", 299 299 + "EventCode": "0xb1", 300 300 + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", 301 301 + "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", 302 302 + "SampleAfterValue": "2000003", 303 303 + "UMask": "0x2", 304 304 + "Unit": "cpu_core" 305 305 + }, 306 306 + { 307 307 + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", 308 308 + "CounterMask": "3", 309 309 + "EventCode": "0xb1", 310 310 + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", 311 311 + "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", 312 312 + "SampleAfterValue": "2000003", 313 313 + "UMask": "0x2", 314 314 + "Unit": "cpu_core" 315 315 + }, 316 316 + { 317 317 + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", 318 318 + "CounterMask": "4", 319 319 + "EventCode": "0xb1", 320 320 + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", 321 321 + "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", 322 322 + "SampleAfterValue": "2000003", 323 323 + "UMask": "0x2", 324 324 + "Unit": "cpu_core" 325 325 + }, 326 326 + { 327 327 + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", 328 328 + "CounterMask": "1", 329 329 + "EventCode": "0xb1", 330 330 + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", 331 331 + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", 332 332 + "SampleAfterValue": "2000003", 333 333 + "UMask": "0x1", 334 334 + "Unit": "cpu_core" 335 335 + }, 336 336 + { 337 337 + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", 338 338 + "CounterMask": "2", 339 339 + "EventCode": "0xb1", 340 340 + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", 341 341 + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", 342 342 + "SampleAfterValue": "2000003", 343 343 + "UMask": "0x1", 344 344 + "Unit": "cpu_core" 345 345 + }, 346 346 + { 347 347 + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", 348 348 + "CounterMask": "3", 349 349 + "EventCode": "0xb1", 350 350 + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", 351 351 + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", 352 352 + "SampleAfterValue": "2000003", 353 353 + "UMask": "0x1", 354 354 + "Unit": "cpu_core" 355 355 + }, 356 356 + { 357 357 + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", 358 358 + "CounterMask": "4", 359 359 + "EventCode": "0xb1", 360 360 + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", 361 361 + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", 362 362 + "SampleAfterValue": "2000003", 363 363 + "UMask": "0x1", 364 364 + "Unit": "cpu_core" 365 365 + }, 366 366 + { 367 367 + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", 368 368 + "CounterMask": "1", 369 369 + "EventCode": "0xb1", 370 370 + "EventName": "UOPS_EXECUTED.STALLS", 371 371 + "Invert": "1", 372 372 + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", 373 373 + "SampleAfterValue": "2000003", 374 374 + "UMask": "0x1", 375 375 + "Unit": "cpu_core" 376 376 + }, 377 377 + { 378 378 + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", 379 379 + "EventCode": "0xb1", 380 380 + "EventName": "UOPS_EXECUTED.THREAD", 381 381 + "SampleAfterValue": "2000003", 382 382 + "UMask": "0x1", 383 383 + "Unit": "cpu_core" 384 384 + }, 385 385 + { 386 386 + "BriefDescription": "Counts the number of x87 uops dispatched.", 387 387 + "EventCode": "0xb1", 388 388 + "EventName": "UOPS_EXECUTED.X87", 389 389 + "PublicDescription": "Counts the number of x87 uops executed.", 390 390 + "SampleAfterValue": "2000003", 391 391 + "UMask": "0x10", 392 392 + "Unit": "cpu_core" 393 393 + }, 394 394 + { 395 395 + "BriefDescription": "Counts the number of uops issued by the front end every cycle.", 396 396 + "EventCode": "0x0e", 397 397 + "EventName": "UOPS_ISSUED.ANY", 398 398 + "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.", 399 399 + "SampleAfterValue": "1000003", 400 400 + "Unit": "cpu_atom" 401 401 + }, 402 402 + { 403 403 + "BriefDescription": "Uops that RAT issues to RS", 404 404 + "EventCode": "0xae", 405 405 + "EventName": "UOPS_ISSUED.ANY", 406 406 + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", 407 407 + "SampleAfterValue": "2000003", 408 408 + "UMask": "0x1", 409 409 + "Unit": "cpu_core" 410 410 + }, 411 411 + { 412 412 + "BriefDescription": "UOPS_ISSUED.CYCLES", 413 413 + "CounterMask": "1", 414 414 + "EventCode": "0xae", 415 415 + "EventName": "UOPS_ISSUED.CYCLES", 416 416 + "SampleAfterValue": "2000003", 417 417 + "UMask": "0x1", 418 418 + "Unit": "cpu_core" 419 419 + }, 420 420 + { 421 421 + "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", 422 422 + "CounterMask": "1", 423 423 + "EventCode": "0xae", 424 424 + "EventName": "UOPS_ISSUED.STALLS", 425 425 + "Invert": "1", 426 426 + "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", 427 427 + "SampleAfterValue": "1000003", 428 428 + "UMask": "0x1", 429 429 + "Unit": "cpu_core" 430 430 + }, 431 431 + { 432 432 + "BriefDescription": "Retired uops except the last uop of each instruction.", 433 433 + "EventCode": "0xc2", 434 434 + "EventName": "UOPS_RETIRED.HEAVY", 435 435 + "PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count.", 436 436 + "SampleAfterValue": "2000003", 437 437 + "UMask": "0x1", 438 438 + "Unit": "cpu_core" 439 439 + }, 440 440 + { 441 441 + "BriefDescription": "Counts the number of integer divide uops retired.", 442 442 + "EventCode": "0xc2", 443 443 + "EventName": "UOPS_RETIRED.IDIV", 444 444 + "PEBS": "1", 445 445 + "SampleAfterValue": "2000003", 446 446 + "UMask": "0x10", 447 447 + "Unit": "cpu_atom" 448 448 + }, 449 449 + { 450 450 + "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", 451 451 + "EventCode": "0xc2", 452 452 + "EventName": "UOPS_RETIRED.MS", 453 453 + "PEBS": "1", 454 454 + "SampleAfterValue": "2000003", 455 455 + "UMask": "0x1", 456 456 + "Unit": "cpu_atom" 457 457 + }, 458 458 + { 459 459 + "BriefDescription": "UOPS_RETIRED.MS", 460 460 + "EventCode": "0xc2", 461 461 + "EventName": "UOPS_RETIRED.MS", 462 462 + "MSRIndex": "0x3F7", 463 463 + "MSRValue": "0x8", 464 464 + "SampleAfterValue": "2000003", 465 465 + "UMask": "0x4", 466 466 + "Unit": "cpu_core" 467 467 + }, 468 468 + { 1038 469 "BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.", 1039 470 "EventCode": "0xc2", 1040 471 "EventName": "UOPS_RETIRED.SLOTS", ··· 1305 210 "SampleAfterValue": "2000003", 1306 211 "UMask": "0x2", 1307 212 "Unit": "cpu_core" 213 213 + }, 214 214 + { 215 215 + "BriefDescription": "Cycles with less than 10 actually retired uops.", 216 216 + "CounterMask": "10", 217 217 + "EventCode": "0xc2", 218 218 + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", 219 219 + "Invert": "1", 220 220 + "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", 221 221 + "SampleAfterValue": "1000003", 222 222 + "UMask": "0x2", 223 223 + "Unit": "cpu_core" 224 224 + }, 225 225 + { 226 226 + "BriefDescription": "Counts the number of x87 uops retired, includes those in ms flows", 227 227 + "EventCode": "0xc2", 228 228 + "EventName": "UOPS_RETIRED.X87", 229 229 + "PEBS": "1", 230 230 + "SampleAfterValue": "2000003", 231 231 + "UMask": "0x2", 232 232 + "Unit": "cpu_atom" 1308 233 } 1309 234 ]

+18

tools/perf/pmu-events/arch/x86/meteorlake/uncore-cache.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "Number of all entries allocated. Includes also retries.", 4 4 + "EventCode": "0x35", 5 5 + "EventName": "UNC_HAC_CBO_TOR_ALLOCATION.ALL", 6 6 + "PerPkg": "1", 7 7 + "UMask": "0x8", 8 8 + "Unit": "HAC_CBO" 9 9 + }, 10 10 + { 11 11 + "BriefDescription": "Asserted on coherent DRD + DRdPref allocations into the queue. Cacheable only", 12 12 + "EventCode": "0x35", 13 13 + "EventName": "UNC_HAC_CBO_TOR_ALLOCATION.DRD", 14 14 + "PerPkg": "1", 15 15 + "UMask": "0x1", 16 16 + "Unit": "HAC_CBO" 17 17 + } 18 18 + ]

+42

tools/perf/pmu-events/arch/x86/meteorlake/uncore-interconnect.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches", 4 4 + "EventCode": "0x81", 5 5 + "EventName": "UNC_HAC_ARB_REQ_TRK_REQUEST.DRD", 6 6 + "PerPkg": "1", 7 7 + "UMask": "0x2", 8 8 + "Unit": "HAC_ARB" 9 9 + }, 10 10 + { 11 11 + "BriefDescription": "Number of all CMI transactions", 12 12 + "EventCode": "0x8a", 13 13 + "EventName": "UNC_HAC_ARB_TRANSACTIONS.ALL", 14 14 + "PerPkg": "1", 15 15 + "UMask": "0x1", 16 16 + "Unit": "HAC_ARB" 17 17 + }, 18 18 + { 19 19 + "BriefDescription": "Number of all CMI reads", 20 20 + "EventCode": "0x8a", 21 21 + "EventName": "UNC_HAC_ARB_TRANSACTIONS.READS", 22 22 + "PerPkg": "1", 23 23 + "UMask": "0x2", 24 24 + "Unit": "HAC_ARB" 25 25 + }, 26 26 + { 27 27 + "BriefDescription": "Number of all CMI writes not including Mflush", 28 28 + "EventCode": "0x8a", 29 29 + "EventName": "UNC_HAC_ARB_TRANSACTIONS.WRITES", 30 30 + "PerPkg": "1", 31 31 + "UMask": "0x4", 32 32 + "Unit": "HAC_ARB" 33 33 + }, 34 34 + { 35 35 + "BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", 36 36 + "EventCode": "0x81", 37 37 + "EventName": "UNC_HAC_ARB_TRK_REQUESTS.ALL", 38 38 + "PerPkg": "1", 39 39 + "UMask": "0x1", 40 40 + "Unit": "HAC_ARB" 41 41 + } 42 42 + ]

+126

tools/perf/pmu-events/arch/x86/meteorlake/uncore-memory.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels).", 4 4 + "EventCode": "0xff", 5 5 + "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", 6 6 + "PerPkg": "1", 7 7 + "PublicDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data.", 8 8 + "UMask": "0x20", 9 9 + "Unit": "imc_free_running_0" 10 10 + }, 11 11 + { 12 12 + "BriefDescription": "Counts every read and write request entering the Memory Controller 0.", 13 13 + "EventCode": "0xff", 14 14 + "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", 15 15 + "PerPkg": "1", 16 16 + "PublicDescription": "Counts every read and write request entering the Memory Controller 0 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW.", 17 17 + "UMask": "0x10", 18 18 + "Unit": "imc_free_running_0" 19 19 + }, 20 20 + { 21 21 + "BriefDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels).", 22 22 + "EventCode": "0xff", 23 23 + "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", 24 24 + "PerPkg": "1", 25 25 + "PublicDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data.", 26 26 + "UMask": "0x30", 27 27 + "Unit": "imc_free_running_0" 28 28 + }, 29 29 + { 30 30 + "BriefDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels).", 31 31 + "EventCode": "0xff", 32 32 + "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", 33 33 + "PerPkg": "1", 34 34 + "PublicDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data.", 35 35 + "UMask": "0x20", 36 36 + "Unit": "imc_free_running_1" 37 37 + }, 38 38 + { 39 39 + "BriefDescription": "Counts every read and write request entering the Memory Controller 1.", 40 40 + "EventCode": "0xff", 41 41 + "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", 42 42 + "PerPkg": "1", 43 43 + "PublicDescription": "Counts every read and write request entering the Memory Controller 1 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW.", 44 44 + "UMask": "0x10", 45 45 + "Unit": "imc_free_running_1" 46 46 + }, 47 47 + { 48 48 + "BriefDescription": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels).", 49 49 + "EventCode": "0xff", 50 50 + "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", 51 51 + "PerPkg": "1", 52 52 + "PublicDescription": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data.", 53 53 + "UMask": "0x30", 54 54 + "Unit": "imc_free_running_1" 55 55 + }, 56 56 + { 57 57 + "BriefDescription": "ACT command for a read request sent to DRAM", 58 58 + "EventCode": "0x24", 59 59 + "EventName": "UNC_M_ACT_COUNT_RD", 60 60 + "PerPkg": "1", 61 61 + "Unit": "iMC" 62 62 + }, 63 63 + { 64 64 + "BriefDescription": "ACT command sent to DRAM", 65 65 + "EventCode": "0x26", 66 66 + "EventName": "UNC_M_ACT_COUNT_TOTAL", 67 67 + "PerPkg": "1", 68 68 + "Unit": "iMC" 69 69 + }, 70 70 + { 71 71 + "BriefDescription": "ACT command for a write request sent to DRAM", 72 72 + "EventCode": "0x25", 73 73 + "EventName": "UNC_M_ACT_COUNT_WR", 74 74 + "PerPkg": "1", 75 75 + "Unit": "iMC" 76 76 + }, 77 77 + { 78 78 + "BriefDescription": "Read CAS command sent to DRAM", 79 79 + "EventCode": "0x22", 80 80 + "EventName": "UNC_M_CAS_COUNT_RD", 81 81 + "PerPkg": "1", 82 82 + "Unit": "iMC" 83 83 + }, 84 84 + { 85 85 + "BriefDescription": "Write CAS command sent to DRAM", 86 86 + "EventCode": "0x23", 87 87 + "EventName": "UNC_M_CAS_COUNT_WR", 88 88 + "PerPkg": "1", 89 89 + "Unit": "iMC" 90 90 + }, 91 91 + { 92 92 + "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration", 93 93 + "EventCode": "0x28", 94 94 + "EventName": "UNC_M_PRE_COUNT_IDLE", 95 95 + "PerPkg": "1", 96 96 + "Unit": "iMC" 97 97 + }, 98 98 + { 99 99 + "BriefDescription": "PRE command sent to DRAM for a read/write request", 100 100 + "EventCode": "0x27", 101 101 + "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", 102 102 + "PerPkg": "1", 103 103 + "Unit": "iMC" 104 104 + }, 105 105 + { 106 106 + "BriefDescription": "Number of bytes read from DRAM, in 32B chunks. Counter increments by 1 after receiving 32B chunk data.", 107 107 + "EventCode": "0x3A", 108 108 + "EventName": "UNC_M_RD_DATA", 109 109 + "PerPkg": "1", 110 110 + "Unit": "iMC" 111 111 + }, 112 112 + { 113 113 + "BriefDescription": "Total number of read and write byte transfers to/from DRAM, in 32B chunks. Counter increments by 1 after sending or receiving 32B chunk data.", 114 114 + "EventCode": "0x3C", 115 115 + "EventName": "UNC_M_TOTAL_DATA", 116 116 + "PerPkg": "1", 117 117 + "Unit": "iMC" 118 118 + }, 119 119 + { 120 120 + "BriefDescription": "Number of bytes written to DRAM, in 32B chunks. Counter increments by 1 after sending 32B chunk data.", 121 121 + "EventCode": "0x3B", 122 122 + "EventName": "UNC_M_WR_DATA", 123 123 + "PerPkg": "1", 124 124 + "Unit": "iMC" 125 125 + } 126 126 + ]

+257

tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json

reviewed

··· 1 1 [ 2 2 { 3 3 + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.", 4 4 + "EventCode": "0x08", 5 5 + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 6 6 + "SampleAfterValue": "200003", 7 7 + "UMask": "0x20", 8 8 + "Unit": "cpu_atom" 9 9 + }, 10 10 + { 11 11 + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", 12 12 + "EventCode": "0x12", 13 13 + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 14 14 + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", 15 15 + "SampleAfterValue": "100003", 16 16 + "UMask": "0x20", 17 17 + "Unit": "cpu_core" 18 18 + }, 19 19 + { 20 20 + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", 21 21 + "CounterMask": "1", 22 22 + "EventCode": "0x12", 23 23 + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", 24 24 + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", 25 25 + "SampleAfterValue": "100003", 26 26 + "UMask": "0x10", 27 27 + "Unit": "cpu_core" 28 28 + }, 29 29 + { 30 30 + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses.", 31 31 + "EventCode": "0x08", 32 32 + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 33 33 + "SampleAfterValue": "200003", 34 34 + "UMask": "0xe", 35 35 + "Unit": "cpu_atom" 36 36 + }, 37 37 + { 3 38 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", 4 39 "EventCode": "0x12", 5 40 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", ··· 44 9 "Unit": "cpu_core" 45 10 }, 46 11 { 12 12 + "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", 13 13 + "EventCode": "0x12", 14 14 + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 15 15 + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 16 16 + "SampleAfterValue": "100003", 17 17 + "UMask": "0x8", 18 18 + "Unit": "cpu_core" 19 19 + }, 20 20 + { 21 21 + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.", 22 22 + "EventCode": "0x08", 23 23 + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 24 24 + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.", 25 25 + "SampleAfterValue": "200003", 26 26 + "UMask": "0x4", 27 27 + "Unit": "cpu_atom" 28 28 + }, 29 29 + { 30 30 + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", 31 31 + "EventCode": "0x12", 32 32 + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 33 33 + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 34 34 + "SampleAfterValue": "100003", 35 35 + "UMask": "0x4", 36 36 + "Unit": "cpu_core" 37 37 + }, 38 38 + { 39 39 + "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", 40 40 + "EventCode": "0x12", 41 41 + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 42 42 + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 43 43 + "SampleAfterValue": "100003", 44 44 + "UMask": "0x2", 45 45 + "Unit": "cpu_core" 46 46 + }, 47 47 + { 48 48 + "BriefDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.", 49 49 + "EventCode": "0x08", 50 50 + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", 51 51 + "PublicDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", 52 52 + "SampleAfterValue": "200003", 53 53 + "UMask": "0x10", 54 54 + "Unit": "cpu_atom" 55 55 + }, 56 56 + { 57 57 + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", 58 58 + "EventCode": "0x12", 59 59 + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", 60 60 + "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", 61 61 + "SampleAfterValue": "100003", 62 62 + "UMask": "0x10", 63 63 + "Unit": "cpu_core" 64 64 + }, 65 65 + { 66 66 + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB.", 67 67 + "EventCode": "0x49", 68 68 + "EventName": "DTLB_STORE_MISSES.STLB_HIT", 69 69 + "SampleAfterValue": "2000003", 70 70 + "UMask": "0x20", 71 71 + "Unit": "cpu_atom" 72 72 + }, 73 73 + { 74 74 + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", 75 75 + "EventCode": "0x13", 76 76 + "EventName": "DTLB_STORE_MISSES.STLB_HIT", 77 77 + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 78 78 + "SampleAfterValue": "100003", 79 79 + "UMask": "0x20", 80 80 + "Unit": "cpu_core" 81 81 + }, 82 82 + { 83 83 + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", 84 84 + "CounterMask": "1", 85 85 + "EventCode": "0x13", 86 86 + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", 87 87 + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", 88 88 + "SampleAfterValue": "100003", 89 89 + "UMask": "0x10", 90 90 + "Unit": "cpu_core" 91 91 + }, 92 92 + { 93 93 + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.", 94 94 + "EventCode": "0x49", 95 95 + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 96 96 + "SampleAfterValue": "2000003", 97 97 + "UMask": "0xe", 98 98 + "Unit": "cpu_atom" 99 99 + }, 100 100 + { 47 101 "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", 48 102 "EventCode": "0x13", 49 103 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 50 104 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 51 105 "SampleAfterValue": "100003", 52 106 "UMask": "0xe", 107 107 + "Unit": "cpu_core" 108 108 + }, 109 109 + { 110 110 + "BriefDescription": "Page walks completed due to a demand data store to a 1G page.", 111 111 + "EventCode": "0x13", 112 112 + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 113 113 + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 114 114 + "SampleAfterValue": "100003", 115 115 + "UMask": "0x8", 116 116 + "Unit": "cpu_core" 117 117 + }, 118 118 + { 119 119 + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", 120 120 + "EventCode": "0x13", 121 121 + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 122 122 + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 123 123 + "SampleAfterValue": "100003", 124 124 + "UMask": "0x4", 125 125 + "Unit": "cpu_core" 126 126 + }, 127 127 + { 128 128 + "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", 129 129 + "EventCode": "0x13", 130 130 + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 131 131 + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 132 132 + "SampleAfterValue": "100003", 133 133 + "UMask": "0x2", 134 134 + "Unit": "cpu_core" 135 135 + }, 136 136 + { 137 137 + "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.", 138 138 + "EventCode": "0x49", 139 139 + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", 140 140 + "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", 141 141 + "SampleAfterValue": "200003", 142 142 + "UMask": "0x10", 143 143 + "Unit": "cpu_atom" 144 144 + }, 145 145 + { 146 146 + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", 147 147 + "EventCode": "0x13", 148 148 + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", 149 149 + "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", 150 150 + "SampleAfterValue": "100003", 151 151 + "UMask": "0x10", 152 152 + "Unit": "cpu_core" 153 153 + }, 154 154 + { 155 155 + "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", 156 156 + "EventCode": "0x85", 157 157 + "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", 158 158 + "SampleAfterValue": "1000003", 159 159 + "UMask": "0x1", 160 160 + "Unit": "cpu_atom" 161 161 + }, 162 162 + { 163 163 + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.", 164 164 + "EventCode": "0x85", 165 165 + "EventName": "ITLB_MISSES.STLB_HIT", 166 166 + "SampleAfterValue": "2000003", 167 167 + "UMask": "0x20", 168 168 + "Unit": "cpu_atom" 169 169 + }, 170 170 + { 171 171 + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", 172 172 + "EventCode": "0x11", 173 173 + "EventName": "ITLB_MISSES.STLB_HIT", 174 174 + "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", 175 175 + "SampleAfterValue": "100003", 176 176 + "UMask": "0x20", 177 177 + "Unit": "cpu_core" 178 178 + }, 179 179 + { 180 180 + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", 181 181 + "CounterMask": "1", 182 182 + "EventCode": "0x11", 183 183 + "EventName": "ITLB_MISSES.WALK_ACTIVE", 184 184 + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", 185 185 + "SampleAfterValue": "100003", 186 186 + "UMask": "0x10", 53 187 "Unit": "cpu_core" 54 188 }, 55 189 { ··· 238 34 "SampleAfterValue": "100003", 239 35 "UMask": "0xe", 240 36 "Unit": "cpu_core" 37 37 + }, 38 38 + { 39 39 + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.", 40 40 + "EventCode": "0x85", 41 41 + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", 42 42 + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.", 43 43 + "SampleAfterValue": "2000003", 44 44 + "UMask": "0x4", 45 45 + "Unit": "cpu_atom" 46 46 + }, 47 47 + { 48 48 + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", 49 49 + "EventCode": "0x11", 50 50 + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", 51 51 + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", 52 52 + "SampleAfterValue": "100003", 53 53 + "UMask": "0x4", 54 54 + "Unit": "cpu_core" 55 55 + }, 56 56 + { 57 57 + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", 58 58 + "EventCode": "0x11", 59 59 + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", 60 60 + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", 61 61 + "SampleAfterValue": "100003", 62 62 + "UMask": "0x2", 63 63 + "Unit": "cpu_core" 64 64 + }, 65 65 + { 66 66 + "BriefDescription": "Counts the number of page walks outstanding for iside in PMH every cycle.", 67 67 + "EventCode": "0x85", 68 68 + "EventName": "ITLB_MISSES.WALK_PENDING", 69 69 + "PublicDescription": "Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks.", 70 70 + "SampleAfterValue": "200003", 71 71 + "UMask": "0x10", 72 72 + "Unit": "cpu_atom" 73 73 + }, 74 74 + { 75 75 + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", 76 76 + "EventCode": "0x11", 77 77 + "EventName": "ITLB_MISSES.WALK_PENDING", 78 78 + "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", 79 79 + "SampleAfterValue": "100003", 80 80 + "UMask": "0x10", 81 81 + "Unit": "cpu_core" 82 82 + }, 83 83 + { 84 84 + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.", 85 85 + "EventCode": "0x05", 86 86 + "EventName": "LD_HEAD.DTLB_MISS_AT_RET", 87 87 + "SampleAfterValue": "1000003", 88 88 + "UMask": "0x90", 89 89 + "Unit": "cpu_atom" 241 90 } 242 91 ]

+894

tools/perf/pmu-events/arch/x86/rocketlake/cache.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", 4 4 + "EventCode": "0x51", 5 5 + "EventName": "L1D.REPLACEMENT", 6 6 + "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 7 7 + "SampleAfterValue": "100003", 8 8 + "UMask": "0x1" 9 9 + }, 10 10 + { 11 11 + "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", 12 12 + "EventCode": "0x48", 13 13 + "EventName": "L1D_PEND_MISS.FB_FULL", 14 14 + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 15 15 + "SampleAfterValue": "1000003", 16 16 + "UMask": "0x2" 17 17 + }, 18 18 + { 19 19 + "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.", 20 20 + "CounterMask": "1", 21 21 + "EdgeDetect": "1", 22 22 + "EventCode": "0x48", 23 23 + "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", 24 24 + "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 25 25 + "SampleAfterValue": "1000003", 26 26 + "UMask": "0x2" 27 27 + }, 28 28 + { 29 29 + "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", 30 30 + "EventCode": "0x48", 31 31 + "EventName": "L1D_PEND_MISS.L2_STALL", 32 32 + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 33 33 + "SampleAfterValue": "1000003", 34 34 + "UMask": "0x4" 35 35 + }, 36 36 + { 37 37 + "BriefDescription": "Number of L1D misses that are outstanding", 38 38 + "EventCode": "0x48", 39 39 + "EventName": "L1D_PEND_MISS.PENDING", 40 40 + "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 41 41 + "SampleAfterValue": "1000003", 42 42 + "UMask": "0x1" 43 43 + }, 44 44 + { 45 45 + "BriefDescription": "Cycles with L1D load Misses outstanding.", 46 46 + "CounterMask": "1", 47 47 + "EventCode": "0x48", 48 48 + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", 49 49 + "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", 50 50 + "SampleAfterValue": "1000003", 51 51 + "UMask": "0x1" 52 52 + }, 53 53 + { 54 54 + "BriefDescription": "L2 cache lines filling L2", 55 55 + "EventCode": "0xF1", 56 56 + "EventName": "L2_LINES_IN.ALL", 57 57 + "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", 58 58 + "SampleAfterValue": "100003", 59 59 + "UMask": "0x1f" 60 60 + }, 61 61 + { 62 62 + "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", 63 63 + "EventCode": "0xF2", 64 64 + "EventName": "L2_LINES_OUT.NON_SILENT", 65 65 + "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", 66 66 + "SampleAfterValue": "200003", 67 67 + "UMask": "0x2" 68 68 + }, 69 69 + { 70 70 + "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.", 71 71 + "EventCode": "0xF2", 72 72 + "EventName": "L2_LINES_OUT.SILENT", 73 73 + "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", 74 74 + "SampleAfterValue": "200003", 75 75 + "UMask": "0x1" 76 76 + }, 77 77 + { 78 78 + "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", 79 79 + "EventCode": "0xf2", 80 80 + "EventName": "L2_LINES_OUT.USELESS_HWPF", 81 81 + "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache", 82 82 + "SampleAfterValue": "200003", 83 83 + "UMask": "0x4" 84 84 + }, 85 85 + { 86 86 + "BriefDescription": "L2 code requests", 87 87 + "EventCode": "0x24", 88 88 + "EventName": "L2_RQSTS.ALL_CODE_RD", 89 89 + "PublicDescription": "Counts the total number of L2 code requests.", 90 90 + "SampleAfterValue": "200003", 91 91 + "UMask": "0xe4" 92 92 + }, 93 93 + { 94 94 + "BriefDescription": "Demand Data Read requests", 95 95 + "EventCode": "0x24", 96 96 + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", 97 97 + "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", 98 98 + "SampleAfterValue": "200003", 99 99 + "UMask": "0xe1" 100 100 + }, 101 101 + { 102 102 + "BriefDescription": "Demand requests that miss L2 cache", 103 103 + "EventCode": "0x24", 104 104 + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", 105 105 + "PublicDescription": "Counts demand requests that miss L2 cache.", 106 106 + "SampleAfterValue": "200003", 107 107 + "UMask": "0x27" 108 108 + }, 109 109 + { 110 110 + "BriefDescription": "Demand requests to L2 cache", 111 111 + "EventCode": "0x24", 112 112 + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", 113 113 + "PublicDescription": "Counts demand requests to L2 cache.", 114 114 + "SampleAfterValue": "200003", 115 115 + "UMask": "0xe7" 116 116 + }, 117 117 + { 118 118 + "BriefDescription": "RFO requests to L2 cache", 119 119 + "EventCode": "0x24", 120 120 + "EventName": "L2_RQSTS.ALL_RFO", 121 121 + "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", 122 122 + "SampleAfterValue": "200003", 123 123 + "UMask": "0xe2" 124 124 + }, 125 125 + { 126 126 + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", 127 127 + "EventCode": "0x24", 128 128 + "EventName": "L2_RQSTS.CODE_RD_HIT", 129 129 + "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", 130 130 + "SampleAfterValue": "200003", 131 131 + "UMask": "0xc4" 132 132 + }, 133 133 + { 134 134 + "BriefDescription": "L2 cache misses when fetching instructions", 135 135 + "EventCode": "0x24", 136 136 + "EventName": "L2_RQSTS.CODE_RD_MISS", 137 137 + "PublicDescription": "Counts L2 cache misses when fetching instructions.", 138 138 + "SampleAfterValue": "200003", 139 139 + "UMask": "0x24" 140 140 + }, 141 141 + { 142 142 + "BriefDescription": "Demand Data Read requests that hit L2 cache", 143 143 + "EventCode": "0x24", 144 144 + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", 145 145 + "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", 146 146 + "SampleAfterValue": "200003", 147 147 + "UMask": "0xc1" 148 148 + }, 149 149 + { 150 150 + "BriefDescription": "Demand Data Read miss L2, no rejects", 151 151 + "EventCode": "0x24", 152 152 + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", 153 153 + "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", 154 154 + "SampleAfterValue": "200003", 155 155 + "UMask": "0x21" 156 156 + }, 157 157 + { 158 158 + "BriefDescription": "All requests that miss L2 cache.", 159 159 + "EventCode": "0x24", 160 160 + "EventName": "L2_RQSTS.MISS", 161 161 + "PublicDescription": "Counts all requests that miss L2 cache.", 162 162 + "SampleAfterValue": "200003", 163 163 + "UMask": "0x3f" 164 164 + }, 165 165 + { 166 166 + "BriefDescription": "All L2 requests.", 167 167 + "EventCode": "0x24", 168 168 + "EventName": "L2_RQSTS.REFERENCES", 169 169 + "PublicDescription": "Counts all L2 requests.", 170 170 + "SampleAfterValue": "200003", 171 171 + "UMask": "0xff" 172 172 + }, 173 173 + { 174 174 + "BriefDescription": "RFO requests that hit L2 cache", 175 175 + "EventCode": "0x24", 176 176 + "EventName": "L2_RQSTS.RFO_HIT", 177 177 + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", 178 178 + "SampleAfterValue": "200003", 179 179 + "UMask": "0xc2" 180 180 + }, 181 181 + { 182 182 + "BriefDescription": "RFO requests that miss L2 cache", 183 183 + "EventCode": "0x24", 184 184 + "EventName": "L2_RQSTS.RFO_MISS", 185 185 + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", 186 186 + "SampleAfterValue": "200003", 187 187 + "UMask": "0x22" 188 188 + }, 189 189 + { 190 190 + "BriefDescription": "SW prefetch requests that hit L2 cache.", 191 191 + "EventCode": "0x24", 192 192 + "EventName": "L2_RQSTS.SWPF_HIT", 193 193 + "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", 194 194 + "SampleAfterValue": "200003", 195 195 + "UMask": "0xc8" 196 196 + }, 197 197 + { 198 198 + "BriefDescription": "SW prefetch requests that miss L2 cache.", 199 199 + "EventCode": "0x24", 200 200 + "EventName": "L2_RQSTS.SWPF_MISS", 201 201 + "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", 202 202 + "SampleAfterValue": "200003", 203 203 + "UMask": "0x28" 204 204 + }, 205 205 + { 206 206 + "BriefDescription": "L2 writebacks that access L2 cache", 207 207 + "EventCode": "0xF0", 208 208 + "EventName": "L2_TRANS.L2_WB", 209 209 + "PublicDescription": "Counts L2 writebacks that access L2 cache.", 210 210 + "SampleAfterValue": "200003", 211 211 + "UMask": "0x40" 212 212 + }, 213 213 + { 214 214 + "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", 215 215 + "EventCode": "0x2e", 216 216 + "EventName": "LONGEST_LAT_CACHE.MISS", 217 217 + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", 218 218 + "SampleAfterValue": "100003", 219 219 + "UMask": "0x41" 220 220 + }, 221 221 + { 222 222 + "BriefDescription": "Retired load instructions.", 223 223 + "Data_LA": "1", 224 224 + "EventCode": "0xd0", 225 225 + "EventName": "MEM_INST_RETIRED.ALL_LOADS", 226 226 + "PEBS": "1", 227 227 + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", 228 228 + "SampleAfterValue": "1000003", 229 229 + "UMask": "0x81" 230 230 + }, 231 231 + { 232 232 + "BriefDescription": "Retired store instructions.", 233 233 + "Data_LA": "1", 234 234 + "EventCode": "0xd0", 235 235 + "EventName": "MEM_INST_RETIRED.ALL_STORES", 236 236 + "PEBS": "1", 237 237 + "PublicDescription": "Counts all retired store instructions.", 238 238 + "SampleAfterValue": "1000003", 239 239 + "UMask": "0x82" 240 240 + }, 241 241 + { 242 242 + "BriefDescription": "All retired memory instructions.", 243 243 + "Data_LA": "1", 244 244 + "EventCode": "0xd0", 245 245 + "EventName": "MEM_INST_RETIRED.ANY", 246 246 + "PEBS": "1", 247 247 + "PublicDescription": "Counts all retired memory instructions - loads and stores.", 248 248 + "SampleAfterValue": "1000003", 249 249 + "UMask": "0x83" 250 250 + }, 251 251 + { 252 252 + "BriefDescription": "Retired load instructions with locked access.", 253 253 + "Data_LA": "1", 254 254 + "EventCode": "0xd0", 255 255 + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", 256 256 + "PEBS": "1", 257 257 + "PublicDescription": "Counts retired load instructions with locked access.", 258 258 + "SampleAfterValue": "100007", 259 259 + "UMask": "0x21" 260 260 + }, 261 261 + { 262 262 + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", 263 263 + "Data_LA": "1", 264 264 + "EventCode": "0xd0", 265 265 + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", 266 266 + "PEBS": "1", 267 267 + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", 268 268 + "SampleAfterValue": "100003", 269 269 + "UMask": "0x41" 270 270 + }, 271 271 + { 272 272 + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", 273 273 + "Data_LA": "1", 274 274 + "EventCode": "0xd0", 275 275 + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", 276 276 + "PEBS": "1", 277 277 + "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.", 278 278 + "SampleAfterValue": "100003", 279 279 + "UMask": "0x42" 280 280 + }, 281 281 + { 282 282 + "BriefDescription": "Retired load instructions that miss the STLB.", 283 283 + "Data_LA": "1", 284 284 + "EventCode": "0xd0", 285 285 + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", 286 286 + "PEBS": "1", 287 287 + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", 288 288 + "SampleAfterValue": "100003", 289 289 + "UMask": "0x11" 290 290 + }, 291 291 + { 292 292 + "BriefDescription": "Retired store instructions that miss the STLB.", 293 293 + "Data_LA": "1", 294 294 + "EventCode": "0xd0", 295 295 + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", 296 296 + "PEBS": "1", 297 297 + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", 298 298 + "SampleAfterValue": "100003", 299 299 + "UMask": "0x12" 300 300 + }, 301 301 + { 302 302 + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", 303 303 + "Data_LA": "1", 304 304 + "EventCode": "0xd2", 305 305 + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", 306 306 + "PEBS": "1", 307 307 + "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", 308 308 + "SampleAfterValue": "20011", 309 309 + "UMask": "0x2" 310 310 + }, 311 311 + { 312 312 + "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 313 313 + "Data_LA": "1", 314 314 + "EventCode": "0xd2", 315 315 + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", 316 316 + "PEBS": "1", 317 317 + "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", 318 318 + "SampleAfterValue": "20011", 319 319 + "UMask": "0x4" 320 320 + }, 321 321 + { 322 322 + "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", 323 323 + "Data_LA": "1", 324 324 + "EventCode": "0xd2", 325 325 + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", 326 326 + "PEBS": "1", 327 327 + "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", 328 328 + "SampleAfterValue": "20011", 329 329 + "UMask": "0x1" 330 330 + }, 331 331 + { 332 332 + "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", 333 333 + "Data_LA": "1", 334 334 + "EventCode": "0xd2", 335 335 + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", 336 336 + "PEBS": "1", 337 337 + "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.", 338 338 + "SampleAfterValue": "100003", 339 339 + "UMask": "0x8" 340 340 + }, 341 341 + { 342 342 + "BriefDescription": "Retired instructions with at least 1 uncacheable load or Bus Lock.", 343 343 + "Data_LA": "1", 344 344 + "EventCode": "0xd4", 345 345 + "EventName": "MEM_LOAD_MISC_RETIRED.UC", 346 346 + "PEBS": "1", 347 347 + "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).", 348 348 + "SampleAfterValue": "100007", 349 349 + "UMask": "0x4" 350 350 + }, 351 351 + { 352 352 + "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", 353 353 + "Data_LA": "1", 354 354 + "EventCode": "0xd1", 355 355 + "EventName": "MEM_LOAD_RETIRED.FB_HIT", 356 356 + "PEBS": "1", 357 357 + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", 358 358 + "SampleAfterValue": "100007", 359 359 + "UMask": "0x40" 360 360 + }, 361 361 + { 362 362 + "BriefDescription": "Retired load instructions with L1 cache hits as data sources", 363 363 + "Data_LA": "1", 364 364 + "EventCode": "0xd1", 365 365 + "EventName": "MEM_LOAD_RETIRED.L1_HIT", 366 366 + "PEBS": "1", 367 367 + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", 368 368 + "SampleAfterValue": "1000003", 369 369 + "UMask": "0x1" 370 370 + }, 371 371 + { 372 372 + "BriefDescription": "Retired load instructions missed L1 cache as data sources", 373 373 + "Data_LA": "1", 374 374 + "EventCode": "0xd1", 375 375 + "EventName": "MEM_LOAD_RETIRED.L1_MISS", 376 376 + "PEBS": "1", 377 377 + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", 378 378 + "SampleAfterValue": "200003", 379 379 + "UMask": "0x8" 380 380 + }, 381 381 + { 382 382 + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", 383 383 + "Data_LA": "1", 384 384 + "EventCode": "0xd1", 385 385 + "EventName": "MEM_LOAD_RETIRED.L2_HIT", 386 386 + "PEBS": "1", 387 387 + "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", 388 388 + "SampleAfterValue": "200003", 389 389 + "UMask": "0x2" 390 390 + }, 391 391 + { 392 392 + "BriefDescription": "Retired load instructions missed L2 cache as data sources", 393 393 + "Data_LA": "1", 394 394 + "EventCode": "0xd1", 395 395 + "EventName": "MEM_LOAD_RETIRED.L2_MISS", 396 396 + "PEBS": "1", 397 397 + "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", 398 398 + "SampleAfterValue": "100021", 399 399 + "UMask": "0x10" 400 400 + }, 401 401 + { 402 402 + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", 403 403 + "Data_LA": "1", 404 404 + "EventCode": "0xd1", 405 405 + "EventName": "MEM_LOAD_RETIRED.L3_HIT", 406 406 + "PEBS": "1", 407 407 + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", 408 408 + "SampleAfterValue": "100021", 409 409 + "UMask": "0x4" 410 410 + }, 411 411 + { 412 412 + "BriefDescription": "Retired load instructions missed L3 cache as data sources", 413 413 + "Data_LA": "1", 414 414 + "EventCode": "0xd1", 415 415 + "EventName": "MEM_LOAD_RETIRED.L3_MISS", 416 416 + "PEBS": "1", 417 417 + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", 418 418 + "SampleAfterValue": "50021", 419 419 + "UMask": "0x20" 420 420 + }, 421 421 + { 422 422 + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.", 423 423 + "EventCode": "0xB7, 0xBB", 424 424 + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", 425 425 + "MSRIndex": "0x1a6,0x1a7", 426 426 + "MSRValue": "0x3FC03C0004", 427 427 + "SampleAfterValue": "100003", 428 428 + "UMask": "0x1" 429 429 + }, 430 430 + { 431 431 + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", 432 432 + "EventCode": "0xB7, 0xBB", 433 433 + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", 434 434 + "MSRIndex": "0x1a6,0x1a7", 435 435 + "MSRValue": "0x10003C0004", 436 436 + "SampleAfterValue": "100003", 437 437 + "UMask": "0x1" 438 438 + }, 439 439 + { 440 440 + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", 441 441 + "EventCode": "0xB7, 0xBB", 442 442 + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", 443 443 + "MSRIndex": "0x1a6,0x1a7", 444 444 + "MSRValue": "0x4003C0004", 445 445 + "SampleAfterValue": "100003", 446 446 + "UMask": "0x1" 447 447 + }, 448 448 + { 449 449 + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", 450 450 + "EventCode": "0xB7, 0xBB", 451 451 + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", 452 452 + "MSRIndex": "0x1a6,0x1a7", 453 453 + "MSRValue": "0x2003C0004", 454 454 + "SampleAfterValue": "100003", 455 455 + "UMask": "0x1" 456 456 + }, 457 457 + { 458 458 + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", 459 459 + "EventCode": "0xB7, 0xBB", 460 460 + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", 461 461 + "MSRIndex": "0x1a6,0x1a7", 462 462 + "MSRValue": "0x1003C0004", 463 463 + "SampleAfterValue": "100003", 464 464 + "UMask": "0x1" 465 465 + }, 466 466 + { 467 467 + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.", 468 468 + "EventCode": "0xB7, 0xBB", 469 469 + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", 470 470 + "MSRIndex": "0x1a6,0x1a7", 471 471 + "MSRValue": "0x1E003C0004", 472 472 + "SampleAfterValue": "100003", 473 473 + "UMask": "0x1" 474 474 + }, 475 475 + { 476 476 + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.", 477 477 + "EventCode": "0xB7, 0xBB", 478 478 + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", 479 479 + "MSRIndex": "0x1a6,0x1a7", 480 480 + "MSRValue": "0x3FC03C0001", 481 481 + "SampleAfterValue": "100003", 482 482 + "UMask": "0x1" 483 483 + }, 484 484 + { 485 485 + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", 486 486 + "EventCode": "0xB7, 0xBB", 487 487 + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", 488 488 + "MSRIndex": "0x1a6,0x1a7", 489 489 + "MSRValue": "0x10003C0001", 490 490 + "SampleAfterValue": "100003", 491 491 + "UMask": "0x1" 492 492 + }, 493 493 + { 494 494 + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", 495 495 + "EventCode": "0xB7, 0xBB", 496 496 + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", 497 497 + "MSRIndex": "0x1a6,0x1a7", 498 498 + "MSRValue": "0x4003C0001", 499 499 + "SampleAfterValue": "100003", 500 500 + "UMask": "0x1" 501 501 + }, 502 502 + { 503 503 + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", 504 504 + "EventCode": "0xB7, 0xBB", 505 505 + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", 506 506 + "MSRIndex": "0x1a6,0x1a7", 507 507 + "MSRValue": "0x2003C0001", 508 508 + "SampleAfterValue": "100003", 509 509 + "UMask": "0x1" 510 510 + }, 511 511 + { 512 512 + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", 513 513 + "EventCode": "0xB7, 0xBB", 514 514 + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", 515 515 + "MSRIndex": "0x1a6,0x1a7", 516 516 + "MSRValue": "0x1003C0001", 517 517 + "SampleAfterValue": "100003", 518 518 + "UMask": "0x1" 519 519 + }, 520 520 + { 521 521 + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.", 522 522 + "EventCode": "0xB7, 0xBB", 523 523 + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", 524 524 + "MSRIndex": "0x1a6,0x1a7", 525 525 + "MSRValue": "0x1E003C0001", 526 526 + "SampleAfterValue": "100003", 527 527 + "UMask": "0x1" 528 528 + }, 529 529 + { 530 530 + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", 531 531 + "EventCode": "0xB7, 0xBB", 532 532 + "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", 533 533 + "MSRIndex": "0x1a6,0x1a7", 534 534 + "MSRValue": "0x3FC03C0002", 535 535 + "SampleAfterValue": "100003", 536 536 + "UMask": "0x1" 537 537 + }, 538 538 + { 539 539 + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", 540 540 + "EventCode": "0xB7, 0xBB", 541 541 + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", 542 542 + "MSRIndex": "0x1a6,0x1a7", 543 543 + "MSRValue": "0x10003C0002", 544 544 + "SampleAfterValue": "100003", 545 545 + "UMask": "0x1" 546 546 + }, 547 547 + { 548 548 + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", 549 549 + "EventCode": "0xB7, 0xBB", 550 550 + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", 551 551 + "MSRIndex": "0x1a6,0x1a7", 552 552 + "MSRValue": "0x4003C0002", 553 553 + "SampleAfterValue": "100003", 554 554 + "UMask": "0x1" 555 555 + }, 556 556 + { 557 557 + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", 558 558 + "EventCode": "0xB7, 0xBB", 559 559 + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", 560 560 + "MSRIndex": "0x1a6,0x1a7", 561 561 + "MSRValue": "0x2003C0002", 562 562 + "SampleAfterValue": "100003", 563 563 + "UMask": "0x1" 564 564 + }, 565 565 + { 566 566 + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", 567 567 + "EventCode": "0xB7, 0xBB", 568 568 + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", 569 569 + "MSRIndex": "0x1a6,0x1a7", 570 570 + "MSRValue": "0x1003C0002", 571 571 + "SampleAfterValue": "100003", 572 572 + "UMask": "0x1" 573 573 + }, 574 574 + { 575 575 + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.", 576 576 + "EventCode": "0xB7, 0xBB", 577 577 + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", 578 578 + "MSRIndex": "0x1a6,0x1a7", 579 579 + "MSRValue": "0x1E003C0002", 580 580 + "SampleAfterValue": "100003", 581 581 + "UMask": "0x1" 582 582 + }, 583 583 + { 584 584 + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", 585 585 + "EventCode": "0xB7, 0xBB", 586 586 + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", 587 587 + "MSRIndex": "0x1a6,0x1a7", 588 588 + "MSRValue": "0x3FC03C0400", 589 589 + "SampleAfterValue": "100003", 590 590 + "UMask": "0x1" 591 591 + }, 592 592 + { 593 593 + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", 594 594 + "EventCode": "0xB7, 0xBB", 595 595 + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", 596 596 + "MSRIndex": "0x1a6,0x1a7", 597 597 + "MSRValue": "0x2003C0400", 598 598 + "SampleAfterValue": "100003", 599 599 + "UMask": "0x1" 600 600 + }, 601 601 + { 602 602 + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", 603 603 + "EventCode": "0xB7, 0xBB", 604 604 + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", 605 605 + "MSRIndex": "0x1a6,0x1a7", 606 606 + "MSRValue": "0x1003C0400", 607 607 + "SampleAfterValue": "100003", 608 608 + "UMask": "0x1" 609 609 + }, 610 610 + { 611 611 + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", 612 612 + "EventCode": "0xB7, 0xBB", 613 613 + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", 614 614 + "MSRIndex": "0x1a6,0x1a7", 615 615 + "MSRValue": "0x3FC03C0010", 616 616 + "SampleAfterValue": "100003", 617 617 + "UMask": "0x1" 618 618 + }, 619 619 + { 620 620 + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", 621 621 + "EventCode": "0xB7, 0xBB", 622 622 + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", 623 623 + "MSRIndex": "0x1a6,0x1a7", 624 624 + "MSRValue": "0x10003C0010", 625 625 + "SampleAfterValue": "100003", 626 626 + "UMask": "0x1" 627 627 + }, 628 628 + { 629 629 + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", 630 630 + "EventCode": "0xB7, 0xBB", 631 631 + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", 632 632 + "MSRIndex": "0x1a6,0x1a7", 633 633 + "MSRValue": "0x4003C0010", 634 634 + "SampleAfterValue": "100003", 635 635 + "UMask": "0x1" 636 636 + }, 637 637 + { 638 638 + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", 639 639 + "EventCode": "0xB7, 0xBB", 640 640 + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", 641 641 + "MSRIndex": "0x1a6,0x1a7", 642 642 + "MSRValue": "0x2003C0010", 643 643 + "SampleAfterValue": "100003", 644 644 + "UMask": "0x1" 645 645 + }, 646 646 + { 647 647 + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", 648 648 + "EventCode": "0xB7, 0xBB", 649 649 + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", 650 650 + "MSRIndex": "0x1a6,0x1a7", 651 651 + "MSRValue": "0x1003C0010", 652 652 + "SampleAfterValue": "100003", 653 653 + "UMask": "0x1" 654 654 + }, 655 655 + { 656 656 + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", 657 657 + "EventCode": "0xB7, 0xBB", 658 658 + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", 659 659 + "MSRIndex": "0x1a6,0x1a7", 660 660 + "MSRValue": "0x1E003C0010", 661 661 + "SampleAfterValue": "100003", 662 662 + "UMask": "0x1" 663 663 + }, 664 664 + { 665 665 + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", 666 666 + "EventCode": "0xB7, 0xBB", 667 667 + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", 668 668 + "MSRIndex": "0x1a6,0x1a7", 669 669 + "MSRValue": "0x3FC03C0020", 670 670 + "SampleAfterValue": "100003", 671 671 + "UMask": "0x1" 672 672 + }, 673 673 + { 674 674 + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", 675 675 + "EventCode": "0xB7, 0xBB", 676 676 + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", 677 677 + "MSRIndex": "0x1a6,0x1a7", 678 678 + "MSRValue": "0x10003C0020", 679 679 + "SampleAfterValue": "100003", 680 680 + "UMask": "0x1" 681 681 + }, 682 682 + { 683 683 + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", 684 684 + "EventCode": "0xB7, 0xBB", 685 685 + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", 686 686 + "MSRIndex": "0x1a6,0x1a7", 687 687 + "MSRValue": "0x4003C0020", 688 688 + "SampleAfterValue": "100003", 689 689 + "UMask": "0x1" 690 690 + }, 691 691 + { 692 692 + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", 693 693 + "EventCode": "0xB7, 0xBB", 694 694 + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", 695 695 + "MSRIndex": "0x1a6,0x1a7", 696 696 + "MSRValue": "0x2003C0020", 697 697 + "SampleAfterValue": "100003", 698 698 + "UMask": "0x1" 699 699 + }, 700 700 + { 701 701 + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", 702 702 + "EventCode": "0xB7, 0xBB", 703 703 + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", 704 704 + "MSRIndex": "0x1a6,0x1a7", 705 705 + "MSRValue": "0x1003C0020", 706 706 + "SampleAfterValue": "100003", 707 707 + "UMask": "0x1" 708 708 + }, 709 709 + { 710 710 + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", 711 711 + "EventCode": "0xB7, 0xBB", 712 712 + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", 713 713 + "MSRIndex": "0x1a6,0x1a7", 714 714 + "MSRValue": "0x1E003C0020", 715 715 + "SampleAfterValue": "100003", 716 716 + "UMask": "0x1" 717 717 + }, 718 718 + { 719 719 + "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.", 720 720 + "EventCode": "0xB7, 0xBB", 721 721 + "EventName": "OCR.HWPF_L3.L3_HIT.ANY", 722 722 + "MSRIndex": "0x1a6,0x1a7", 723 723 + "MSRValue": "0x3FC03C2380", 724 724 + "SampleAfterValue": "100003", 725 725 + "UMask": "0x1" 726 726 + }, 727 727 + { 728 728 + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", 729 729 + "EventCode": "0xB7, 0xBB", 730 730 + "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", 731 731 + "MSRIndex": "0x1a6,0x1a7", 732 732 + "MSRValue": "0x4003C8000", 733 733 + "SampleAfterValue": "100003", 734 734 + "UMask": "0x1" 735 735 + }, 736 736 + { 737 737 + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", 738 738 + "EventCode": "0xB7, 0xBB", 739 739 + "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", 740 740 + "MSRIndex": "0x1a6,0x1a7", 741 741 + "MSRValue": "0x2003C8000", 742 742 + "SampleAfterValue": "100003", 743 743 + "UMask": "0x1" 744 744 + }, 745 745 + { 746 746 + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", 747 747 + "EventCode": "0xB7, 0xBB", 748 748 + "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", 749 749 + "MSRIndex": "0x1a6,0x1a7", 750 750 + "MSRValue": "0x1003C8000", 751 751 + "SampleAfterValue": "100003", 752 752 + "UMask": "0x1" 753 753 + }, 754 754 + { 755 755 + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.", 756 756 + "EventCode": "0xB7, 0xBB", 757 757 + "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", 758 758 + "MSRIndex": "0x1a6,0x1a7", 759 759 + "MSRValue": "0x1E003C8000", 760 760 + "SampleAfterValue": "100003", 761 761 + "UMask": "0x1" 762 762 + }, 763 763 + { 764 764 + "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.", 765 765 + "EventCode": "0xB7, 0xBB", 766 766 + "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", 767 767 + "MSRIndex": "0x1a6,0x1a7", 768 768 + "MSRValue": "0x3FC03C0800", 769 769 + "SampleAfterValue": "100003", 770 770 + "UMask": "0x1" 771 771 + }, 772 772 + { 773 773 + "BriefDescription": "Demand and prefetch data reads", 774 774 + "EventCode": "0xB0", 775 775 + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", 776 776 + "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", 777 777 + "SampleAfterValue": "100003", 778 778 + "UMask": "0x8" 779 779 + }, 780 780 + { 781 781 + "BriefDescription": "Counts memory transactions sent to the uncore.", 782 782 + "EventCode": "0xB0", 783 783 + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", 784 784 + "PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.", 785 785 + "SampleAfterValue": "100003", 786 786 + "UMask": "0x80" 787 787 + }, 788 788 + { 789 789 + "BriefDescription": "Demand Data Read requests sent to uncore", 790 790 + "EventCode": "0xb0", 791 791 + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", 792 792 + "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", 793 793 + "SampleAfterValue": "100003", 794 794 + "UMask": "0x1" 795 795 + }, 796 796 + { 797 797 + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", 798 798 + "EventCode": "0xb0", 799 799 + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", 800 800 + "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", 801 801 + "SampleAfterValue": "100003", 802 802 + "UMask": "0x4" 803 803 + }, 804 804 + { 805 805 + "BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.", 806 806 + "EventCode": "0x60", 807 807 + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 808 808 + "PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", 809 809 + "SampleAfterValue": "1000003", 810 810 + "UMask": "0x8" 811 811 + }, 812 812 + { 813 813 + "BriefDescription": "Cycles where at least 1 outstanding data read request is pending.", 814 814 + "CounterMask": "1", 815 815 + "EventCode": "0x60", 816 816 + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 817 817 + "PublicDescription": "Cycles where at least 1 outstanding data read request is pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", 818 818 + "SampleAfterValue": "1000003", 819 819 + "UMask": "0x8" 820 820 + }, 821 821 + { 822 822 + "BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.", 823 823 + "CounterMask": "1", 824 824 + "EventCode": "0x60", 825 825 + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", 826 826 + "PublicDescription": "Cycles where at least 1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", 827 827 + "SampleAfterValue": "1000003", 828 828 + "UMask": "0x4" 829 829 + }, 830 830 + { 831 831 + "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.", 832 832 + "EventCode": "0x60", 833 833 + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 834 834 + "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", 835 835 + "SampleAfterValue": "1000003", 836 836 + "UMask": "0x1" 837 837 + }, 838 838 + { 839 839 + "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.", 840 840 + "EventCode": "0x60", 841 841 + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 842 842 + "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.", 843 843 + "SampleAfterValue": "1000003", 844 844 + "UMask": "0x4" 845 845 + }, 846 846 + { 847 847 + "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.", 848 848 + "EventCode": "0xF4", 849 849 + "EventName": "SQ_MISC.BUS_LOCK", 850 850 + "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.", 851 851 + "SampleAfterValue": "100003", 852 852 + "UMask": "0x10" 853 853 + }, 854 854 + { 855 855 + "BriefDescription": "Cycles the queue waiting for offcore responses is full.", 856 856 + "EventCode": "0xf4", 857 857 + "EventName": "SQ_MISC.SQ_FULL", 858 858 + "PublicDescription": "Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries.", 859 859 + "SampleAfterValue": "100003", 860 860 + "UMask": "0x4" 861 861 + }, 862 862 + { 863 863 + "BriefDescription": "Number of PREFETCHNTA instructions executed.", 864 864 + "EventCode": "0x32", 865 865 + "EventName": "SW_PREFETCH_ACCESS.NTA", 866 866 + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", 867 867 + "SampleAfterValue": "100003", 868 868 + "UMask": "0x1" 869 869 + }, 870 870 + { 871 871 + "BriefDescription": "Number of PREFETCHW instructions executed.", 872 872 + "EventCode": "0x32", 873 873 + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", 874 874 + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", 875 875 + "SampleAfterValue": "100003", 876 876 + "UMask": "0x8" 877 877 + }, 878 878 + { 879 879 + "BriefDescription": "Number of PREFETCHT0 instructions executed.", 880 880 + "EventCode": "0x32", 881 881 + "EventName": "SW_PREFETCH_ACCESS.T0", 882 882 + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", 883 883 + "SampleAfterValue": "100003", 884 884 + "UMask": "0x2" 885 885 + }, 886 886 + { 887 887 + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", 888 888 + "EventCode": "0x32", 889 889 + "EventName": "SW_PREFETCH_ACCESS.T1_T2", 890 890 + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", 891 891 + "SampleAfterValue": "100003", 892 892 + "UMask": "0x4" 893 893 + } 894 894 + ]

+105

tools/perf/pmu-events/arch/x86/rocketlake/floating-point.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "Counts all microcode FP assists.", 4 4 + "EventCode": "0xc1", 5 5 + "EventName": "ASSISTS.FP", 6 6 + "PublicDescription": "Counts all microcode Floating Point assists.", 7 7 + "SampleAfterValue": "100003", 8 8 + "UMask": "0x2" 9 9 + }, 10 10 + { 11 11 + "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 12 12 + "EventCode": "0xc7", 13 13 + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 14 14 + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 15 15 + "SampleAfterValue": "100003", 16 16 + "UMask": "0x4" 17 17 + }, 18 18 + { 19 19 + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 20 20 + "EventCode": "0xc7", 21 21 + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 22 22 + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 23 23 + "SampleAfterValue": "100003", 24 24 + "UMask": "0x8" 25 25 + }, 26 26 + { 27 27 + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 28 28 + "EventCode": "0xc7", 29 29 + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 30 30 + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 31 31 + "SampleAfterValue": "100003", 32 32 + "UMask": "0x10" 33 33 + }, 34 34 + { 35 35 + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 36 36 + "EventCode": "0xc7", 37 37 + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 38 38 + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 39 39 + "SampleAfterValue": "100003", 40 40 + "UMask": "0x20" 41 41 + }, 42 42 + { 43 43 + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 44 44 + "EventCode": "0xc7", 45 45 + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 46 46 + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 47 47 + "SampleAfterValue": "100003", 48 48 + "UMask": "0x18" 49 49 + }, 50 50 + { 51 51 + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 52 52 + "EventCode": "0xc7", 53 53 + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", 54 54 + "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 55 55 + "SampleAfterValue": "100003", 56 56 + "UMask": "0x40" 57 57 + }, 58 58 + { 59 59 + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 60 60 + "EventCode": "0xc7", 61 61 + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", 62 62 + "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 63 63 + "SampleAfterValue": "100003", 64 64 + "UMask": "0x80" 65 65 + }, 66 66 + { 67 67 + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 68 68 + "EventCode": "0xc7", 69 69 + "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", 70 70 + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 71 71 + "SampleAfterValue": "100003", 72 72 + "UMask": "0x60" 73 73 + }, 74 74 + { 75 75 + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 76 76 + "EventCode": "0xc7", 77 77 + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 78 78 + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 79 79 + "SampleAfterValue": "1000003", 80 80 + "UMask": "0x3" 81 81 + }, 82 82 + { 83 83 + "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 84 84 + "EventCode": "0xc7", 85 85 + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 86 86 + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 87 87 + "SampleAfterValue": "100003", 88 88 + "UMask": "0x1" 89 89 + }, 90 90 + { 91 91 + "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 92 92 + "EventCode": "0xc7", 93 93 + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 94 94 + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 95 95 + "SampleAfterValue": "100003", 96 96 + "UMask": "0x2" 97 97 + }, 98 98 + { 99 99 + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 100 100 + "EventCode": "0xc7", 101 101 + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 102 102 + "SampleAfterValue": "1000003", 103 103 + "UMask": "0xfc" 104 104 + } 105 105 + ]

+377

tools/perf/pmu-events/arch/x86/rocketlake/frontend.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", 4 4 + "EventCode": "0xe6", 5 5 + "EventName": "BACLEARS.ANY", 6 6 + "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", 7 7 + "SampleAfterValue": "100003", 8 8 + "UMask": "0x1" 9 9 + }, 10 10 + { 11 11 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]", 12 12 + "EventCode": "0x87", 13 13 + "EventName": "DECODE.LCP", 14 14 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]", 15 15 + "SampleAfterValue": "500009", 16 16 + "UMask": "0x1" 17 17 + }, 18 18 + { 19 19 + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 20 20 + "CounterMask": "1", 21 21 + "EdgeDetect": "1", 22 22 + "EventCode": "0xab", 23 23 + "EventName": "DSB2MITE_SWITCHES.COUNT", 24 24 + "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", 25 25 + "SampleAfterValue": "100003", 26 26 + "UMask": "0x2" 27 27 + }, 28 28 + { 29 29 + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 30 30 + "EventCode": "0xab", 31 31 + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", 32 32 + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", 33 33 + "SampleAfterValue": "100003", 34 34 + "UMask": "0x2" 35 35 + }, 36 36 + { 37 37 + "BriefDescription": "Retired Instructions who experienced DSB miss.", 38 38 + "EventCode": "0xc6", 39 39 + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", 40 40 + "MSRIndex": "0x3F7", 41 41 + "MSRValue": "0x1", 42 42 + "PEBS": "1", 43 43 + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", 44 44 + "SampleAfterValue": "100007", 45 45 + "UMask": "0x1" 46 46 + }, 47 47 + { 48 48 + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", 49 49 + "EventCode": "0xc6", 50 50 + "EventName": "FRONTEND_RETIRED.DSB_MISS", 51 51 + "MSRIndex": "0x3F7", 52 52 + "MSRValue": "0x11", 53 53 + "PEBS": "1", 54 54 + "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", 55 55 + "SampleAfterValue": "100007", 56 56 + "UMask": "0x1" 57 57 + }, 58 58 + { 59 59 + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", 60 60 + "EventCode": "0xc6", 61 61 + "EventName": "FRONTEND_RETIRED.ITLB_MISS", 62 62 + "MSRIndex": "0x3F7", 63 63 + "MSRValue": "0x14", 64 64 + "PEBS": "1", 65 65 + "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", 66 66 + "SampleAfterValue": "100007", 67 67 + "UMask": "0x1" 68 68 + }, 69 69 + { 70 70 + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", 71 71 + "EventCode": "0xc6", 72 72 + "EventName": "FRONTEND_RETIRED.L1I_MISS", 73 73 + "MSRIndex": "0x3F7", 74 74 + "MSRValue": "0x12", 75 75 + "PEBS": "1", 76 76 + "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", 77 77 + "SampleAfterValue": "100007", 78 78 + "UMask": "0x1" 79 79 + }, 80 80 + { 81 81 + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", 82 82 + "EventCode": "0xc6", 83 83 + "EventName": "FRONTEND_RETIRED.L2_MISS", 84 84 + "MSRIndex": "0x3F7", 85 85 + "MSRValue": "0x13", 86 86 + "PEBS": "1", 87 87 + "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", 88 88 + "SampleAfterValue": "100007", 89 89 + "UMask": "0x1" 90 90 + }, 91 91 + { 92 92 + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", 93 93 + "EventCode": "0xc6", 94 94 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", 95 95 + "MSRIndex": "0x3F7", 96 96 + "MSRValue": "0x500106", 97 97 + "PEBS": "1", 98 98 + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", 99 99 + "SampleAfterValue": "100007", 100 100 + "UMask": "0x1" 101 101 + }, 102 102 + { 103 103 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", 104 104 + "EventCode": "0xc6", 105 105 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", 106 106 + "MSRIndex": "0x3F7", 107 107 + "MSRValue": "0x508006", 108 108 + "PEBS": "1", 109 109 + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", 110 110 + "SampleAfterValue": "100007", 111 111 + "UMask": "0x1" 112 112 + }, 113 113 + { 114 114 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", 115 115 + "EventCode": "0xc6", 116 116 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", 117 117 + "MSRIndex": "0x3F7", 118 118 + "MSRValue": "0x501006", 119 119 + "PEBS": "1", 120 120 + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", 121 121 + "SampleAfterValue": "100007", 122 122 + "UMask": "0x1" 123 123 + }, 124 124 + { 125 125 + "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", 126 126 + "EventCode": "0xc6", 127 127 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", 128 128 + "MSRIndex": "0x3F7", 129 129 + "MSRValue": "0x500206", 130 130 + "PEBS": "1", 131 131 + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", 132 132 + "SampleAfterValue": "100007", 133 133 + "UMask": "0x1" 134 134 + }, 135 135 + { 136 136 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", 137 137 + "EventCode": "0xc6", 138 138 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", 139 139 + "MSRIndex": "0x3F7", 140 140 + "MSRValue": "0x510006", 141 141 + "PEBS": "1", 142 142 + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", 143 143 + "SampleAfterValue": "100007", 144 144 + "UMask": "0x1" 145 145 + }, 146 146 + { 147 147 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", 148 148 + "EventCode": "0xc6", 149 149 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", 150 150 + "MSRIndex": "0x3F7", 151 151 + "MSRValue": "0x100206", 152 152 + "PEBS": "1", 153 153 + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", 154 154 + "SampleAfterValue": "100007", 155 155 + "UMask": "0x1" 156 156 + }, 157 157 + { 158 158 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", 159 159 + "EventCode": "0xc6", 160 160 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", 161 161 + "MSRIndex": "0x3F7", 162 162 + "MSRValue": "0x502006", 163 163 + "PEBS": "1", 164 164 + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", 165 165 + "SampleAfterValue": "100007", 166 166 + "UMask": "0x1" 167 167 + }, 168 168 + { 169 169 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", 170 170 + "EventCode": "0xc6", 171 171 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", 172 172 + "MSRIndex": "0x3F7", 173 173 + "MSRValue": "0x500406", 174 174 + "PEBS": "1", 175 175 + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", 176 176 + "SampleAfterValue": "100007", 177 177 + "UMask": "0x1" 178 178 + }, 179 179 + { 180 180 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", 181 181 + "EventCode": "0xc6", 182 182 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", 183 183 + "MSRIndex": "0x3F7", 184 184 + "MSRValue": "0x520006", 185 185 + "PEBS": "1", 186 186 + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", 187 187 + "SampleAfterValue": "100007", 188 188 + "UMask": "0x1" 189 189 + }, 190 190 + { 191 191 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", 192 192 + "EventCode": "0xc6", 193 193 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", 194 194 + "MSRIndex": "0x3F7", 195 195 + "MSRValue": "0x504006", 196 196 + "PEBS": "1", 197 197 + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", 198 198 + "SampleAfterValue": "100007", 199 199 + "UMask": "0x1" 200 200 + }, 201 201 + { 202 202 + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", 203 203 + "EventCode": "0xc6", 204 204 + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", 205 205 + "MSRIndex": "0x3F7", 206 206 + "MSRValue": "0x500806", 207 207 + "PEBS": "1", 208 208 + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", 209 209 + "SampleAfterValue": "100007", 210 210 + "UMask": "0x1" 211 211 + }, 212 212 + { 213 213 + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", 214 214 + "EventCode": "0xc6", 215 215 + "EventName": "FRONTEND_RETIRED.STLB_MISS", 216 216 + "MSRIndex": "0x3F7", 217 217 + "MSRValue": "0x15", 218 218 + "PEBS": "1", 219 219 + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", 220 220 + "SampleAfterValue": "100007", 221 221 + "UMask": "0x1" 222 222 + }, 223 223 + { 224 224 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]", 225 225 + "EventCode": "0x80", 226 226 + "EventName": "ICACHE_16B.IFDATA_STALL", 227 227 + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]", 228 228 + "SampleAfterValue": "500009", 229 229 + "UMask": "0x4" 230 230 + }, 231 231 + { 232 232 + "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", 233 233 + "EventCode": "0x83", 234 234 + "EventName": "ICACHE_64B.IFTAG_HIT", 235 235 + "PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", 236 236 + "SampleAfterValue": "200003", 237 237 + "UMask": "0x1" 238 238 + }, 239 239 + { 240 240 + "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", 241 241 + "EventCode": "0x83", 242 242 + "EventName": "ICACHE_64B.IFTAG_MISS", 243 243 + "PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", 244 244 + "SampleAfterValue": "200003", 245 245 + "UMask": "0x2" 246 246 + }, 247 247 + { 248 248 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", 249 249 + "EventCode": "0x83", 250 250 + "EventName": "ICACHE_64B.IFTAG_STALL", 251 251 + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", 252 252 + "SampleAfterValue": "200003", 253 253 + "UMask": "0x4" 254 254 + }, 255 255 + { 256 256 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]", 257 257 + "EventCode": "0x80", 258 258 + "EventName": "ICACHE_DATA.STALLS", 259 259 + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]", 260 260 + "SampleAfterValue": "500009", 261 261 + "UMask": "0x4" 262 262 + }, 263 263 + { 264 264 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", 265 265 + "EventCode": "0x83", 266 266 + "EventName": "ICACHE_TAG.STALLS", 267 267 + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", 268 268 + "SampleAfterValue": "200003", 269 269 + "UMask": "0x4" 270 270 + }, 271 271 + { 272 272 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 273 273 + "CounterMask": "1", 274 274 + "EventCode": "0x79", 275 275 + "EventName": "IDQ.DSB_CYCLES_ANY", 276 276 + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", 277 277 + "SampleAfterValue": "2000003", 278 278 + "UMask": "0x8" 279 279 + }, 280 280 + { 281 281 + "BriefDescription": "Cycles DSB is delivering optimal number of Uops", 282 282 + "CounterMask": "5", 283 283 + "EventCode": "0x79", 284 284 + "EventName": "IDQ.DSB_CYCLES_OK", 285 285 + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", 286 286 + "SampleAfterValue": "2000003", 287 287 + "UMask": "0x8" 288 288 + }, 289 289 + { 290 290 + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", 291 291 + "EventCode": "0x79", 292 292 + "EventName": "IDQ.DSB_UOPS", 293 293 + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", 294 294 + "SampleAfterValue": "2000003", 295 295 + "UMask": "0x8" 296 296 + }, 297 297 + { 298 298 + "BriefDescription": "Cycles MITE is delivering any Uop", 299 299 + "CounterMask": "1", 300 300 + "EventCode": "0x79", 301 301 + "EventName": "IDQ.MITE_CYCLES_ANY", 302 302 + "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", 303 303 + "SampleAfterValue": "2000003", 304 304 + "UMask": "0x4" 305 305 + }, 306 306 + { 307 307 + "BriefDescription": "Cycles MITE is delivering optimal number of Uops", 308 308 + "CounterMask": "5", 309 309 + "EventCode": "0x79", 310 310 + "EventName": "IDQ.MITE_CYCLES_OK", 311 311 + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", 312 312 + "SampleAfterValue": "2000003", 313 313 + "UMask": "0x4" 314 314 + }, 315 315 + { 316 316 + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", 317 317 + "EventCode": "0x79", 318 318 + "EventName": "IDQ.MITE_UOPS", 319 319 + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", 320 320 + "SampleAfterValue": "2000003", 321 321 + "UMask": "0x4" 322 322 + }, 323 323 + { 324 324 + "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", 325 325 + "CounterMask": "1", 326 326 + "EventCode": "0x79", 327 327 + "EventName": "IDQ.MS_CYCLES_ANY", 328 328 + "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", 329 329 + "SampleAfterValue": "2000003", 330 330 + "UMask": "0x30" 331 331 + }, 332 332 + { 333 333 + "BriefDescription": "Number of switches from DSB or MITE to the MS", 334 334 + "CounterMask": "1", 335 335 + "EdgeDetect": "1", 336 336 + "EventCode": "0x79", 337 337 + "EventName": "IDQ.MS_SWITCHES", 338 338 + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", 339 339 + "SampleAfterValue": "100003", 340 340 + "UMask": "0x30" 341 341 + }, 342 342 + { 343 343 + "BriefDescription": "Uops delivered to IDQ while MS is busy", 344 344 + "EventCode": "0x79", 345 345 + "EventName": "IDQ.MS_UOPS", 346 346 + "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", 347 347 + "SampleAfterValue": "100003", 348 348 + "UMask": "0x30" 349 349 + }, 350 350 + { 351 351 + "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled", 352 352 + "EventCode": "0x9c", 353 353 + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", 354 354 + "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", 355 355 + "SampleAfterValue": "1000003", 356 356 + "UMask": "0x1" 357 357 + }, 358 358 + { 359 359 + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled", 360 360 + "CounterMask": "5", 361 361 + "EventCode": "0x9c", 362 362 + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", 363 363 + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", 364 364 + "SampleAfterValue": "1000003", 365 365 + "UMask": "0x1" 366 366 + }, 367 367 + { 368 368 + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", 369 369 + "CounterMask": "1", 370 370 + "EventCode": "0x9C", 371 371 + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", 372 372 + "Invert": "1", 373 373 + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", 374 374 + "SampleAfterValue": "1000003", 375 375 + "UMask": "0x1" 376 376 + } 377 377 + ]

+394

tools/perf/pmu-events/arch/x86/rocketlake/memory.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", 4 4 + "CounterMask": "2", 5 5 + "EventCode": "0xA3", 6 6 + "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", 7 7 + "SampleAfterValue": "1000003", 8 8 + "UMask": "0x2" 9 9 + }, 10 10 + { 11 11 + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", 12 12 + "CounterMask": "6", 13 13 + "EventCode": "0xa3", 14 14 + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", 15 15 + "SampleAfterValue": "1000003", 16 16 + "UMask": "0x6" 17 17 + }, 18 18 + { 19 19 + "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", 20 20 + "EventCode": "0xc8", 21 21 + "EventName": "HLE_RETIRED.ABORTED", 22 22 + "PublicDescription": "Counts the number of times HLE abort was triggered.", 23 23 + "SampleAfterValue": "100003", 24 24 + "UMask": "0x4" 25 25 + }, 26 26 + { 27 27 + "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 28 28 + "EventCode": "0xc8", 29 29 + "EventName": "HLE_RETIRED.ABORTED_EVENTS", 30 30 + "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).", 31 31 + "SampleAfterValue": "100003", 32 32 + "UMask": "0x80" 33 33 + }, 34 34 + { 35 35 + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 36 36 + "EventCode": "0xc8", 37 37 + "EventName": "HLE_RETIRED.ABORTED_MEM", 38 38 + "PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 39 39 + "SampleAfterValue": "100003", 40 40 + "UMask": "0x8" 41 41 + }, 42 42 + { 43 43 + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 44 44 + "EventCode": "0xc8", 45 45 + "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", 46 46 + "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", 47 47 + "SampleAfterValue": "100003", 48 48 + "UMask": "0x20" 49 49 + }, 50 50 + { 51 51 + "BriefDescription": "Number of times an HLE execution successfully committed", 52 52 + "EventCode": "0xc8", 53 53 + "EventName": "HLE_RETIRED.COMMIT", 54 54 + "PublicDescription": "Counts the number of times HLE commit succeeded.", 55 55 + "SampleAfterValue": "100003", 56 56 + "UMask": "0x2" 57 57 + }, 58 58 + { 59 59 + "BriefDescription": "Number of times an HLE execution started.", 60 60 + "EventCode": "0xc8", 61 61 + "EventName": "HLE_RETIRED.START", 62 62 + "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.", 63 63 + "SampleAfterValue": "100003", 64 64 + "UMask": "0x1" 65 65 + }, 66 66 + { 67 67 + "BriefDescription": "Number of machine clears due to memory ordering conflicts.", 68 68 + "EventCode": "0xc3", 69 69 + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", 70 70 + "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", 71 71 + "SampleAfterValue": "100003", 72 72 + "UMask": "0x2" 73 73 + }, 74 74 + { 75 75 + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", 76 76 + "Data_LA": "1", 77 77 + "EventCode": "0xcd", 78 78 + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", 79 79 + "MSRIndex": "0x3F6", 80 80 + "MSRValue": "0x80", 81 81 + "PEBS": "2", 82 82 + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", 83 83 + "SampleAfterValue": "1009", 84 84 + "UMask": "0x1" 85 85 + }, 86 86 + { 87 87 + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", 88 88 + "Data_LA": "1", 89 89 + "EventCode": "0xcd", 90 90 + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", 91 91 + "MSRIndex": "0x3F6", 92 92 + "MSRValue": "0x10", 93 93 + "PEBS": "2", 94 94 + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", 95 95 + "SampleAfterValue": "20011", 96 96 + "UMask": "0x1" 97 97 + }, 98 98 + { 99 99 + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", 100 100 + "Data_LA": "1", 101 101 + "EventCode": "0xcd", 102 102 + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", 103 103 + "MSRIndex": "0x3F6", 104 104 + "MSRValue": "0x100", 105 105 + "PEBS": "2", 106 106 + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", 107 107 + "SampleAfterValue": "503", 108 108 + "UMask": "0x1" 109 109 + }, 110 110 + { 111 111 + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", 112 112 + "Data_LA": "1", 113 113 + "EventCode": "0xcd", 114 114 + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", 115 115 + "MSRIndex": "0x3F6", 116 116 + "MSRValue": "0x20", 117 117 + "PEBS": "2", 118 118 + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", 119 119 + "SampleAfterValue": "100007", 120 120 + "UMask": "0x1" 121 121 + }, 122 122 + { 123 123 + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", 124 124 + "Data_LA": "1", 125 125 + "EventCode": "0xcd", 126 126 + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", 127 127 + "MSRIndex": "0x3F6", 128 128 + "MSRValue": "0x4", 129 129 + "PEBS": "2", 130 130 + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", 131 131 + "SampleAfterValue": "100003", 132 132 + "UMask": "0x1" 133 133 + }, 134 134 + { 135 135 + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", 136 136 + "Data_LA": "1", 137 137 + "EventCode": "0xcd", 138 138 + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", 139 139 + "MSRIndex": "0x3F6", 140 140 + "MSRValue": "0x200", 141 141 + "PEBS": "2", 142 142 + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", 143 143 + "SampleAfterValue": "101", 144 144 + "UMask": "0x1" 145 145 + }, 146 146 + { 147 147 + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", 148 148 + "Data_LA": "1", 149 149 + "EventCode": "0xcd", 150 150 + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", 151 151 + "MSRIndex": "0x3F6", 152 152 + "MSRValue": "0x40", 153 153 + "PEBS": "2", 154 154 + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", 155 155 + "SampleAfterValue": "2003", 156 156 + "UMask": "0x1" 157 157 + }, 158 158 + { 159 159 + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", 160 160 + "Data_LA": "1", 161 161 + "EventCode": "0xcd", 162 162 + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", 163 163 + "MSRIndex": "0x3F6", 164 164 + "MSRValue": "0x8", 165 165 + "PEBS": "2", 166 166 + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", 167 167 + "SampleAfterValue": "50021", 168 168 + "UMask": "0x1" 169 169 + }, 170 170 + { 171 171 + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.", 172 172 + "EventCode": "0xB7, 0xBB", 173 173 + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", 174 174 + "MSRIndex": "0x1a6,0x1a7", 175 175 + "MSRValue": "0x3FFFC00004", 176 176 + "SampleAfterValue": "100003", 177 177 + "UMask": "0x1" 178 178 + }, 179 179 + { 180 180 + "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.", 181 181 + "EventCode": "0xB7, 0xBB", 182 182 + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", 183 183 + "MSRIndex": "0x1a6,0x1a7", 184 184 + "MSRValue": "0x3FFFC00001", 185 185 + "SampleAfterValue": "100003", 186 186 + "UMask": "0x1" 187 187 + }, 188 188 + { 189 189 + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.", 190 190 + "EventCode": "0xB7, 0xBB", 191 191 + "EventName": "OCR.DEMAND_RFO.L3_MISS", 192 192 + "MSRIndex": "0x1a6,0x1a7", 193 193 + "MSRValue": "0x3FFFC00002", 194 194 + "SampleAfterValue": "100003", 195 195 + "UMask": "0x1" 196 196 + }, 197 197 + { 198 198 + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.", 199 199 + "EventCode": "0xB7, 0xBB", 200 200 + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", 201 201 + "MSRIndex": "0x1a6,0x1a7", 202 202 + "MSRValue": "0x3FFFC00400", 203 203 + "SampleAfterValue": "100003", 204 204 + "UMask": "0x1" 205 205 + }, 206 206 + { 207 207 + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache.", 208 208 + "EventCode": "0xB7, 0xBB", 209 209 + "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", 210 210 + "MSRIndex": "0x1a6,0x1a7", 211 211 + "MSRValue": "0x3FFFC00010", 212 212 + "SampleAfterValue": "100003", 213 213 + "UMask": "0x1" 214 214 + }, 215 215 + { 216 216 + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache.", 217 217 + "EventCode": "0xB7, 0xBB", 218 218 + "EventName": "OCR.HWPF_L2_RFO.L3_MISS", 219 219 + "MSRIndex": "0x1a6,0x1a7", 220 220 + "MSRValue": "0x3FFFC00020", 221 221 + "SampleAfterValue": "100003", 222 222 + "UMask": "0x1" 223 223 + }, 224 224 + { 225 225 + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.", 226 226 + "EventCode": "0xB7, 0xBB", 227 227 + "EventName": "OCR.OTHER.L3_MISS", 228 228 + "MSRIndex": "0x1a6,0x1a7", 229 229 + "MSRValue": "0x3FFFC08000", 230 230 + "SampleAfterValue": "100003", 231 231 + "UMask": "0x1" 232 232 + }, 233 233 + { 234 234 + "BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.", 235 235 + "EventCode": "0xB7, 0xBB", 236 236 + "EventName": "OCR.STREAMING_WR.L3_MISS", 237 237 + "MSRIndex": "0x1a6,0x1a7", 238 238 + "MSRValue": "0x3FFFC00800", 239 239 + "SampleAfterValue": "100003", 240 240 + "UMask": "0x1" 241 241 + }, 242 242 + { 243 243 + "BriefDescription": "Counts demand data read requests that miss the L3 cache.", 244 244 + "EventCode": "0xb0", 245 245 + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 246 246 + "SampleAfterValue": "100003", 247 247 + "UMask": "0x10" 248 248 + }, 249 249 + { 250 250 + "BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.", 251 251 + "CounterMask": "1", 252 252 + "EventCode": "0x60", 253 253 + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", 254 254 + "PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", 255 255 + "SampleAfterValue": "1000003", 256 256 + "UMask": "0x10" 257 257 + }, 258 258 + { 259 259 + "BriefDescription": "Number of times an RTM execution aborted.", 260 260 + "EventCode": "0xc9", 261 261 + "EventName": "RTM_RETIRED.ABORTED", 262 262 + "PublicDescription": "Counts the number of times RTM abort was triggered.", 263 263 + "SampleAfterValue": "100003", 264 264 + "UMask": "0x4" 265 265 + }, 266 266 + { 267 267 + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", 268 268 + "EventCode": "0xc9", 269 269 + "EventName": "RTM_RETIRED.ABORTED_EVENTS", 270 270 + "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", 271 271 + "SampleAfterValue": "100003", 272 272 + "UMask": "0x80" 273 273 + }, 274 274 + { 275 275 + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 276 276 + "EventCode": "0xc9", 277 277 + "EventName": "RTM_RETIRED.ABORTED_MEM", 278 278 + "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 279 279 + "SampleAfterValue": "100003", 280 280 + "UMask": "0x8" 281 281 + }, 282 282 + { 283 283 + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", 284 284 + "EventCode": "0xc9", 285 285 + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", 286 286 + "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", 287 287 + "SampleAfterValue": "100003", 288 288 + "UMask": "0x40" 289 289 + }, 290 290 + { 291 291 + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", 292 292 + "EventCode": "0xc9", 293 293 + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", 294 294 + "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", 295 295 + "SampleAfterValue": "100003", 296 296 + "UMask": "0x20" 297 297 + }, 298 298 + { 299 299 + "BriefDescription": "Number of times an RTM execution successfully committed", 300 300 + "EventCode": "0xc9", 301 301 + "EventName": "RTM_RETIRED.COMMIT", 302 302 + "PublicDescription": "Counts the number of times RTM commit succeeded.", 303 303 + "SampleAfterValue": "100003", 304 304 + "UMask": "0x2" 305 305 + }, 306 306 + { 307 307 + "BriefDescription": "Number of times an RTM execution started.", 308 308 + "EventCode": "0xc9", 309 309 + "EventName": "RTM_RETIRED.START", 310 310 + "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", 311 311 + "SampleAfterValue": "100003", 312 312 + "UMask": "0x1" 313 313 + }, 314 314 + { 315 315 + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", 316 316 + "EventCode": "0x5d", 317 317 + "EventName": "TX_EXEC.MISC2", 318 318 + "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", 319 319 + "SampleAfterValue": "100003", 320 320 + "UMask": "0x2" 321 321 + }, 322 322 + { 323 323 + "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", 324 324 + "EventCode": "0x5d", 325 325 + "EventName": "TX_EXEC.MISC3", 326 326 + "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", 327 327 + "SampleAfterValue": "100003", 328 328 + "UMask": "0x4" 329 329 + }, 330 330 + { 331 331 + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", 332 332 + "EventCode": "0x54", 333 333 + "EventName": "TX_MEM.ABORT_CAPACITY_READ", 334 334 + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", 335 335 + "SampleAfterValue": "100003", 336 336 + "UMask": "0x80" 337 337 + }, 338 338 + { 339 339 + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", 340 340 + "EventCode": "0x54", 341 341 + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", 342 342 + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", 343 343 + "SampleAfterValue": "100003", 344 344 + "UMask": "0x2" 345 345 + }, 346 346 + { 347 347 + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", 348 348 + "EventCode": "0x54", 349 349 + "EventName": "TX_MEM.ABORT_CONFLICT", 350 350 + "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", 351 351 + "SampleAfterValue": "100003", 352 352 + "UMask": "0x1" 353 353 + }, 354 354 + { 355 355 + "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", 356 356 + "EventCode": "0x54", 357 357 + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", 358 358 + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 359 359 + "SampleAfterValue": "100003", 360 360 + "UMask": "0x10" 361 361 + }, 362 362 + { 363 363 + "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", 364 364 + "EventCode": "0x54", 365 365 + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", 366 366 + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", 367 367 + "SampleAfterValue": "100003", 368 368 + "UMask": "0x8" 369 369 + }, 370 370 + { 371 371 + "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", 372 372 + "EventCode": "0x54", 373 373 + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", 374 374 + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", 375 375 + "SampleAfterValue": "100003", 376 376 + "UMask": "0x20" 377 377 + }, 378 378 + { 379 379 + "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", 380 380 + "EventCode": "0x54", 381 381 + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", 382 382 + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/commit store to lock.", 383 383 + "SampleAfterValue": "100003", 384 384 + "UMask": "0x4" 385 385 + }, 386 386 + { 387 387 + "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", 388 388 + "EventCode": "0x54", 389 389 + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", 390 390 + "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.", 391 391 + "SampleAfterValue": "100003", 392 392 + "UMask": "0x40" 393 393 + } 394 394 + ]

+113

tools/perf/pmu-events/arch/x86/rocketlake/metricgroups.json

reviewed

··· 1 1 + { 2 2 + "Backend": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 3 3 + "Bad": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 4 4 + "BadSpec": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 5 5 + "BigFoot": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 6 6 + "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 7 7 + "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 8 8 + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 9 9 + "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 10 10 + "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 11 11 + "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 12 12 + "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 13 13 + "DSBmiss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 14 14 + "DataSharing": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 15 15 + "Fed": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 16 16 + "FetchBW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 17 17 + "FetchLat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 18 18 + "Flops": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 19 19 + "FpScalar": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 20 20 + "FpVector": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 21 21 + "Frontend": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 22 22 + "HPC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 23 23 + "IcMiss": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 24 24 + "InsType": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 25 25 + "L2Evicts": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 26 26 + "LSD": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 27 27 + "MachineClears": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 28 28 + "Mem": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 29 29 + "MemoryBW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 30 30 + "MemoryBound": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 31 31 + "MemoryLat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 32 32 + "MemoryTLB": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 33 33 + "Memory_BW": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 34 34 + "Memory_Lat": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 35 35 + "MicroSeq": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 36 36 + "OS": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 37 37 + "Offcore": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 38 38 + "PGO": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 39 39 + "Pipeline": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 40 40 + "PortsUtil": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 41 41 + "Power": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 42 42 + "Prefetches": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 43 43 + "Ret": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 44 44 + "Retire": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 45 45 + "SMT": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 46 46 + "Server": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 47 47 + "Snoop": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 48 48 + "SoC": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 49 49 + "Summary": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 50 50 + "TmaL1": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 51 51 + "TmaL2": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 52 52 + "TmaL3mem": "Grouping from Top-down Microarchitecture Analysis Metrics spreadsheet", 53 53 + "TopdownL1": "Metrics for top-down breakdown at level 1", 54 54 + "TopdownL2": "Metrics for top-down breakdown at level 2", 55 55 + "TopdownL3": "Metrics for top-down breakdown at level 3", 56 56 + "TopdownL4": "Metrics for top-down breakdown at level 4", 57 57 + "TopdownL5": "Metrics for top-down breakdown at level 5", 58 58 + "TopdownL6": "Metrics for top-down breakdown at level 6", 59 59 + "tma_L1_group": "Metrics for top-down breakdown at level 1", 60 60 + "tma_L2_group": "Metrics for top-down breakdown at level 2", 61 61 + "tma_L3_group": "Metrics for top-down breakdown at level 3", 62 62 + "tma_L4_group": "Metrics for top-down breakdown at level 4", 63 63 + "tma_L5_group": "Metrics for top-down breakdown at level 5", 64 64 + "tma_L6_group": "Metrics for top-down breakdown at level 6", 65 65 + "tma_alu_op_utilization_group": "Metrics contributing to tma_alu_op_utilization category", 66 66 + "tma_backend_bound_group": "Metrics contributing to tma_backend_bound category", 67 67 + "tma_bad_speculation_group": "Metrics contributing to tma_bad_speculation category", 68 68 + "tma_branch_resteers_group": "Metrics contributing to tma_branch_resteers category", 69 69 + "tma_core_bound_group": "Metrics contributing to tma_core_bound category", 70 70 + "tma_dram_bound_group": "Metrics contributing to tma_dram_bound category", 71 71 + "tma_dtlb_load_group": "Metrics contributing to tma_dtlb_load category", 72 72 + "tma_dtlb_store_group": "Metrics contributing to tma_dtlb_store category", 73 73 + "tma_fetch_bandwidth_group": "Metrics contributing to tma_fetch_bandwidth category", 74 74 + "tma_fetch_latency_group": "Metrics contributing to tma_fetch_latency category", 75 75 + "tma_fp_arith_group": "Metrics contributing to tma_fp_arith category", 76 76 + "tma_fp_vector_group": "Metrics contributing to tma_fp_vector category", 77 77 + "tma_frontend_bound_group": "Metrics contributing to tma_frontend_bound category", 78 78 + "tma_heavy_operations_group": "Metrics contributing to tma_heavy_operations category", 79 79 + "tma_issue2P": "Metrics related by the issue $issue2P", 80 80 + "tma_issueBC": "Metrics related by the issue $issueBC", 81 81 + "tma_issueBM": "Metrics related by the issue $issueBM", 82 82 + "tma_issueBW": "Metrics related by the issue $issueBW", 83 83 + "tma_issueD0": "Metrics related by the issue $issueD0", 84 84 + "tma_issueFB": "Metrics related by the issue $issueFB", 85 85 + "tma_issueFL": "Metrics related by the issue $issueFL", 86 86 + "tma_issueL1": "Metrics related by the issue $issueL1", 87 87 + "tma_issueLat": "Metrics related by the issue $issueLat", 88 88 + "tma_issueMC": "Metrics related by the issue $issueMC", 89 89 + "tma_issueMS": "Metrics related by the issue $issueMS", 90 90 + "tma_issueMV": "Metrics related by the issue $issueMV", 91 91 + "tma_issueRFO": "Metrics related by the issue $issueRFO", 92 92 + "tma_issueSL": "Metrics related by the issue $issueSL", 93 93 + "tma_issueSO": "Metrics related by the issue $issueSO", 94 94 + "tma_issueSmSt": "Metrics related by the issue $issueSmSt", 95 95 + "tma_issueSpSt": "Metrics related by the issue $issueSpSt", 96 96 + "tma_issueSyncxn": "Metrics related by the issue $issueSyncxn", 97 97 + "tma_issueTLB": "Metrics related by the issue $issueTLB", 98 98 + "tma_l1_bound_group": "Metrics contributing to tma_l1_bound category", 99 99 + "tma_l3_bound_group": "Metrics contributing to tma_l3_bound category", 100 100 + "tma_light_operations_group": "Metrics contributing to tma_light_operations category", 101 101 + "tma_load_op_utilization_group": "Metrics contributing to tma_load_op_utilization category", 102 102 + "tma_mem_latency_group": "Metrics contributing to tma_mem_latency category", 103 103 + "tma_memory_bound_group": "Metrics contributing to tma_memory_bound category", 104 104 + "tma_microcode_sequencer_group": "Metrics contributing to tma_microcode_sequencer category", 105 105 + "tma_mite_group": "Metrics contributing to tma_mite category", 106 106 + "tma_ports_utilization_group": "Metrics contributing to tma_ports_utilization category", 107 107 + "tma_ports_utilized_0_group": "Metrics contributing to tma_ports_utilized_0 category", 108 108 + "tma_ports_utilized_3m_group": "Metrics contributing to tma_ports_utilized_3m category", 109 109 + "tma_retiring_group": "Metrics contributing to tma_retiring category", 110 110 + "tma_serializing_operation_group": "Metrics contributing to tma_serializing_operation category", 111 111 + "tma_store_bound_group": "Metrics contributing to tma_store_bound category", 112 112 + "tma_store_op_utilization_group": "Metrics contributing to tma_store_op_utilization category" 113 113 + }

+242

tools/perf/pmu-events/arch/x86/rocketlake/other.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", 4 4 + "EventCode": "0x28", 5 5 + "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", 6 6 + "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", 7 7 + "SampleAfterValue": "200003", 8 8 + "UMask": "0x7" 9 9 + }, 10 10 + { 11 11 + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", 12 12 + "EventCode": "0x28", 13 13 + "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", 14 14 + "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", 15 15 + "SampleAfterValue": "200003", 16 16 + "UMask": "0x18" 17 17 + }, 18 18 + { 19 19 + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", 20 20 + "EventCode": "0x28", 21 21 + "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", 22 22 + "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", 23 23 + "SampleAfterValue": "200003", 24 24 + "UMask": "0x20" 25 25 + }, 26 26 + { 27 27 + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", 28 28 + "EventCode": "0xB7, 0xBB", 29 29 + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", 30 30 + "MSRIndex": "0x1a6,0x1a7", 31 31 + "MSRValue": "0x10004", 32 32 + "SampleAfterValue": "100003", 33 33 + "UMask": "0x1" 34 34 + }, 35 35 + { 36 36 + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", 37 37 + "EventCode": "0xB7, 0xBB", 38 38 + "EventName": "OCR.DEMAND_CODE_RD.DRAM", 39 39 + "MSRIndex": "0x1a6,0x1a7", 40 40 + "MSRValue": "0x184000004", 41 41 + "SampleAfterValue": "100003", 42 42 + "UMask": "0x1" 43 43 + }, 44 44 + { 45 45 + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", 46 46 + "EventCode": "0xB7, 0xBB", 47 47 + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", 48 48 + "MSRIndex": "0x1a6,0x1a7", 49 49 + "MSRValue": "0x184000004", 50 50 + "SampleAfterValue": "100003", 51 51 + "UMask": "0x1" 52 52 + }, 53 53 + { 54 54 + "BriefDescription": "Counts demand data reads that have any type of response.", 55 55 + "EventCode": "0xB7, 0xBB", 56 56 + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", 57 57 + "MSRIndex": "0x1a6,0x1a7", 58 58 + "MSRValue": "0x10001", 59 59 + "SampleAfterValue": "100003", 60 60 + "UMask": "0x1" 61 61 + }, 62 62 + { 63 63 + "BriefDescription": "Counts demand data reads that DRAM supplied the request.", 64 64 + "EventCode": "0xB7, 0xBB", 65 65 + "EventName": "OCR.DEMAND_DATA_RD.DRAM", 66 66 + "MSRIndex": "0x1a6,0x1a7", 67 67 + "MSRValue": "0x184000001", 68 68 + "SampleAfterValue": "100003", 69 69 + "UMask": "0x1" 70 70 + }, 71 71 + { 72 72 + "BriefDescription": "Counts demand data reads that DRAM supplied the request.", 73 73 + "EventCode": "0xB7, 0xBB", 74 74 + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", 75 75 + "MSRIndex": "0x1a6,0x1a7", 76 76 + "MSRValue": "0x184000001", 77 77 + "SampleAfterValue": "100003", 78 78 + "UMask": "0x1" 79 79 + }, 80 80 + { 81 81 + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", 82 82 + "EventCode": "0xB7, 0xBB", 83 83 + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", 84 84 + "MSRIndex": "0x1a6,0x1a7", 85 85 + "MSRValue": "0x10002", 86 86 + "SampleAfterValue": "100003", 87 87 + "UMask": "0x1" 88 88 + }, 89 89 + { 90 90 + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", 91 91 + "EventCode": "0xB7, 0xBB", 92 92 + "EventName": "OCR.DEMAND_RFO.DRAM", 93 93 + "MSRIndex": "0x1a6,0x1a7", 94 94 + "MSRValue": "0x184000002", 95 95 + "SampleAfterValue": "100003", 96 96 + "UMask": "0x1" 97 97 + }, 98 98 + { 99 99 + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", 100 100 + "EventCode": "0xB7, 0xBB", 101 101 + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", 102 102 + "MSRIndex": "0x1a6,0x1a7", 103 103 + "MSRValue": "0x184000002", 104 104 + "SampleAfterValue": "100003", 105 105 + "UMask": "0x1" 106 106 + }, 107 107 + { 108 108 + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", 109 109 + "EventCode": "0xB7, 0xBB", 110 110 + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", 111 111 + "MSRIndex": "0x1a6,0x1a7", 112 112 + "MSRValue": "0x10400", 113 113 + "SampleAfterValue": "100003", 114 114 + "UMask": "0x1" 115 115 + }, 116 116 + { 117 117 + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", 118 118 + "EventCode": "0xB7, 0xBB", 119 119 + "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", 120 120 + "MSRIndex": "0x1a6,0x1a7", 121 121 + "MSRValue": "0x184000400", 122 122 + "SampleAfterValue": "100003", 123 123 + "UMask": "0x1" 124 124 + }, 125 125 + { 126 126 + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", 127 127 + "EventCode": "0xB7, 0xBB", 128 128 + "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", 129 129 + "MSRIndex": "0x1a6,0x1a7", 130 130 + "MSRValue": "0x184000400", 131 131 + "SampleAfterValue": "100003", 132 132 + "UMask": "0x1" 133 133 + }, 134 134 + { 135 135 + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", 136 136 + "EventCode": "0xB7, 0xBB", 137 137 + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", 138 138 + "MSRIndex": "0x1a6,0x1a7", 139 139 + "MSRValue": "0x10010", 140 140 + "SampleAfterValue": "100003", 141 141 + "UMask": "0x1" 142 142 + }, 143 143 + { 144 144 + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", 145 145 + "EventCode": "0xB7, 0xBB", 146 146 + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", 147 147 + "MSRIndex": "0x1a6,0x1a7", 148 148 + "MSRValue": "0x184000010", 149 149 + "SampleAfterValue": "100003", 150 150 + "UMask": "0x1" 151 151 + }, 152 152 + { 153 153 + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", 154 154 + "EventCode": "0xB7, 0xBB", 155 155 + "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", 156 156 + "MSRIndex": "0x1a6,0x1a7", 157 157 + "MSRValue": "0x184000010", 158 158 + "SampleAfterValue": "100003", 159 159 + "UMask": "0x1" 160 160 + }, 161 161 + { 162 162 + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", 163 163 + "EventCode": "0xB7, 0xBB", 164 164 + "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", 165 165 + "MSRIndex": "0x1a6,0x1a7", 166 166 + "MSRValue": "0x10020", 167 167 + "SampleAfterValue": "100003", 168 168 + "UMask": "0x1" 169 169 + }, 170 170 + { 171 171 + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", 172 172 + "EventCode": "0xB7, 0xBB", 173 173 + "EventName": "OCR.HWPF_L2_RFO.DRAM", 174 174 + "MSRIndex": "0x1a6,0x1a7", 175 175 + "MSRValue": "0x184000020", 176 176 + "SampleAfterValue": "100003", 177 177 + "UMask": "0x1" 178 178 + }, 179 179 + { 180 180 + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", 181 181 + "EventCode": "0xB7, 0xBB", 182 182 + "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", 183 183 + "MSRIndex": "0x1a6,0x1a7", 184 184 + "MSRValue": "0x184000020", 185 185 + "SampleAfterValue": "100003", 186 186 + "UMask": "0x1" 187 187 + }, 188 188 + { 189 189 + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", 190 190 + "EventCode": "0xB7, 0xBB", 191 191 + "EventName": "OCR.OTHER.ANY_RESPONSE", 192 192 + "MSRIndex": "0x1a6,0x1a7", 193 193 + "MSRValue": "0x18000", 194 194 + "SampleAfterValue": "100003", 195 195 + "UMask": "0x1" 196 196 + }, 197 197 + { 198 198 + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", 199 199 + "EventCode": "0xB7, 0xBB", 200 200 + "EventName": "OCR.OTHER.DRAM", 201 201 + "MSRIndex": "0x1a6,0x1a7", 202 202 + "MSRValue": "0x184008000", 203 203 + "SampleAfterValue": "100003", 204 204 + "UMask": "0x1" 205 205 + }, 206 206 + { 207 207 + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", 208 208 + "EventCode": "0xB7, 0xBB", 209 209 + "EventName": "OCR.OTHER.LOCAL_DRAM", 210 210 + "MSRIndex": "0x1a6,0x1a7", 211 211 + "MSRValue": "0x184008000", 212 212 + "SampleAfterValue": "100003", 213 213 + "UMask": "0x1" 214 214 + }, 215 215 + { 216 216 + "BriefDescription": "Counts streaming stores that have any type of response.", 217 217 + "EventCode": "0xB7, 0xBB", 218 218 + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", 219 219 + "MSRIndex": "0x1a6,0x1a7", 220 220 + "MSRValue": "0x10800", 221 221 + "SampleAfterValue": "100003", 222 222 + "UMask": "0x1" 223 223 + }, 224 224 + { 225 225 + "BriefDescription": "Counts streaming stores that DRAM supplied the request.", 226 226 + "EventCode": "0xB7, 0xBB", 227 227 + "EventName": "OCR.STREAMING_WR.DRAM", 228 228 + "MSRIndex": "0x1a6,0x1a7", 229 229 + "MSRValue": "0x184000800", 230 230 + "SampleAfterValue": "100003", 231 231 + "UMask": "0x1" 232 232 + }, 233 233 + { 234 234 + "BriefDescription": "Counts streaming stores that DRAM supplied the request.", 235 235 + "EventCode": "0xB7, 0xBB", 236 236 + "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", 237 237 + "MSRIndex": "0x1a6,0x1a7", 238 238 + "MSRValue": "0x184000800", 239 239 + "SampleAfterValue": "100003", 240 240 + "UMask": "0x1" 241 241 + } 242 242 + ]

+801

tools/perf/pmu-events/arch/x86/rocketlake/pipeline.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", 4 4 + "CounterMask": "1", 5 5 + "EventCode": "0x14", 6 6 + "EventName": "ARITH.DIVIDER_ACTIVE", 7 7 + "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", 8 8 + "SampleAfterValue": "1000003", 9 9 + "UMask": "0x9" 10 10 + }, 11 11 + { 12 12 + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", 13 13 + "EventCode": "0xc1", 14 14 + "EventName": "ASSISTS.ANY", 15 15 + "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.", 16 16 + "SampleAfterValue": "100003", 17 17 + "UMask": "0x7" 18 18 + }, 19 19 + { 20 20 + "BriefDescription": "All branch instructions retired.", 21 21 + "EventCode": "0xc4", 22 22 + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", 23 23 + "PEBS": "1", 24 24 + "PublicDescription": "Counts all branch instructions retired.", 25 25 + "SampleAfterValue": "400009" 26 26 + }, 27 27 + { 28 28 + "BriefDescription": "Conditional branch instructions retired.", 29 29 + "EventCode": "0xc4", 30 30 + "EventName": "BR_INST_RETIRED.COND", 31 31 + "PEBS": "1", 32 32 + "PublicDescription": "Counts conditional branch instructions retired.", 33 33 + "SampleAfterValue": "400009", 34 34 + "UMask": "0x11" 35 35 + }, 36 36 + { 37 37 + "BriefDescription": "Not taken branch instructions retired.", 38 38 + "EventCode": "0xc4", 39 39 + "EventName": "BR_INST_RETIRED.COND_NTAKEN", 40 40 + "PEBS": "1", 41 41 + "PublicDescription": "Counts not taken branch instructions retired.", 42 42 + "SampleAfterValue": "400009", 43 43 + "UMask": "0x10" 44 44 + }, 45 45 + { 46 46 + "BriefDescription": "Taken conditional branch instructions retired.", 47 47 + "EventCode": "0xc4", 48 48 + "EventName": "BR_INST_RETIRED.COND_TAKEN", 49 49 + "PEBS": "1", 50 50 + "PublicDescription": "Counts taken conditional branch instructions retired.", 51 51 + "SampleAfterValue": "400009", 52 52 + "UMask": "0x1" 53 53 + }, 54 54 + { 55 55 + "BriefDescription": "Far branch instructions retired.", 56 56 + "EventCode": "0xc4", 57 57 + "EventName": "BR_INST_RETIRED.FAR_BRANCH", 58 58 + "PEBS": "1", 59 59 + "PublicDescription": "Counts far branch instructions retired.", 60 60 + "SampleAfterValue": "100007", 61 61 + "UMask": "0x40" 62 62 + }, 63 63 + { 64 64 + "BriefDescription": "Indirect near branch instructions retired (excluding returns)", 65 65 + "EventCode": "0xc4", 66 66 + "EventName": "BR_INST_RETIRED.INDIRECT", 67 67 + "PEBS": "1", 68 68 + "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", 69 69 + "SampleAfterValue": "100003", 70 70 + "UMask": "0x80" 71 71 + }, 72 72 + { 73 73 + "BriefDescription": "Direct and indirect near call instructions retired.", 74 74 + "EventCode": "0xc4", 75 75 + "EventName": "BR_INST_RETIRED.NEAR_CALL", 76 76 + "PEBS": "1", 77 77 + "PublicDescription": "Counts both direct and indirect near call instructions retired.", 78 78 + "SampleAfterValue": "100007", 79 79 + "UMask": "0x2" 80 80 + }, 81 81 + { 82 82 + "BriefDescription": "Return instructions retired.", 83 83 + "EventCode": "0xc4", 84 84 + "EventName": "BR_INST_RETIRED.NEAR_RETURN", 85 85 + "PEBS": "1", 86 86 + "PublicDescription": "Counts return instructions retired.", 87 87 + "SampleAfterValue": "100007", 88 88 + "UMask": "0x8" 89 89 + }, 90 90 + { 91 91 + "BriefDescription": "Taken branch instructions retired.", 92 92 + "EventCode": "0xc4", 93 93 + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", 94 94 + "PEBS": "1", 95 95 + "PublicDescription": "Counts taken branch instructions retired.", 96 96 + "SampleAfterValue": "400009", 97 97 + "UMask": "0x20" 98 98 + }, 99 99 + { 100 100 + "BriefDescription": "All mispredicted branch instructions retired.", 101 101 + "EventCode": "0xc5", 102 102 + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", 103 103 + "PEBS": "1", 104 104 + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", 105 105 + "SampleAfterValue": "50021" 106 106 + }, 107 107 + { 108 108 + "BriefDescription": "Mispredicted conditional branch instructions retired.", 109 109 + "EventCode": "0xc5", 110 110 + "EventName": "BR_MISP_RETIRED.COND", 111 111 + "PEBS": "1", 112 112 + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", 113 113 + "SampleAfterValue": "50021", 114 114 + "UMask": "0x11" 115 115 + }, 116 116 + { 117 117 + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", 118 118 + "EventCode": "0xc5", 119 119 + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", 120 120 + "PEBS": "1", 121 121 + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", 122 122 + "SampleAfterValue": "50021", 123 123 + "UMask": "0x10" 124 124 + }, 125 125 + { 126 126 + "BriefDescription": "number of branch instructions retired that were mispredicted and taken.", 127 127 + "EventCode": "0xc5", 128 128 + "EventName": "BR_MISP_RETIRED.COND_TAKEN", 129 129 + "PEBS": "1", 130 130 + "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", 131 131 + "SampleAfterValue": "50021", 132 132 + "UMask": "0x1" 133 133 + }, 134 134 + { 135 135 + "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", 136 136 + "EventCode": "0xc5", 137 137 + "EventName": "BR_MISP_RETIRED.INDIRECT", 138 138 + "PEBS": "1", 139 139 + "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", 140 140 + "SampleAfterValue": "50021", 141 141 + "UMask": "0x80" 142 142 + }, 143 143 + { 144 144 + "BriefDescription": "Mispredicted indirect CALL instructions retired.", 145 145 + "EventCode": "0xc5", 146 146 + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", 147 147 + "PEBS": "1", 148 148 + "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", 149 149 + "SampleAfterValue": "50021", 150 150 + "UMask": "0x2" 151 151 + }, 152 152 + { 153 153 + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", 154 154 + "EventCode": "0xc5", 155 155 + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", 156 156 + "PEBS": "1", 157 157 + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", 158 158 + "SampleAfterValue": "50021", 159 159 + "UMask": "0x20" 160 160 + }, 161 161 + { 162 162 + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", 163 163 + "EventCode": "0xc5", 164 164 + "EventName": "BR_MISP_RETIRED.RET", 165 165 + "PEBS": "1", 166 166 + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", 167 167 + "SampleAfterValue": "50021", 168 168 + "UMask": "0x8" 169 169 + }, 170 170 + { 171 171 + "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", 172 172 + "EventCode": "0xec", 173 173 + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", 174 174 + "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", 175 175 + "SampleAfterValue": "2000003", 176 176 + "UMask": "0x2" 177 177 + }, 178 178 + { 179 179 + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", 180 180 + "EventCode": "0x3C", 181 181 + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", 182 182 + "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.", 183 183 + "SampleAfterValue": "25003", 184 184 + "UMask": "0x2" 185 185 + }, 186 186 + { 187 187 + "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", 188 188 + "EventCode": "0x3c", 189 189 + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", 190 190 + "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", 191 191 + "SampleAfterValue": "2000003", 192 192 + "UMask": "0x8" 193 193 + }, 194 194 + { 195 195 + "BriefDescription": "Reference cycles when the core is not in halt state.", 196 196 + "EventName": "CPU_CLK_UNHALTED.REF_TSC", 197 197 + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", 198 198 + "SampleAfterValue": "2000003", 199 199 + "UMask": "0x3" 200 200 + }, 201 201 + { 202 202 + "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", 203 203 + "EventCode": "0x3C", 204 204 + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", 205 205 + "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.", 206 206 + "SampleAfterValue": "25003", 207 207 + "UMask": "0x1" 208 208 + }, 209 209 + { 210 210 + "BriefDescription": "Core cycles when the thread is not in halt state", 211 211 + "EventName": "CPU_CLK_UNHALTED.THREAD", 212 212 + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", 213 213 + "SampleAfterValue": "2000003", 214 214 + "UMask": "0x2" 215 215 + }, 216 216 + { 217 217 + "BriefDescription": "Thread cycles when thread is not in halt state", 218 218 + "EventCode": "0x3C", 219 219 + "EventName": "CPU_CLK_UNHALTED.THREAD_P", 220 220 + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", 221 221 + "SampleAfterValue": "2000003" 222 222 + }, 223 223 + { 224 224 + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", 225 225 + "CounterMask": "8", 226 226 + "EventCode": "0xA3", 227 227 + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", 228 228 + "SampleAfterValue": "1000003", 229 229 + "UMask": "0x8" 230 230 + }, 231 231 + { 232 232 + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", 233 233 + "CounterMask": "1", 234 234 + "EventCode": "0xA3", 235 235 + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", 236 236 + "SampleAfterValue": "1000003", 237 237 + "UMask": "0x1" 238 238 + }, 239 239 + { 240 240 + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", 241 241 + "CounterMask": "16", 242 242 + "EventCode": "0xA3", 243 243 + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", 244 244 + "SampleAfterValue": "1000003", 245 245 + "UMask": "0x10" 246 246 + }, 247 247 + { 248 248 + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", 249 249 + "CounterMask": "12", 250 250 + "EventCode": "0xA3", 251 251 + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", 252 252 + "SampleAfterValue": "1000003", 253 253 + "UMask": "0xc" 254 254 + }, 255 255 + { 256 256 + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", 257 257 + "CounterMask": "5", 258 258 + "EventCode": "0xa3", 259 259 + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", 260 260 + "SampleAfterValue": "1000003", 261 261 + "UMask": "0x5" 262 262 + }, 263 263 + { 264 264 + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", 265 265 + "CounterMask": "20", 266 266 + "EventCode": "0xa3", 267 267 + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", 268 268 + "SampleAfterValue": "1000003", 269 269 + "UMask": "0x14" 270 270 + }, 271 271 + { 272 272 + "BriefDescription": "Total execution stalls.", 273 273 + "CounterMask": "4", 274 274 + "EventCode": "0xa3", 275 275 + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", 276 276 + "SampleAfterValue": "1000003", 277 277 + "UMask": "0x4" 278 278 + }, 279 279 + { 280 280 + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", 281 281 + "EventCode": "0xa6", 282 282 + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", 283 283 + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", 284 284 + "SampleAfterValue": "2000003", 285 285 + "UMask": "0x2" 286 286 + }, 287 287 + { 288 288 + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", 289 289 + "EventCode": "0xa6", 290 290 + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", 291 291 + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", 292 292 + "SampleAfterValue": "2000003", 293 293 + "UMask": "0x4" 294 294 + }, 295 295 + { 296 296 + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", 297 297 + "EventCode": "0xa6", 298 298 + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", 299 299 + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", 300 300 + "SampleAfterValue": "2000003", 301 301 + "UMask": "0x8" 302 302 + }, 303 303 + { 304 304 + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", 305 305 + "EventCode": "0xa6", 306 306 + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", 307 307 + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", 308 308 + "SampleAfterValue": "2000003", 309 309 + "UMask": "0x10" 310 310 + }, 311 311 + { 312 312 + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", 313 313 + "CounterMask": "2", 314 314 + "EventCode": "0xA6", 315 315 + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", 316 316 + "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", 317 317 + "SampleAfterValue": "1000003", 318 318 + "UMask": "0x40" 319 319 + }, 320 320 + { 321 321 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]", 322 322 + "EventCode": "0x87", 323 323 + "EventName": "ILD_STALL.LCP", 324 324 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]", 325 325 + "SampleAfterValue": "500009", 326 326 + "UMask": "0x1" 327 327 + }, 328 328 + { 329 329 + "BriefDescription": "Instruction decoders utilized in a cycle", 330 330 + "EventCode": "0x55", 331 331 + "EventName": "INST_DECODED.DECODERS", 332 332 + "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.", 333 333 + "SampleAfterValue": "2000003", 334 334 + "UMask": "0x1" 335 335 + }, 336 336 + { 337 337 + "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", 338 338 + "EventName": "INST_RETIRED.ANY", 339 339 + "PEBS": "1", 340 340 + "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", 341 341 + "SampleAfterValue": "2000003", 342 342 + "UMask": "0x1" 343 343 + }, 344 344 + { 345 345 + "BriefDescription": "Number of instructions retired. General Counter - architectural event", 346 346 + "EventCode": "0xc0", 347 347 + "EventName": "INST_RETIRED.ANY_P", 348 348 + "PEBS": "1", 349 349 + "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", 350 350 + "SampleAfterValue": "2000003" 351 351 + }, 352 352 + { 353 353 + "BriefDescription": "Number of all retired NOP instructions.", 354 354 + "EventCode": "0xc0", 355 355 + "EventName": "INST_RETIRED.NOP", 356 356 + "PEBS": "1", 357 357 + "SampleAfterValue": "2000003", 358 358 + "UMask": "0x2" 359 359 + }, 360 360 + { 361 361 + "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution", 362 362 + "EventName": "INST_RETIRED.PREC_DIST", 363 363 + "PEBS": "1", 364 364 + "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.", 365 365 + "SampleAfterValue": "2000003", 366 366 + "UMask": "0x1" 367 367 + }, 368 368 + { 369 369 + "BriefDescription": "Cycles without actually retired instructions.", 370 370 + "CounterMask": "1", 371 371 + "EventCode": "0xc0", 372 372 + "EventName": "INST_RETIRED.STALL_CYCLES", 373 373 + "Invert": "1", 374 374 + "PublicDescription": "This event counts cycles without actually retired instructions.", 375 375 + "SampleAfterValue": "1000003", 376 376 + "UMask": "0x1" 377 377 + }, 378 378 + { 379 379 + "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", 380 380 + "CounterMask": "1", 381 381 + "EventCode": "0x0D", 382 382 + "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", 383 383 + "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", 384 384 + "SampleAfterValue": "2000003", 385 385 + "UMask": "0x3" 386 386 + }, 387 387 + { 388 388 + "BriefDescription": "Clears speculative count", 389 389 + "CounterMask": "1", 390 390 + "EdgeDetect": "1", 391 391 + "EventCode": "0x0D", 392 392 + "EventName": "INT_MISC.CLEARS_COUNT", 393 393 + "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears", 394 394 + "SampleAfterValue": "500009", 395 395 + "UMask": "0x1" 396 396 + }, 397 397 + { 398 398 + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", 399 399 + "EventCode": "0x0d", 400 400 + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", 401 401 + "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", 402 402 + "SampleAfterValue": "500009", 403 403 + "UMask": "0x80" 404 404 + }, 405 405 + { 406 406 + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", 407 407 + "EventCode": "0x0D", 408 408 + "EventName": "INT_MISC.RECOVERY_CYCLES", 409 409 + "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", 410 410 + "SampleAfterValue": "500009", 411 411 + "UMask": "0x1" 412 412 + }, 413 413 + { 414 414 + "BriefDescription": "TMA slots where uops got dropped", 415 415 + "EventCode": "0x0d", 416 416 + "EventName": "INT_MISC.UOP_DROPPING", 417 417 + "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", 418 418 + "SampleAfterValue": "1000003", 419 419 + "UMask": "0x10" 420 420 + }, 421 421 + { 422 422 + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", 423 423 + "EventCode": "0x03", 424 424 + "EventName": "LD_BLOCKS.NO_SR", 425 425 + "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", 426 426 + "SampleAfterValue": "100003", 427 427 + "UMask": "0x8" 428 428 + }, 429 429 + { 430 430 + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", 431 431 + "EventCode": "0x03", 432 432 + "EventName": "LD_BLOCKS.STORE_FORWARD", 433 433 + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", 434 434 + "SampleAfterValue": "100003", 435 435 + "UMask": "0x2" 436 436 + }, 437 437 + { 438 438 + "BriefDescription": "False dependencies due to partial compare on address.", 439 439 + "EventCode": "0x07", 440 440 + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", 441 441 + "PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.", 442 442 + "SampleAfterValue": "100003", 443 443 + "UMask": "0x1" 444 444 + }, 445 445 + { 446 446 + "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", 447 447 + "EventCode": "0x4c", 448 448 + "EventName": "LOAD_HIT_PREFETCH.SWPF", 449 449 + "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", 450 450 + "SampleAfterValue": "100003", 451 451 + "UMask": "0x1" 452 452 + }, 453 453 + { 454 454 + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", 455 455 + "CounterMask": "1", 456 456 + "EventCode": "0xA8", 457 457 + "EventName": "LSD.CYCLES_ACTIVE", 458 458 + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", 459 459 + "SampleAfterValue": "2000003", 460 460 + "UMask": "0x1" 461 461 + }, 462 462 + { 463 463 + "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", 464 464 + "CounterMask": "5", 465 465 + "EventCode": "0xa8", 466 466 + "EventName": "LSD.CYCLES_OK", 467 467 + "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", 468 468 + "SampleAfterValue": "2000003", 469 469 + "UMask": "0x1" 470 470 + }, 471 471 + { 472 472 + "BriefDescription": "Number of Uops delivered by the LSD.", 473 473 + "EventCode": "0xa8", 474 474 + "EventName": "LSD.UOPS", 475 475 + "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", 476 476 + "SampleAfterValue": "2000003", 477 477 + "UMask": "0x1" 478 478 + }, 479 479 + { 480 480 + "BriefDescription": "Number of machine clears (nukes) of any type.", 481 481 + "CounterMask": "1", 482 482 + "EdgeDetect": "1", 483 483 + "EventCode": "0xc3", 484 484 + "EventName": "MACHINE_CLEARS.COUNT", 485 485 + "PublicDescription": "Counts the number of machine clears (nukes) of any type.", 486 486 + "SampleAfterValue": "100003", 487 487 + "UMask": "0x1" 488 488 + }, 489 489 + { 490 490 + "BriefDescription": "Self-modifying code (SMC) detected.", 491 491 + "EventCode": "0xc3", 492 492 + "EventName": "MACHINE_CLEARS.SMC", 493 493 + "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", 494 494 + "SampleAfterValue": "100003", 495 495 + "UMask": "0x4" 496 496 + }, 497 497 + { 498 498 + "BriefDescription": "Increments whenever there is an update to the LBR array.", 499 499 + "EventCode": "0xcc", 500 500 + "EventName": "MISC_RETIRED.LBR_INSERTS", 501 501 + "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly.", 502 502 + "SampleAfterValue": "100003", 503 503 + "UMask": "0x20" 504 504 + }, 505 505 + { 506 506 + "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", 507 507 + "EventCode": "0xcc", 508 508 + "EventName": "MISC_RETIRED.PAUSE_INST", 509 509 + "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", 510 510 + "SampleAfterValue": "100003", 511 511 + "UMask": "0x40" 512 512 + }, 513 513 + { 514 514 + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", 515 515 + "EventCode": "0xa2", 516 516 + "EventName": "RESOURCE_STALLS.SB", 517 517 + "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", 518 518 + "SampleAfterValue": "100003", 519 519 + "UMask": "0x8" 520 520 + }, 521 521 + { 522 522 + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", 523 523 + "EventCode": "0xa2", 524 524 + "EventName": "RESOURCE_STALLS.SCOREBOARD", 525 525 + "SampleAfterValue": "100003", 526 526 + "UMask": "0x2" 527 527 + }, 528 528 + { 529 529 + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", 530 530 + "EventCode": "0x5e", 531 531 + "EventName": "RS_EVENTS.EMPTY_CYCLES", 532 532 + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", 533 533 + "SampleAfterValue": "1000003", 534 534 + "UMask": "0x1" 535 535 + }, 536 536 + { 537 537 + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", 538 538 + "CounterMask": "1", 539 539 + "EdgeDetect": "1", 540 540 + "EventCode": "0x5E", 541 541 + "EventName": "RS_EVENTS.EMPTY_END", 542 542 + "Invert": "1", 543 543 + "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", 544 544 + "SampleAfterValue": "100003", 545 545 + "UMask": "0x1" 546 546 + }, 547 547 + { 548 548 + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", 549 549 + "EventCode": "0xa4", 550 550 + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", 551 551 + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", 552 552 + "SampleAfterValue": "10000003", 553 553 + "UMask": "0x2" 554 554 + }, 555 555 + { 556 556 + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", 557 557 + "EventCode": "0xa4", 558 558 + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", 559 559 + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the speculative path as well as the out-of-order engine recovery past a branch misprediction.", 560 560 + "SampleAfterValue": "10000003", 561 561 + "UMask": "0x8" 562 562 + }, 563 563 + { 564 564 + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", 565 565 + "EventName": "TOPDOWN.SLOTS", 566 566 + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", 567 567 + "SampleAfterValue": "10000003", 568 568 + "UMask": "0x4" 569 569 + }, 570 570 + { 571 571 + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", 572 572 + "EventCode": "0xa4", 573 573 + "EventName": "TOPDOWN.SLOTS_P", 574 574 + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", 575 575 + "SampleAfterValue": "10000003", 576 576 + "UMask": "0x1" 577 577 + }, 578 578 + { 579 579 + "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0", 580 580 + "EventCode": "0x56", 581 581 + "EventName": "UOPS_DECODED.DEC0", 582 582 + "PublicDescription": "Uops exclusively fetched by decoder 0", 583 583 + "SampleAfterValue": "1000003", 584 584 + "UMask": "0x1" 585 585 + }, 586 586 + { 587 587 + "BriefDescription": "Number of uops executed on port 0", 588 588 + "EventCode": "0xa1", 589 589 + "EventName": "UOPS_DISPATCHED.PORT_0", 590 590 + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.", 591 591 + "SampleAfterValue": "2000003", 592 592 + "UMask": "0x1" 593 593 + }, 594 594 + { 595 595 + "BriefDescription": "Number of uops executed on port 1", 596 596 + "EventCode": "0xa1", 597 597 + "EventName": "UOPS_DISPATCHED.PORT_1", 598 598 + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.", 599 599 + "SampleAfterValue": "2000003", 600 600 + "UMask": "0x2" 601 601 + }, 602 602 + { 603 603 + "BriefDescription": "Number of uops executed on port 2 and 3", 604 604 + "EventCode": "0xa1", 605 605 + "EventName": "UOPS_DISPATCHED.PORT_2_3", 606 606 + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.", 607 607 + "SampleAfterValue": "2000003", 608 608 + "UMask": "0x4" 609 609 + }, 610 610 + { 611 611 + "BriefDescription": "Number of uops executed on port 4 and 9", 612 612 + "EventCode": "0xa1", 613 613 + "EventName": "UOPS_DISPATCHED.PORT_4_9", 614 614 + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.", 615 615 + "SampleAfterValue": "2000003", 616 616 + "UMask": "0x10" 617 617 + }, 618 618 + { 619 619 + "BriefDescription": "Number of uops executed on port 5", 620 620 + "EventCode": "0xa1", 621 621 + "EventName": "UOPS_DISPATCHED.PORT_5", 622 622 + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.", 623 623 + "SampleAfterValue": "2000003", 624 624 + "UMask": "0x20" 625 625 + }, 626 626 + { 627 627 + "BriefDescription": "Number of uops executed on port 6", 628 628 + "EventCode": "0xa1", 629 629 + "EventName": "UOPS_DISPATCHED.PORT_6", 630 630 + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.", 631 631 + "SampleAfterValue": "2000003", 632 632 + "UMask": "0x40" 633 633 + }, 634 634 + { 635 635 + "BriefDescription": "Number of uops executed on port 7 and 8", 636 636 + "EventCode": "0xa1", 637 637 + "EventName": "UOPS_DISPATCHED.PORT_7_8", 638 638 + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.", 639 639 + "SampleAfterValue": "2000003", 640 640 + "UMask": "0x80" 641 641 + }, 642 642 + { 643 643 + "BriefDescription": "Number of uops executed on the core.", 644 644 + "EventCode": "0xB1", 645 645 + "EventName": "UOPS_EXECUTED.CORE", 646 646 + "PublicDescription": "Counts the number of uops executed from any thread.", 647 647 + "SampleAfterValue": "2000003", 648 648 + "UMask": "0x2" 649 649 + }, 650 650 + { 651 651 + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", 652 652 + "CounterMask": "1", 653 653 + "EventCode": "0xB1", 654 654 + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", 655 655 + "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", 656 656 + "SampleAfterValue": "2000003", 657 657 + "UMask": "0x2" 658 658 + }, 659 659 + { 660 660 + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", 661 661 + "CounterMask": "2", 662 662 + "EventCode": "0xB1", 663 663 + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", 664 664 + "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", 665 665 + "SampleAfterValue": "2000003", 666 666 + "UMask": "0x2" 667 667 + }, 668 668 + { 669 669 + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", 670 670 + "CounterMask": "3", 671 671 + "EventCode": "0xB1", 672 672 + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", 673 673 + "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", 674 674 + "SampleAfterValue": "2000003", 675 675 + "UMask": "0x2" 676 676 + }, 677 677 + { 678 678 + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", 679 679 + "CounterMask": "4", 680 680 + "EventCode": "0xB1", 681 681 + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", 682 682 + "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", 683 683 + "SampleAfterValue": "2000003", 684 684 + "UMask": "0x2" 685 685 + }, 686 686 + { 687 687 + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", 688 688 + "CounterMask": "1", 689 689 + "EventCode": "0xb1", 690 690 + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", 691 691 + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", 692 692 + "SampleAfterValue": "2000003", 693 693 + "UMask": "0x1" 694 694 + }, 695 695 + { 696 696 + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", 697 697 + "CounterMask": "2", 698 698 + "EventCode": "0xb1", 699 699 + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", 700 700 + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", 701 701 + "SampleAfterValue": "2000003", 702 702 + "UMask": "0x1" 703 703 + }, 704 704 + { 705 705 + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", 706 706 + "CounterMask": "3", 707 707 + "EventCode": "0xb1", 708 708 + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", 709 709 + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", 710 710 + "SampleAfterValue": "2000003", 711 711 + "UMask": "0x1" 712 712 + }, 713 713 + { 714 714 + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", 715 715 + "CounterMask": "4", 716 716 + "EventCode": "0xb1", 717 717 + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", 718 718 + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", 719 719 + "SampleAfterValue": "2000003", 720 720 + "UMask": "0x1" 721 721 + }, 722 722 + { 723 723 + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", 724 724 + "CounterMask": "1", 725 725 + "EventCode": "0xB1", 726 726 + "EventName": "UOPS_EXECUTED.STALL_CYCLES", 727 727 + "Invert": "1", 728 728 + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", 729 729 + "SampleAfterValue": "2000003", 730 730 + "UMask": "0x1" 731 731 + }, 732 732 + { 733 733 + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", 734 734 + "EventCode": "0xb1", 735 735 + "EventName": "UOPS_EXECUTED.THREAD", 736 736 + "SampleAfterValue": "2000003", 737 737 + "UMask": "0x1" 738 738 + }, 739 739 + { 740 740 + "BriefDescription": "Counts the number of x87 uops dispatched.", 741 741 + "EventCode": "0xB1", 742 742 + "EventName": "UOPS_EXECUTED.X87", 743 743 + "PublicDescription": "Counts the number of x87 uops executed.", 744 744 + "SampleAfterValue": "2000003", 745 745 + "UMask": "0x10" 746 746 + }, 747 747 + { 748 748 + "BriefDescription": "Uops that RAT issues to RS", 749 749 + "EventCode": "0x0e", 750 750 + "EventName": "UOPS_ISSUED.ANY", 751 751 + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", 752 752 + "SampleAfterValue": "2000003", 753 753 + "UMask": "0x1" 754 754 + }, 755 755 + { 756 756 + "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", 757 757 + "CounterMask": "1", 758 758 + "EventCode": "0x0E", 759 759 + "EventName": "UOPS_ISSUED.STALL_CYCLES", 760 760 + "Invert": "1", 761 761 + "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", 762 762 + "SampleAfterValue": "1000003", 763 763 + "UMask": "0x1" 764 764 + }, 765 765 + { 766 766 + "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", 767 767 + "EventCode": "0x0e", 768 768 + "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", 769 769 + "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to 'Mixing Intel AVX and Intel SSE Code' section of the Optimization Guide.", 770 770 + "SampleAfterValue": "100003", 771 771 + "UMask": "0x2" 772 772 + }, 773 773 + { 774 774 + "BriefDescription": "Retirement slots used.", 775 775 + "EventCode": "0xc2", 776 776 + "EventName": "UOPS_RETIRED.SLOTS", 777 777 + "PublicDescription": "Counts the retirement slots used each cycle.", 778 778 + "SampleAfterValue": "2000003", 779 779 + "UMask": "0x2" 780 780 + }, 781 781 + { 782 782 + "BriefDescription": "Cycles without actually retired uops.", 783 783 + "CounterMask": "1", 784 784 + "EventCode": "0xc2", 785 785 + "EventName": "UOPS_RETIRED.STALL_CYCLES", 786 786 + "Invert": "1", 787 787 + "PublicDescription": "This event counts cycles without actually retired uops.", 788 788 + "SampleAfterValue": "1000003", 789 789 + "UMask": "0x2" 790 790 + }, 791 791 + { 792 792 + "BriefDescription": "Cycles with less than 10 actually retired uops.", 793 793 + "CounterMask": "10", 794 794 + "EventCode": "0xc2", 795 795 + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", 796 796 + "Invert": "1", 797 797 + "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", 798 798 + "SampleAfterValue": "1000003", 799 799 + "UMask": "0x2" 800 800 + } 801 801 + ]

+1571

tools/perf/pmu-events/arch/x86/rocketlake/rkl-metrics.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "C10 residency percent per package", 4 4 + "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", 5 5 + "MetricGroup": "Power", 6 6 + "MetricName": "C10_Pkg_Residency", 7 7 + "ScaleUnit": "100%" 8 8 + }, 9 9 + { 10 10 + "BriefDescription": "C2 residency percent per package", 11 11 + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", 12 12 + "MetricGroup": "Power", 13 13 + "MetricName": "C2_Pkg_Residency", 14 14 + "ScaleUnit": "100%" 15 15 + }, 16 16 + { 17 17 + "BriefDescription": "C3 residency percent per package", 18 18 + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", 19 19 + "MetricGroup": "Power", 20 20 + "MetricName": "C3_Pkg_Residency", 21 21 + "ScaleUnit": "100%" 22 22 + }, 23 23 + { 24 24 + "BriefDescription": "C6 residency percent per core", 25 25 + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", 26 26 + "MetricGroup": "Power", 27 27 + "MetricName": "C6_Core_Residency", 28 28 + "ScaleUnit": "100%" 29 29 + }, 30 30 + { 31 31 + "BriefDescription": "C6 residency percent per package", 32 32 + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", 33 33 + "MetricGroup": "Power", 34 34 + "MetricName": "C6_Pkg_Residency", 35 35 + "ScaleUnit": "100%" 36 36 + }, 37 37 + { 38 38 + "BriefDescription": "C7 residency percent per core", 39 39 + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", 40 40 + "MetricGroup": "Power", 41 41 + "MetricName": "C7_Core_Residency", 42 42 + "ScaleUnit": "100%" 43 43 + }, 44 44 + { 45 45 + "BriefDescription": "C7 residency percent per package", 46 46 + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", 47 47 + "MetricGroup": "Power", 48 48 + "MetricName": "C7_Pkg_Residency", 49 49 + "ScaleUnit": "100%" 50 50 + }, 51 51 + { 52 52 + "BriefDescription": "C8 residency percent per package", 53 53 + "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", 54 54 + "MetricGroup": "Power", 55 55 + "MetricName": "C8_Pkg_Residency", 56 56 + "ScaleUnit": "100%" 57 57 + }, 58 58 + { 59 59 + "BriefDescription": "C9 residency percent per package", 60 60 + "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", 61 61 + "MetricGroup": "Power", 62 62 + "MetricName": "C9_Pkg_Residency", 63 63 + "ScaleUnit": "100%" 64 64 + }, 65 65 + { 66 66 + "BriefDescription": "Uncore frequency per die [GHZ]", 67 67 + "MetricExpr": "tma_info_system_socket_clks / #num_dies / duration_time / 1e9", 68 68 + "MetricGroup": "SoC", 69 69 + "MetricName": "UNCORE_FREQ" 70 70 + }, 71 71 + { 72 72 + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", 73 73 + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", 74 74 + "MetricGroup": "smi", 75 75 + "MetricName": "smi_cycles", 76 76 + "MetricThreshold": "smi_cycles > 0.1", 77 77 + "ScaleUnit": "100%" 78 78 + }, 79 79 + { 80 80 + "BriefDescription": "Number of SMI interrupts.", 81 81 + "MetricExpr": "msr@smi@", 82 82 + "MetricGroup": "smi", 83 83 + "MetricName": "smi_num", 84 84 + "ScaleUnit": "1SMI#" 85 85 + }, 86 86 + { 87 87 + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", 88 88 + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_thread_clks", 89 89 + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", 90 90 + "MetricName": "tma_4k_aliasing", 91 91 + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 92 92 + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", 93 93 + "ScaleUnit": "100%" 94 94 + }, 95 95 + { 96 96 + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", 97 97 + "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * tma_info_core_core_clks)", 98 98 + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", 99 99 + "MetricName": "tma_alu_op_utilization", 100 100 + "MetricThreshold": "tma_alu_op_utilization > 0.6", 101 101 + "ScaleUnit": "100%" 102 102 + }, 103 103 + { 104 104 + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", 105 105 + "MetricExpr": "100 * ASSISTS.ANY / tma_info_thread_slots", 106 106 + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", 107 107 + "MetricName": "tma_assists", 108 108 + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", 109 109 + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", 110 110 + "ScaleUnit": "100%" 111 111 + }, 112 112 + { 113 113 + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", 114 114 + "DefaultMetricgroupName": "TopdownL1", 115 115 + "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@ / tma_info_thread_slots", 116 116 + "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", 117 117 + "MetricName": "tma_backend_bound", 118 118 + "MetricThreshold": "tma_backend_bound > 0.2", 119 119 + "MetricgroupNoGroup": "TopdownL1;Default", 120 120 + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", 121 121 + "ScaleUnit": "100%" 122 122 + }, 123 123 + { 124 124 + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", 125 125 + "DefaultMetricgroupName": "TopdownL1", 126 126 + "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)", 127 127 + "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", 128 128 + "MetricName": "tma_bad_speculation", 129 129 + "MetricThreshold": "tma_bad_speculation > 0.15", 130 130 + "MetricgroupNoGroup": "TopdownL1;Default", 131 131 + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", 132 132 + "ScaleUnit": "100%" 133 133 + }, 134 134 + { 135 135 + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.", 136 136 + "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * tma_info_thread_slots)", 137 137 + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", 138 138 + "MetricName": "tma_branch_instructions", 139 139 + "MetricThreshold": "tma_branch_instructions > 0.1 & tma_light_operations > 0.6", 140 140 + "ScaleUnit": "100%" 141 141 + }, 142 142 + { 143 143 + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", 144 144 + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", 145 145 + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", 146 146 + "MetricName": "tma_branch_mispredicts", 147 147 + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", 148 148 + "MetricgroupNoGroup": "TopdownL2", 149 149 + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers", 150 150 + "ScaleUnit": "100%" 151 151 + }, 152 152 + { 153 153 + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", 154 154 + "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks + tma_unknown_branches", 155 155 + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", 156 156 + "MetricName": "tma_branch_resteers", 157 157 + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", 158 158 + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", 159 159 + "ScaleUnit": "100%" 160 160 + }, 161 161 + { 162 162 + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", 163 163 + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", 164 164 + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", 165 165 + "MetricName": "tma_cisc", 166 166 + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", 167 167 + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", 168 168 + "ScaleUnit": "100%" 169 169 + }, 170 170 + { 171 171 + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", 172 172 + "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks", 173 173 + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", 174 174 + "MetricName": "tma_clears_resteers", 175 175 + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", 176 176 + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", 177 177 + "ScaleUnit": "100%" 178 178 + }, 179 179 + { 180 180 + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", 181 181 + "MetricConstraint": "NO_GROUP_EVENTS", 182 182 + "MetricExpr": "(29 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 23.5 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks", 183 183 + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", 184 184 + "MetricName": "tma_contested_accesses", 185 185 + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 186 186 + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", 187 187 + "ScaleUnit": "100%" 188 188 + }, 189 189 + { 190 190 + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", 191 191 + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", 192 192 + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 193 193 + "MetricName": "tma_core_bound", 194 194 + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", 195 195 + "MetricgroupNoGroup": "TopdownL2", 196 196 + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", 197 197 + "ScaleUnit": "100%" 198 198 + }, 199 199 + { 200 200 + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", 201 201 + "MetricConstraint": "NO_GROUP_EVENTS", 202 202 + "MetricExpr": "23.5 * tma_info_system_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks", 203 203 + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", 204 204 + "MetricName": "tma_data_sharing", 205 205 + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 206 206 + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", 207 207 + "ScaleUnit": "100%" 208 208 + }, 209 209 + { 210 210 + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", 211 211 + "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / tma_info_core_core_clks / 2", 212 212 + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group", 213 213 + "MetricName": "tma_decoder0_alone", 214 214 + "MetricThreshold": "tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 5 > 0.35))", 215 215 + "PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions", 216 216 + "ScaleUnit": "100%" 217 217 + }, 218 218 + { 219 219 + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", 220 220 + "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_thread_clks", 221 221 + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", 222 222 + "MetricName": "tma_divider", 223 223 + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", 224 224 + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", 225 225 + "ScaleUnit": "100%" 226 226 + }, 227 227 + { 228 228 + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", 229 229 + "MetricConstraint": "NO_GROUP_EVENTS", 230 230 + "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_thread_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks - tma_l2_bound", 231 231 + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", 232 232 + "MetricName": "tma_dram_bound", 233 233 + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", 234 234 + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", 235 235 + "ScaleUnit": "100%" 236 236 + }, 237 237 + { 238 238 + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", 239 239 + "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_core_clks / 2", 240 240 + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", 241 241 + "MetricName": "tma_dsb", 242 242 + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 5 > 0.35)", 243 243 + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", 244 244 + "ScaleUnit": "100%" 245 245 + }, 246 246 + { 247 247 + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", 248 248 + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_clks", 249 249 + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", 250 250 + "MetricName": "tma_dsb_switches", 251 251 + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", 252 252 + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", 253 253 + "ScaleUnit": "100%" 254 254 + }, 255 255 + { 256 256 + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", 257 257 + "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", 258 258 + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", 259 259 + "MetricName": "tma_dtlb_load", 260 260 + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 261 261 + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_bottleneck_memory_data_tlbs", 262 262 + "ScaleUnit": "100%" 263 263 + }, 264 264 + { 265 265 + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", 266 266 + "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks", 267 267 + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", 268 268 + "MetricName": "tma_dtlb_store", 269 269 + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 270 270 + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_bottleneck_memory_data_tlbs", 271 271 + "ScaleUnit": "100%" 272 272 + }, 273 273 + { 274 274 + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", 275 275 + "MetricExpr": "32.5 * tma_info_system_average_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks", 276 276 + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", 277 277 + "MetricName": "tma_false_sharing", 278 278 + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 279 279 + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", 280 280 + "ScaleUnit": "100%" 281 281 + }, 282 282 + { 283 283 + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", 284 284 + "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_thread_clks", 285 285 + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", 286 286 + "MetricName": "tma_fb_full", 287 287 + "MetricThreshold": "tma_fb_full > 0.3", 288 288 + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_bottleneck_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", 289 289 + "ScaleUnit": "100%" 290 290 + }, 291 291 + { 292 292 + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", 293 293 + "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", 294 294 + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", 295 295 + "MetricName": "tma_fetch_bandwidth", 296 296 + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 5 > 0.35", 297 297 + "MetricgroupNoGroup": "TopdownL2", 298 298 + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", 299 299 + "ScaleUnit": "100%" 300 300 + }, 301 301 + { 302 302 + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", 303 303 + "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / tma_info_thread_slots", 304 304 + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", 305 305 + "MetricName": "tma_fetch_latency", 306 306 + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", 307 307 + "MetricgroupNoGroup": "TopdownL2", 308 308 + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", 309 309 + "ScaleUnit": "100%" 310 310 + }, 311 311 + { 312 312 + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", 313 313 + "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", 314 314 + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0", 315 315 + "MetricName": "tma_few_uops_instructions", 316 316 + "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1", 317 317 + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone", 318 318 + "ScaleUnit": "100%" 319 319 + }, 320 320 + { 321 321 + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", 322 322 + "MetricConstraint": "NO_GROUP_EVENTS", 323 323 + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", 324 324 + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", 325 325 + "MetricName": "tma_fp_arith", 326 326 + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", 327 327 + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", 328 328 + "ScaleUnit": "100%" 329 329 + }, 330 330 + { 331 331 + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", 332 332 + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / (tma_retiring * tma_info_thread_slots)", 333 333 + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", 334 334 + "MetricName": "tma_fp_scalar", 335 335 + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", 336 336 + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", 337 337 + "ScaleUnit": "100%" 338 338 + }, 339 339 + { 340 340 + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", 341 341 + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ / (tma_retiring * tma_info_thread_slots)", 342 342 + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", 343 343 + "MetricName": "tma_fp_vector", 344 344 + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", 345 345 + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", 346 346 + "ScaleUnit": "100%" 347 347 + }, 348 348 + { 349 349 + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", 350 350 + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * tma_info_thread_slots)", 351 351 + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", 352 352 + "MetricName": "tma_fp_vector_128b", 353 353 + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", 354 354 + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", 355 355 + "ScaleUnit": "100%" 356 356 + }, 357 357 + { 358 358 + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", 359 359 + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * tma_info_thread_slots)", 360 360 + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", 361 361 + "MetricName": "tma_fp_vector_256b", 362 362 + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", 363 363 + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", 364 364 + "ScaleUnit": "100%" 365 365 + }, 366 366 + { 367 367 + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", 368 368 + "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * tma_info_thread_slots)", 369 369 + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", 370 370 + "MetricName": "tma_fp_vector_512b", 371 371 + "MetricThreshold": "tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", 372 372 + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", 373 373 + "ScaleUnit": "100%" 374 374 + }, 375 375 + { 376 376 + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", 377 377 + "DefaultMetricgroupName": "TopdownL1", 378 378 + "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / tma_info_thread_slots", 379 379 + "MetricGroup": "Default;PGO;TmaL1;TopdownL1;tma_L1_group", 380 380 + "MetricName": "tma_frontend_bound", 381 381 + "MetricThreshold": "tma_frontend_bound > 0.15", 382 382 + "MetricgroupNoGroup": "TopdownL1;Default", 383 383 + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", 384 384 + "ScaleUnit": "100%" 385 385 + }, 386 386 + { 387 387 + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", 388 388 + "MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=1@) / IDQ.MITE_UOPS", 389 389 + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 390 390 + "MetricName": "tma_heavy_operations", 391 391 + "MetricThreshold": "tma_heavy_operations > 0.1", 392 392 + "MetricgroupNoGroup": "TopdownL2", 393 393 + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", 394 394 + "ScaleUnit": "100%" 395 395 + }, 396 396 + { 397 397 + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", 398 398 + "MetricExpr": "ICACHE_16B.IFDATA_STALL / tma_info_thread_clks", 399 399 + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", 400 400 + "MetricName": "tma_icache_misses", 401 401 + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", 402 402 + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", 403 403 + "ScaleUnit": "100%" 404 404 + }, 405 405 + { 406 406 + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", 407 407 + "MetricConstraint": "NO_GROUP_EVENTS", 408 408 + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_thread_slots / BR_MISP_RETIRED.ALL_BRANCHES", 409 409 + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", 410 410 + "MetricName": "tma_info_bad_spec_branch_misprediction_cost", 411 411 + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_bottleneck_mispredictions, tma_mispredicts_resteers" 412 412 + }, 413 413 + { 414 414 + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", 415 415 + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN", 416 416 + "MetricGroup": "Bad;BrMispredicts", 417 417 + "MetricName": "tma_info_bad_spec_ipmisp_cond_ntaken", 418 418 + "MetricThreshold": "tma_info_bad_spec_ipmisp_cond_ntaken < 200" 419 419 + }, 420 420 + { 421 421 + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", 422 422 + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", 423 423 + "MetricGroup": "Bad;BrMispredicts", 424 424 + "MetricName": "tma_info_bad_spec_ipmisp_cond_taken", 425 425 + "MetricThreshold": "tma_info_bad_spec_ipmisp_cond_taken < 200" 426 426 + }, 427 427 + { 428 428 + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", 429 429 + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", 430 430 + "MetricGroup": "Bad;BrMispredicts", 431 431 + "MetricName": "tma_info_bad_spec_ipmisp_indirect", 432 432 + "MetricThreshold": "tma_info_bad_spec_ipmisp_indirect < 1e3" 433 433 + }, 434 434 + { 435 435 + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", 436 436 + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RET", 437 437 + "MetricGroup": "Bad;BrMispredicts", 438 438 + "MetricName": "tma_info_bad_spec_ipmisp_ret", 439 439 + "MetricThreshold": "tma_info_bad_spec_ipmisp_ret < 500" 440 440 + }, 441 441 + { 442 442 + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", 443 443 + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", 444 444 + "MetricGroup": "Bad;BadSpec;BrMispredicts", 445 445 + "MetricName": "tma_info_bad_spec_ipmispredict", 446 446 + "MetricThreshold": "tma_info_bad_spec_ipmispredict < 200" 447 447 + }, 448 448 + { 449 449 + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", 450 450 + "MetricConstraint": "NO_GROUP_EVENTS", 451 451 + "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_system_smt_2t_utilization > 0.5 else 0)", 452 452 + "MetricGroup": "Cor;SMT", 453 453 + "MetricName": "tma_info_botlnk_l0_core_bound_likely", 454 454 + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" 455 455 + }, 456 456 + { 457 457 + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck", 458 458 + "MetricConstraint": "NO_GROUP_EVENTS", 459 459 + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite))", 460 460 + "MetricGroup": "DSBmiss;Fed;tma_issueFB", 461 461 + "MetricName": "tma_info_botlnk_l2_dsb_misses", 462 462 + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", 463 463 + "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" 464 464 + }, 465 465 + { 466 466 + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck", 467 467 + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", 468 468 + "MetricGroup": "Fed;FetchLat;IcMiss;tma_issueFL", 469 469 + "MetricName": "tma_info_botlnk_l2_ic_misses", 470 470 + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", 471 471 + "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: " 472 472 + }, 473 473 + { 474 474 + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", 475 475 + "MetricConstraint": "NO_GROUP_EVENTS", 476 476 + "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", 477 477 + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB;tma_issueBC", 478 478 + "MetricName": "tma_info_bottleneck_big_code", 479 479 + "MetricThreshold": "tma_info_bottleneck_big_code > 20", 480 480 + "PublicDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses). Related metrics: tma_info_bottleneck_branching_overhead" 481 481 + }, 482 482 + { 483 483 + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", 484 484 + "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / tma_info_thread_slots)", 485 485 + "MetricGroup": "Ret;tma_issueBC", 486 486 + "MetricName": "tma_info_bottleneck_branching_overhead", 487 487 + "MetricThreshold": "tma_info_bottleneck_branching_overhead > 10", 488 488 + "PublicDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls). Related metrics: tma_info_bottleneck_big_code" 489 489 + }, 490 490 + { 491 491 + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", 492 492 + "MetricConstraint": "NO_GROUP_EVENTS", 493 493 + "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code", 494 494 + "MetricGroup": "Fed;FetchBW;Frontend", 495 495 + "MetricName": "tma_info_bottleneck_instruction_fetch_bw", 496 496 + "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20" 497 497 + }, 498 498 + { 499 499 + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", 500 500 + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", 501 501 + "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", 502 502 + "MetricName": "tma_info_bottleneck_memory_bandwidth", 503 503 + "MetricThreshold": "tma_info_bottleneck_memory_bandwidth > 20", 504 504 + "PublicDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full" 505 505 + }, 506 506 + { 507 507 + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", 508 508 + "MetricConstraint": "NO_GROUP_EVENTS", 509 509 + "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", 510 510 + "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", 511 511 + "MetricName": "tma_info_bottleneck_memory_data_tlbs", 512 512 + "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", 513 513 + "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store" 514 514 + }, 515 515 + { 516 516 + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", 517 517 + "MetricConstraint": "NO_GROUP_EVENTS", 518 518 + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", 519 519 + "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", 520 520 + "MetricName": "tma_info_bottleneck_memory_latency", 521 521 + "MetricThreshold": "tma_info_bottleneck_memory_latency > 20", 522 522 + "PublicDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency" 523 523 + }, 524 524 + { 525 525 + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", 526 526 + "MetricConstraint": "NO_GROUP_EVENTS", 527 527 + "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", 528 528 + "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", 529 529 + "MetricName": "tma_info_bottleneck_mispredictions", 530 530 + "MetricThreshold": "tma_info_bottleneck_mispredictions > 20", 531 531 + "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers" 532 532 + }, 533 533 + { 534 534 + "BriefDescription": "Fraction of branches that are CALL or RET", 535 535 + "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", 536 536 + "MetricGroup": "Bad;Branches", 537 537 + "MetricName": "tma_info_branches_callret" 538 538 + }, 539 539 + { 540 540 + "BriefDescription": "Fraction of branches that are non-taken conditionals", 541 541 + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", 542 542 + "MetricGroup": "Bad;Branches;CodeGen;PGO", 543 543 + "MetricName": "tma_info_branches_cond_nt" 544 544 + }, 545 545 + { 546 546 + "BriefDescription": "Fraction of branches that are taken conditionals", 547 547 + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", 548 548 + "MetricGroup": "Bad;Branches;CodeGen;PGO", 549 549 + "MetricName": "tma_info_branches_cond_tk" 550 550 + }, 551 551 + { 552 552 + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", 553 553 + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", 554 554 + "MetricGroup": "Bad;Branches", 555 555 + "MetricName": "tma_info_branches_jump" 556 556 + }, 557 557 + { 558 558 + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", 559 559 + "MetricExpr": "1 - (tma_info_branches_cond_nt + tma_info_branches_cond_tk + tma_info_branches_callret + tma_info_branches_jump)", 560 560 + "MetricGroup": "Bad;Branches", 561 561 + "MetricName": "tma_info_branches_other_branches" 562 562 + }, 563 563 + { 564 564 + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", 565 565 + "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", 566 566 + "MetricGroup": "SMT", 567 567 + "MetricName": "tma_info_core_core_clks" 568 568 + }, 569 569 + { 570 570 + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", 571 571 + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_core_clks", 572 572 + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", 573 573 + "MetricName": "tma_info_core_coreipc" 574 574 + }, 575 575 + { 576 576 + "BriefDescription": "Floating Point Operations Per Cycle", 577 577 + "MetricConstraint": "NO_GROUP_EVENTS", 578 578 + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_core_clks", 579 579 + "MetricGroup": "Flops;Ret", 580 580 + "MetricName": "tma_info_core_flopc" 581 581 + }, 582 582 + { 583 583 + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", 584 584 + "MetricConstraint": "NO_GROUP_EVENTS", 585 585 + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@) / (2 * tma_info_core_core_clks)", 586 586 + "MetricGroup": "Cor;Flops;HPC", 587 587 + "MetricName": "tma_info_core_fp_arith_utilization", 588 588 + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." 589 589 + }, 590 590 + { 591 591 + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", 592 592 + "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", 593 593 + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", 594 594 + "MetricName": "tma_info_core_ilp" 595 595 + }, 596 596 + { 597 597 + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", 598 598 + "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", 599 599 + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", 600 600 + "MetricName": "tma_info_frontend_dsb_coverage", 601 601 + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_info_thread_ipc / 5 > 0.35", 602 602 + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp" 603 603 + }, 604 604 + { 605 605 + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", 606 606 + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", 607 607 + "MetricGroup": "DSBmiss", 608 608 + "MetricName": "tma_info_frontend_dsb_switch_cost" 609 609 + }, 610 610 + { 611 611 + "BriefDescription": "Average number of Uops issued by front-end when it issued something", 612 612 + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", 613 613 + "MetricGroup": "Fed;FetchBW", 614 614 + "MetricName": "tma_info_frontend_fetch_upc" 615 615 + }, 616 616 + { 617 617 + "BriefDescription": "Average Latency for L1 instruction cache misses", 618 618 + "MetricExpr": "ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@", 619 619 + "MetricGroup": "Fed;FetchLat;IcMiss", 620 620 + "MetricName": "tma_info_frontend_icache_miss_latency" 621 621 + }, 622 622 + { 623 623 + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", 624 624 + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", 625 625 + "MetricGroup": "DSBmiss;Fed", 626 626 + "MetricName": "tma_info_frontend_ipdsb_miss_ret", 627 627 + "MetricThreshold": "tma_info_frontend_ipdsb_miss_ret < 50" 628 628 + }, 629 629 + { 630 630 + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", 631 631 + "MetricExpr": "tma_info_inst_mix_instructions / BACLEARS.ANY", 632 632 + "MetricGroup": "Fed", 633 633 + "MetricName": "tma_info_frontend_ipunknown_branch" 634 634 + }, 635 635 + { 636 636 + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", 637 637 + "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", 638 638 + "MetricGroup": "IcMiss", 639 639 + "MetricName": "tma_info_frontend_l2mpki_code" 640 640 + }, 641 641 + { 642 642 + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", 643 643 + "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", 644 644 + "MetricGroup": "IcMiss", 645 645 + "MetricName": "tma_info_frontend_l2mpki_code_all" 646 646 + }, 647 647 + { 648 648 + "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", 649 649 + "MetricExpr": "LSD.UOPS / UOPS_ISSUED.ANY", 650 650 + "MetricGroup": "Fed;LSD", 651 651 + "MetricName": "tma_info_frontend_lsd_coverage" 652 652 + }, 653 653 + { 654 654 + "BriefDescription": "Branch instructions per taken branch.", 655 655 + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", 656 656 + "MetricGroup": "Branches;Fed;PGO", 657 657 + "MetricName": "tma_info_inst_mix_bptkbranch" 658 658 + }, 659 659 + { 660 660 + "BriefDescription": "Total number of retired Instructions", 661 661 + "MetricExpr": "INST_RETIRED.ANY", 662 662 + "MetricGroup": "Summary;TmaL1;tma_L1_group", 663 663 + "MetricName": "tma_info_inst_mix_instructions", 664 664 + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" 665 665 + }, 666 666 + { 667 667 + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", 668 668 + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@)", 669 669 + "MetricGroup": "Flops;InsType", 670 670 + "MetricName": "tma_info_inst_mix_iparith", 671 671 + "MetricThreshold": "tma_info_inst_mix_iparith < 10", 672 672 + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." 673 673 + }, 674 674 + { 675 675 + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", 676 676 + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", 677 677 + "MetricGroup": "Flops;FpVector;InsType", 678 678 + "MetricName": "tma_info_inst_mix_iparith_avx128", 679 679 + "MetricThreshold": "tma_info_inst_mix_iparith_avx128 < 10", 680 680 + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." 681 681 + }, 682 682 + { 683 683 + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", 684 684 + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", 685 685 + "MetricGroup": "Flops;FpVector;InsType", 686 686 + "MetricName": "tma_info_inst_mix_iparith_avx256", 687 687 + "MetricThreshold": "tma_info_inst_mix_iparith_avx256 < 10", 688 688 + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." 689 689 + }, 690 690 + { 691 691 + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", 692 692 + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", 693 693 + "MetricGroup": "Flops;FpVector;InsType", 694 694 + "MetricName": "tma_info_inst_mix_iparith_avx512", 695 695 + "MetricThreshold": "tma_info_inst_mix_iparith_avx512 < 10", 696 696 + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." 697 697 + }, 698 698 + { 699 699 + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", 700 700 + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 701 701 + "MetricGroup": "Flops;FpScalar;InsType", 702 702 + "MetricName": "tma_info_inst_mix_iparith_scalar_dp", 703 703 + "MetricThreshold": "tma_info_inst_mix_iparith_scalar_dp < 10", 704 704 + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." 705 705 + }, 706 706 + { 707 707 + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", 708 708 + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 709 709 + "MetricGroup": "Flops;FpScalar;InsType", 710 710 + "MetricName": "tma_info_inst_mix_iparith_scalar_sp", 711 711 + "MetricThreshold": "tma_info_inst_mix_iparith_scalar_sp < 10", 712 712 + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." 713 713 + }, 714 714 + { 715 715 + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", 716 716 + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", 717 717 + "MetricGroup": "Branches;Fed;InsType", 718 718 + "MetricName": "tma_info_inst_mix_ipbranch", 719 719 + "MetricThreshold": "tma_info_inst_mix_ipbranch < 8" 720 720 + }, 721 721 + { 722 722 + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", 723 723 + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", 724 724 + "MetricGroup": "Branches;Fed;PGO", 725 725 + "MetricName": "tma_info_inst_mix_ipcall", 726 726 + "MetricThreshold": "tma_info_inst_mix_ipcall < 200" 727 727 + }, 728 728 + { 729 729 + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", 730 730 + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", 731 731 + "MetricGroup": "Flops;InsType", 732 732 + "MetricName": "tma_info_inst_mix_ipflop", 733 733 + "MetricThreshold": "tma_info_inst_mix_ipflop < 10" 734 734 + }, 735 735 + { 736 736 + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", 737 737 + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", 738 738 + "MetricGroup": "InsType", 739 739 + "MetricName": "tma_info_inst_mix_ipload", 740 740 + "MetricThreshold": "tma_info_inst_mix_ipload < 3" 741 741 + }, 742 742 + { 743 743 + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", 744 744 + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", 745 745 + "MetricGroup": "InsType", 746 746 + "MetricName": "tma_info_inst_mix_ipstore", 747 747 + "MetricThreshold": "tma_info_inst_mix_ipstore < 8" 748 748 + }, 749 749 + { 750 750 + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", 751 751 + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", 752 752 + "MetricGroup": "Prefetches", 753 753 + "MetricName": "tma_info_inst_mix_ipswpf", 754 754 + "MetricThreshold": "tma_info_inst_mix_ipswpf < 100" 755 755 + }, 756 756 + { 757 757 + "BriefDescription": "Instruction per taken branch", 758 758 + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", 759 759 + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", 760 760 + "MetricName": "tma_info_inst_mix_iptb", 761 761 + "MetricThreshold": "tma_info_inst_mix_iptb < 11", 762 762 + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp" 763 763 + }, 764 764 + { 765 765 + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", 766 766 + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", 767 767 + "MetricGroup": "Mem;MemoryBW", 768 768 + "MetricName": "tma_info_memory_core_l1d_cache_fill_bw" 769 769 + }, 770 770 + { 771 771 + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", 772 772 + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", 773 773 + "MetricGroup": "Mem;MemoryBW", 774 774 + "MetricName": "tma_info_memory_core_l2_cache_fill_bw" 775 775 + }, 776 776 + { 777 777 + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", 778 778 + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", 779 779 + "MetricGroup": "Mem;MemoryBW;Offcore", 780 780 + "MetricName": "tma_info_memory_core_l3_cache_access_bw" 781 781 + }, 782 782 + { 783 783 + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", 784 784 + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", 785 785 + "MetricGroup": "Mem;MemoryBW", 786 786 + "MetricName": "tma_info_memory_core_l3_cache_fill_bw" 787 787 + }, 788 788 + { 789 789 + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", 790 790 + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", 791 791 + "MetricGroup": "CacheMisses;Mem", 792 792 + "MetricName": "tma_info_memory_fb_hpki" 793 793 + }, 794 794 + { 795 795 + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", 796 796 + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", 797 797 + "MetricGroup": "CacheMisses;Mem", 798 798 + "MetricName": "tma_info_memory_l1mpki" 799 799 + }, 800 800 + { 801 801 + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", 802 802 + "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", 803 803 + "MetricGroup": "CacheMisses;Mem", 804 804 + "MetricName": "tma_info_memory_l1mpki_load" 805 805 + }, 806 806 + { 807 807 + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", 808 808 + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", 809 809 + "MetricGroup": "CacheMisses;Mem", 810 810 + "MetricName": "tma_info_memory_l2hpki_all" 811 811 + }, 812 812 + { 813 813 + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", 814 814 + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", 815 815 + "MetricGroup": "CacheMisses;Mem", 816 816 + "MetricName": "tma_info_memory_l2hpki_load" 817 817 + }, 818 818 + { 819 819 + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", 820 820 + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", 821 821 + "MetricGroup": "Backend;CacheMisses;Mem", 822 822 + "MetricName": "tma_info_memory_l2mpki" 823 823 + }, 824 824 + { 825 825 + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", 826 826 + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", 827 827 + "MetricGroup": "CacheMisses;Mem;Offcore", 828 828 + "MetricName": "tma_info_memory_l2mpki_all" 829 829 + }, 830 830 + { 831 831 + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", 832 832 + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", 833 833 + "MetricGroup": "CacheMisses;Mem", 834 834 + "MetricName": "tma_info_memory_l2mpki_load" 835 835 + }, 836 836 + { 837 837 + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", 838 838 + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", 839 839 + "MetricGroup": "CacheMisses;Mem", 840 840 + "MetricName": "tma_info_memory_l3mpki" 841 841 + }, 842 842 + { 843 843 + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", 844 844 + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", 845 845 + "MetricGroup": "Mem;MemoryBound;MemoryLat", 846 846 + "MetricName": "tma_info_memory_load_miss_real_latency" 847 847 + }, 848 848 + { 849 849 + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", 850 850 + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", 851 851 + "MetricGroup": "Mem;MemoryBW;MemoryBound", 852 852 + "MetricName": "tma_info_memory_mlp", 853 853 + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" 854 854 + }, 855 855 + { 856 856 + "BriefDescription": "Average Parallel L2 cache miss data reads", 857 857 + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", 858 858 + "MetricGroup": "Memory_BW;Offcore", 859 859 + "MetricName": "tma_info_memory_oro_data_l2_mlp" 860 860 + }, 861 861 + { 862 862 + "BriefDescription": "Average Latency for L2 cache miss demand Loads", 863 863 + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", 864 864 + "MetricGroup": "Memory_Lat;Offcore", 865 865 + "MetricName": "tma_info_memory_oro_load_l2_miss_latency" 866 866 + }, 867 867 + { 868 868 + "BriefDescription": "Average Parallel L2 cache miss demand Loads", 869 869 + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=1@", 870 870 + "MetricGroup": "Memory_BW;Offcore", 871 871 + "MetricName": "tma_info_memory_oro_load_l2_mlp" 872 872 + }, 873 873 + { 874 874 + "BriefDescription": "Average Latency for L3 cache miss demand Loads", 875 875 + "MetricExpr": "cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,umask\\=0x10@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 876 876 + "MetricGroup": "Memory_Lat;Offcore", 877 877 + "MetricName": "tma_info_memory_oro_load_l3_miss_latency" 878 878 + }, 879 879 + { 880 880 + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", 881 881 + "MetricExpr": "tma_info_memory_core_l1d_cache_fill_bw", 882 882 + "MetricGroup": "Mem;MemoryBW", 883 883 + "MetricName": "tma_info_memory_thread_l1d_cache_fill_bw_1t" 884 884 + }, 885 885 + { 886 886 + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", 887 887 + "MetricExpr": "tma_info_memory_core_l2_cache_fill_bw", 888 888 + "MetricGroup": "Mem;MemoryBW", 889 889 + "MetricName": "tma_info_memory_thread_l2_cache_fill_bw_1t" 890 890 + }, 891 891 + { 892 892 + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", 893 893 + "MetricExpr": "tma_info_memory_core_l3_cache_access_bw", 894 894 + "MetricGroup": "Mem;MemoryBW;Offcore", 895 895 + "MetricName": "tma_info_memory_thread_l3_cache_access_bw_1t" 896 896 + }, 897 897 + { 898 898 + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", 899 899 + "MetricExpr": "tma_info_memory_core_l3_cache_fill_bw", 900 900 + "MetricGroup": "Mem;MemoryBW", 901 901 + "MetricName": "tma_info_memory_thread_l3_cache_fill_bw_1t" 902 902 + }, 903 903 + { 904 904 + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", 905 905 + "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", 906 906 + "MetricGroup": "Fed;MemoryTLB", 907 907 + "MetricName": "tma_info_memory_tlb_code_stlb_mpki" 908 908 + }, 909 909 + { 910 910 + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", 911 911 + "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", 912 912 + "MetricGroup": "Mem;MemoryTLB", 913 913 + "MetricName": "tma_info_memory_tlb_load_stlb_mpki" 914 914 + }, 915 915 + { 916 916 + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", 917 917 + "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * tma_info_core_core_clks)", 918 918 + "MetricGroup": "Mem;MemoryTLB", 919 919 + "MetricName": "tma_info_memory_tlb_page_walks_utilization", 920 920 + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0.5" 921 921 + }, 922 922 + { 923 923 + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", 924 924 + "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", 925 925 + "MetricGroup": "Mem;MemoryTLB", 926 926 + "MetricName": "tma_info_memory_tlb_store_stlb_mpki" 927 927 + }, 928 928 + { 929 929 + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", 930 930 + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", 931 931 + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", 932 932 + "MetricName": "tma_info_pipeline_execute" 933 933 + }, 934 934 + { 935 935 + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", 936 936 + "MetricConstraint": "NO_GROUP_EVENTS", 937 937 + "MetricExpr": "tma_retiring * tma_info_thread_slots / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@", 938 938 + "MetricGroup": "Pipeline;Ret", 939 939 + "MetricName": "tma_info_pipeline_retire" 940 940 + }, 941 941 + { 942 942 + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", 943 943 + "MetricExpr": "tma_info_system_turbo_utilization * TSC / 1e9 / duration_time", 944 944 + "MetricGroup": "Power;Summary", 945 945 + "MetricName": "tma_info_system_average_frequency" 946 946 + }, 947 947 + { 948 948 + "BriefDescription": "Average CPU Utilization", 949 949 + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", 950 950 + "MetricGroup": "HPC;Summary", 951 951 + "MetricName": "tma_info_system_cpu_utilization" 952 952 + }, 953 953 + { 954 954 + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", 955 955 + "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", 956 956 + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", 957 957 + "MetricName": "tma_info_system_dram_bw_use", 958 958 + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_bottleneck_memory_bandwidth, tma_mem_bandwidth, tma_sq_full" 959 959 + }, 960 960 + { 961 961 + "BriefDescription": "Giga Floating Point Operations Per Second", 962 962 + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time", 963 963 + "MetricGroup": "Cor;Flops;HPC", 964 964 + "MetricName": "tma_info_system_gflops", 965 965 + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." 966 966 + }, 967 967 + { 968 968 + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", 969 969 + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", 970 970 + "MetricGroup": "Branches;OS", 971 971 + "MetricName": "tma_info_system_ipfarbranch", 972 972 + "MetricThreshold": "tma_info_system_ipfarbranch < 1e6" 973 973 + }, 974 974 + { 975 975 + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", 976 976 + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", 977 977 + "MetricGroup": "OS", 978 978 + "MetricName": "tma_info_system_kernel_cpi" 979 979 + }, 980 980 + { 981 981 + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", 982 982 + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", 983 983 + "MetricGroup": "OS", 984 984 + "MetricName": "tma_info_system_kernel_utilization", 985 985 + "MetricThreshold": "tma_info_system_kernel_utilization > 0.05" 986 986 + }, 987 987 + { 988 988 + "BriefDescription": "Average number of parallel data read requests to external memory", 989 989 + "MetricExpr": "UNC_ARB_DAT_OCCUPANCY.RD / cpu@UNC_ARB_DAT_OCCUPANCY.RD\\,cmask\\=1@", 990 990 + "MetricGroup": "Mem;MemoryBW;SoC", 991 991 + "MetricName": "tma_info_system_mem_parallel_reads", 992 992 + "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches" 993 993 + }, 994 994 + { 995 995 + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", 996 996 + "MetricExpr": "(UNC_ARB_TRK_OCCUPANCY.RD + UNC_ARB_DAT_OCCUPANCY.RD) / UNC_ARB_TRK_REQUESTS.RD", 997 997 + "MetricGroup": "Mem;MemoryLat;SoC", 998 998 + "MetricName": "tma_info_system_mem_read_latency", 999 999 + "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)" 1000 1000 + }, 1001 1001 + { 1002 1002 + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", 1003 1003 + "MetricExpr": "(UNC_ARB_TRK_OCCUPANCY.ALL + UNC_ARB_DAT_OCCUPANCY.RD) / UNC_ARB_TRK_REQUESTS.ALL", 1004 1004 + "MetricGroup": "Mem;SoC", 1005 1005 + "MetricName": "tma_info_system_mem_request_latency" 1006 1006 + }, 1007 1007 + { 1008 1008 + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", 1009 1009 + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / tma_info_core_core_clks", 1010 1010 + "MetricGroup": "Power", 1011 1011 + "MetricName": "tma_info_system_power_license0_utilization", 1012 1012 + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." 1013 1013 + }, 1014 1014 + { 1015 1015 + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", 1016 1016 + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_core_clks", 1017 1017 + "MetricGroup": "Power", 1018 1018 + "MetricName": "tma_info_system_power_license1_utilization", 1019 1019 + "MetricThreshold": "tma_info_system_power_license1_utilization > 0.5", 1020 1020 + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." 1021 1021 + }, 1022 1022 + { 1023 1023 + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", 1024 1024 + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_core_clks", 1025 1025 + "MetricGroup": "Power", 1026 1026 + "MetricName": "tma_info_system_power_license2_utilization", 1027 1027 + "MetricThreshold": "tma_info_system_power_license2_utilization > 0.5", 1028 1028 + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." 1029 1029 + }, 1030 1030 + { 1031 1031 + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", 1032 1032 + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)", 1033 1033 + "MetricGroup": "SMT", 1034 1034 + "MetricName": "tma_info_system_smt_2t_utilization" 1035 1035 + }, 1036 1036 + { 1037 1037 + "BriefDescription": "Socket actual clocks when any core is active on that socket", 1038 1038 + "MetricExpr": "UNC_CLOCK.SOCKET", 1039 1039 + "MetricGroup": "SoC", 1040 1040 + "MetricName": "tma_info_system_socket_clks" 1041 1041 + }, 1042 1042 + { 1043 1043 + "BriefDescription": "Average Frequency Utilization relative nominal frequency", 1044 1044 + "MetricExpr": "tma_info_thread_clks / CPU_CLK_UNHALTED.REF_TSC", 1045 1045 + "MetricGroup": "Power", 1046 1046 + "MetricName": "tma_info_system_turbo_utilization" 1047 1047 + }, 1048 1048 + { 1049 1049 + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", 1050 1050 + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", 1051 1051 + "MetricGroup": "Pipeline", 1052 1052 + "MetricName": "tma_info_thread_clks" 1053 1053 + }, 1054 1054 + { 1055 1055 + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", 1056 1056 + "MetricExpr": "1 / tma_info_thread_ipc", 1057 1057 + "MetricGroup": "Mem;Pipeline", 1058 1058 + "MetricName": "tma_info_thread_cpi" 1059 1059 + }, 1060 1060 + { 1061 1061 + "BriefDescription": "The ratio of Executed- by Issued-Uops", 1062 1062 + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", 1063 1063 + "MetricGroup": "Cor;Pipeline", 1064 1064 + "MetricName": "tma_info_thread_execute_per_issue", 1065 1065 + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." 1066 1066 + }, 1067 1067 + { 1068 1068 + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", 1069 1069 + "MetricExpr": "INST_RETIRED.ANY / tma_info_thread_clks", 1070 1070 + "MetricGroup": "Ret;Summary", 1071 1071 + "MetricName": "tma_info_thread_ipc" 1072 1072 + }, 1073 1073 + { 1074 1074 + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", 1075 1075 + "MetricExpr": "TOPDOWN.SLOTS", 1076 1076 + "MetricGroup": "TmaL1;tma_L1_group", 1077 1077 + "MetricName": "tma_info_thread_slots" 1078 1078 + }, 1079 1079 + { 1080 1080 + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", 1081 1081 + "MetricExpr": "(tma_info_thread_slots / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)", 1082 1082 + "MetricGroup": "SMT;TmaL1;tma_L1_group", 1083 1083 + "MetricName": "tma_info_thread_slots_utilization" 1084 1084 + }, 1085 1085 + { 1086 1086 + "BriefDescription": "Uops Per Instruction", 1087 1087 + "MetricExpr": "tma_retiring * tma_info_thread_slots / INST_RETIRED.ANY", 1088 1088 + "MetricGroup": "Pipeline;Ret;Retire", 1089 1089 + "MetricName": "tma_info_thread_uoppi", 1090 1090 + "MetricThreshold": "tma_info_thread_uoppi > 1.05" 1091 1091 + }, 1092 1092 + { 1093 1093 + "BriefDescription": "Instruction per taken branch", 1094 1094 + "MetricExpr": "tma_retiring * tma_info_thread_slots / BR_INST_RETIRED.NEAR_TAKEN", 1095 1095 + "MetricGroup": "Branches;Fed;FetchBW", 1096 1096 + "MetricName": "tma_info_thread_uptb", 1097 1097 + "MetricThreshold": "tma_info_thread_uptb < 7.5" 1098 1098 + }, 1099 1099 + { 1100 1100 + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", 1101 1101 + "MetricExpr": "ICACHE_64B.IFTAG_STALL / tma_info_thread_clks", 1102 1102 + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", 1103 1103 + "MetricName": "tma_itlb_misses", 1104 1104 + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", 1105 1105 + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", 1106 1106 + "ScaleUnit": "100%" 1107 1107 + }, 1108 1108 + { 1109 1109 + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", 1110 1110 + "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_thread_clks, 0)", 1111 1111 + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", 1112 1112 + "MetricName": "tma_l1_bound", 1113 1113 + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", 1114 1114 + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", 1115 1115 + "ScaleUnit": "100%" 1116 1116 + }, 1117 1117 + { 1118 1118 + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", 1119 1119 + "MetricConstraint": "NO_GROUP_EVENTS", 1120 1120 + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_thread_clks)", 1121 1121 + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", 1122 1122 + "MetricName": "tma_l2_bound", 1123 1123 + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", 1124 1124 + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", 1125 1125 + "ScaleUnit": "100%" 1126 1126 + }, 1127 1127 + { 1128 1128 + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", 1129 1129 + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_thread_clks", 1130 1130 + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", 1131 1131 + "MetricName": "tma_l3_bound", 1132 1132 + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", 1133 1133 + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", 1134 1134 + "ScaleUnit": "100%" 1135 1135 + }, 1136 1136 + { 1137 1137 + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", 1138 1138 + "MetricExpr": "9 * tma_info_system_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks", 1139 1139 + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", 1140 1140 + "MetricName": "tma_l3_hit_latency", 1141 1141 + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 1142 1142 + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_bottleneck_memory_latency, tma_mem_latency", 1143 1143 + "ScaleUnit": "100%" 1144 1144 + }, 1145 1145 + { 1146 1146 + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", 1147 1147 + "MetricExpr": "ILD_STALL.LCP / tma_info_thread_clks", 1148 1148 + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", 1149 1149 + "MetricName": "tma_lcp", 1150 1150 + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", 1151 1151 + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", 1152 1152 + "ScaleUnit": "100%" 1153 1153 + }, 1154 1154 + { 1155 1155 + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", 1156 1156 + "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)", 1157 1157 + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", 1158 1158 + "MetricName": "tma_light_operations", 1159 1159 + "MetricThreshold": "tma_light_operations > 0.6", 1160 1160 + "MetricgroupNoGroup": "TopdownL2", 1161 1161 + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", 1162 1162 + "ScaleUnit": "100%" 1163 1163 + }, 1164 1164 + { 1165 1165 + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", 1166 1166 + "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * tma_info_core_core_clks)", 1167 1167 + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", 1168 1168 + "MetricName": "tma_load_op_utilization", 1169 1169 + "MetricThreshold": "tma_load_op_utilization > 0.6", 1170 1170 + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", 1171 1171 + "ScaleUnit": "100%" 1172 1172 + }, 1173 1173 + { 1174 1174 + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", 1175 1175 + "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", 1176 1176 + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", 1177 1177 + "MetricName": "tma_load_stlb_hit", 1178 1178 + "MetricThreshold": "tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", 1179 1179 + "ScaleUnit": "100%" 1180 1180 + }, 1181 1181 + { 1182 1182 + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", 1183 1183 + "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_thread_clks", 1184 1184 + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", 1185 1185 + "MetricName": "tma_load_stlb_miss", 1186 1186 + "MetricThreshold": "tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", 1187 1187 + "ScaleUnit": "100%" 1188 1188 + }, 1189 1189 + { 1190 1190 + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", 1191 1191 + "MetricConstraint": "NO_GROUP_EVENTS", 1192 1192 + "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks", 1193 1193 + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", 1194 1194 + "MetricName": "tma_lock_latency", 1195 1195 + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 1196 1196 + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", 1197 1197 + "ScaleUnit": "100%" 1198 1198 + }, 1199 1199 + { 1200 1200 + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit", 1201 1201 + "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / tma_info_core_core_clks / 2", 1202 1202 + "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", 1203 1203 + "MetricName": "tma_lsd", 1204 1204 + "MetricThreshold": "tma_lsd > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 5 > 0.35)", 1205 1205 + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure.", 1206 1206 + "ScaleUnit": "100%" 1207 1207 + }, 1208 1208 + { 1209 1209 + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", 1210 1210 + "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)", 1211 1211 + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", 1212 1212 + "MetricName": "tma_machine_clears", 1213 1213 + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", 1214 1214 + "MetricgroupNoGroup": "TopdownL2", 1215 1215 + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", 1216 1216 + "ScaleUnit": "100%" 1217 1217 + }, 1218 1218 + { 1219 1219 + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", 1220 1220 + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_thread_clks", 1221 1221 + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", 1222 1222 + "MetricName": "tma_mem_bandwidth", 1223 1223 + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 1224 1224 + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full", 1225 1225 + "ScaleUnit": "100%" 1226 1226 + }, 1227 1227 + { 1228 1228 + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", 1229 1229 + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", 1230 1230 + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", 1231 1231 + "MetricName": "tma_mem_latency", 1232 1232 + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 1233 1233 + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_bottleneck_memory_latency, tma_l3_hit_latency", 1234 1234 + "ScaleUnit": "100%" 1235 1235 + }, 1236 1236 + { 1237 1237 + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", 1238 1238 + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", 1239 1239 + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", 1240 1240 + "MetricName": "tma_memory_bound", 1241 1241 + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", 1242 1242 + "MetricgroupNoGroup": "TopdownL2", 1243 1243 + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", 1244 1244 + "ScaleUnit": "100%" 1245 1245 + }, 1246 1246 + { 1247 1247 + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", 1248 1248 + "MetricConstraint": "NO_GROUP_EVENTS", 1249 1249 + "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", 1250 1250 + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", 1251 1251 + "MetricName": "tma_memory_operations", 1252 1252 + "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operations > 0.6", 1253 1253 + "ScaleUnit": "100%" 1254 1254 + }, 1255 1255 + { 1256 1256 + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", 1257 1257 + "MetricExpr": "tma_retiring * tma_info_thread_slots / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_thread_slots", 1258 1258 + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", 1259 1259 + "MetricName": "tma_microcode_sequencer", 1260 1260 + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", 1261 1261 + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", 1262 1262 + "ScaleUnit": "100%" 1263 1263 + }, 1264 1264 + { 1265 1265 + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", 1266 1266 + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks", 1267 1267 + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", 1268 1268 + "MetricName": "tma_mispredicts_resteers", 1269 1269 + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", 1270 1270 + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredictions", 1271 1271 + "ScaleUnit": "100%" 1272 1272 + }, 1273 1273 + { 1274 1274 + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", 1275 1275 + "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_core_clks / 2", 1276 1276 + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", 1277 1277 + "MetricName": "tma_mite", 1278 1278 + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 5 > 0.35)", 1279 1279 + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", 1280 1280 + "ScaleUnit": "100%" 1281 1281 + }, 1282 1282 + { 1283 1283 + "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline", 1284 1284 + "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / tma_info_thread_clks", 1285 1285 + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", 1286 1286 + "MetricName": "tma_mite_4wide", 1287 1287 + "MetricThreshold": "tma_mite_4wide > 0.05 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_thread_ipc / 5 > 0.35))", 1288 1288 + "ScaleUnit": "100%" 1289 1289 + }, 1290 1290 + { 1291 1291 + "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", 1292 1292 + "MetricExpr": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY", 1293 1293 + "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group", 1294 1294 + "MetricName": "tma_mixing_vectors", 1295 1295 + "MetricThreshold": "tma_mixing_vectors > 0.05", 1296 1296 + "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches", 1297 1297 + "ScaleUnit": "100%" 1298 1298 + }, 1299 1299 + { 1300 1300 + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", 1301 1301 + "MetricExpr": "3 * IDQ.MS_SWITCHES / tma_info_thread_clks", 1302 1302 + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", 1303 1303 + "MetricName": "tma_ms_switches", 1304 1304 + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", 1305 1305 + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", 1306 1306 + "ScaleUnit": "100%" 1307 1307 + }, 1308 1308 + { 1309 1309 + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", 1310 1310 + "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * tma_info_thread_slots)", 1311 1311 + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", 1312 1312 + "MetricName": "tma_nop_instructions", 1313 1313 + "MetricThreshold": "tma_nop_instructions > 0.1 & tma_light_operations > 0.6", 1314 1314 + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", 1315 1315 + "ScaleUnit": "100%" 1316 1316 + }, 1317 1317 + { 1318 1318 + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes", 1319 1319 + "MetricConstraint": "NO_GROUP_EVENTS", 1320 1320 + "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))", 1321 1321 + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", 1322 1322 + "MetricName": "tma_other_light_ops", 1323 1323 + "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operations > 0.6", 1324 1324 + "PublicDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", 1325 1325 + "ScaleUnit": "100%" 1326 1326 + }, 1327 1327 + { 1328 1328 + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", 1329 1329 + "MetricExpr": "UOPS_DISPATCHED.PORT_0 / tma_info_core_core_clks", 1330 1330 + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", 1331 1331 + "MetricName": "tma_port_0", 1332 1332 + "MetricThreshold": "tma_port_0 > 0.6", 1333 1333 + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", 1334 1334 + "ScaleUnit": "100%" 1335 1335 + }, 1336 1336 + { 1337 1337 + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", 1338 1338 + "MetricExpr": "UOPS_DISPATCHED.PORT_1 / tma_info_core_core_clks", 1339 1339 + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", 1340 1340 + "MetricName": "tma_port_1", 1341 1341 + "MetricThreshold": "tma_port_1 > 0.6", 1342 1342 + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", 1343 1343 + "ScaleUnit": "100%" 1344 1344 + }, 1345 1345 + { 1346 1346 + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", 1347 1347 + "MetricExpr": "UOPS_DISPATCHED.PORT_5 / tma_info_core_core_clks", 1348 1348 + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", 1349 1349 + "MetricName": "tma_port_5", 1350 1350 + "MetricThreshold": "tma_port_5 > 0.6", 1351 1351 + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", 1352 1352 + "ScaleUnit": "100%" 1353 1353 + }, 1354 1354 + { 1355 1355 + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", 1356 1356 + "MetricExpr": "UOPS_DISPATCHED.PORT_6 / tma_info_core_core_clks", 1357 1357 + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", 1358 1358 + "MetricName": "tma_port_6", 1359 1359 + "MetricThreshold": "tma_port_6 > 0.6", 1360 1360 + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", 1361 1361 + "ScaleUnit": "100%" 1362 1362 + }, 1363 1363 + { 1364 1364 + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", 1365 1365 + "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / tma_info_thread_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_thread_clks)", 1366 1366 + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", 1367 1367 + "MetricName": "tma_ports_utilization", 1368 1368 + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", 1369 1369 + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", 1370 1370 + "ScaleUnit": "100%" 1371 1371 + }, 1372 1372 + { 1373 1373 + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", 1374 1374 + "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / tma_info_thread_clks + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks", 1375 1375 + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", 1376 1376 + "MetricName": "tma_ports_utilized_0", 1377 1377 + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", 1378 1378 + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", 1379 1379 + "ScaleUnit": "100%" 1380 1380 + }, 1381 1381 + { 1382 1382 + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", 1383 1383 + "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / tma_info_thread_clks", 1384 1384 + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", 1385 1385 + "MetricName": "tma_ports_utilized_1", 1386 1386 + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", 1387 1387 + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound", 1388 1388 + "ScaleUnit": "100%" 1389 1389 + }, 1390 1390 + { 1391 1391 + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", 1392 1392 + "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / tma_info_thread_clks", 1393 1393 + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", 1394 1394 + "MetricName": "tma_ports_utilized_2", 1395 1395 + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", 1396 1396 + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", 1397 1397 + "ScaleUnit": "100%" 1398 1398 + }, 1399 1399 + { 1400 1400 + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", 1401 1401 + "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks", 1402 1402 + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", 1403 1403 + "MetricName": "tma_ports_utilized_3m", 1404 1404 + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", 1405 1405 + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3", 1406 1406 + "ScaleUnit": "100%" 1407 1407 + }, 1408 1408 + { 1409 1409 + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", 1410 1410 + "DefaultMetricgroupName": "TopdownL1", 1411 1411 + "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_thread_slots", 1412 1412 + "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", 1413 1413 + "MetricName": "tma_retiring", 1414 1414 + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", 1415 1415 + "MetricgroupNoGroup": "TopdownL1;Default", 1416 1416 + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", 1417 1417 + "ScaleUnit": "100%" 1418 1418 + }, 1419 1419 + { 1420 1420 + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", 1421 1421 + "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks", 1422 1422 + "MetricGroup": "PortsUtil;TopdownL5;tma_L5_group;tma_issueSO;tma_ports_utilized_0_group", 1423 1423 + "MetricName": "tma_serializing_operation", 1424 1424 + "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))", 1425 1425 + "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches", 1426 1426 + "ScaleUnit": "100%" 1427 1427 + }, 1428 1428 + { 1429 1429 + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions", 1430 1430 + "MetricExpr": "140 * MISC_RETIRED.PAUSE_INST / tma_info_thread_clks", 1431 1431 + "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", 1432 1432 + "MetricName": "tma_slow_pause", 1433 1433 + "MetricThreshold": "tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))))", 1434 1434 + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST", 1435 1435 + "ScaleUnit": "100%" 1436 1436 + }, 1437 1437 + { 1438 1438 + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", 1439 1439 + "MetricExpr": "tma_info_memory_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_thread_clks", 1440 1440 + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", 1441 1441 + "MetricName": "tma_split_loads", 1442 1442 + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 1443 1443 + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", 1444 1444 + "ScaleUnit": "100%" 1445 1445 + }, 1446 1446 + { 1447 1447 + "BriefDescription": "This metric represents rate of split store accesses", 1448 1448 + "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_core_clks", 1449 1449 + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", 1450 1450 + "MetricName": "tma_split_stores", 1451 1451 + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 1452 1452 + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", 1453 1453 + "ScaleUnit": "100%" 1454 1454 + }, 1455 1455 + { 1456 1456 + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", 1457 1457 + "MetricExpr": "L1D_PEND_MISS.L2_STALL / tma_info_thread_clks", 1458 1458 + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", 1459 1459 + "MetricName": "tma_sq_full", 1460 1460 + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 1461 1461 + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_bottleneck_memory_bandwidth, tma_info_system_dram_bw_use, tma_mem_bandwidth", 1462 1462 + "ScaleUnit": "100%" 1463 1463 + }, 1464 1464 + { 1465 1465 + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", 1466 1466 + "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / tma_info_thread_clks", 1467 1467 + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", 1468 1468 + "MetricName": "tma_store_bound", 1469 1469 + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", 1470 1470 + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", 1471 1471 + "ScaleUnit": "100%" 1472 1472 + }, 1473 1473 + { 1474 1474 + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", 1475 1475 + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_thread_clks", 1476 1476 + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", 1477 1477 + "MetricName": "tma_store_fwd_blk", 1478 1478 + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 1479 1479 + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", 1480 1480 + "ScaleUnit": "100%" 1481 1481 + }, 1482 1482 + { 1483 1483 + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", 1484 1484 + "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", 1485 1485 + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", 1486 1486 + "MetricName": "tma_store_latency", 1487 1487 + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 1488 1488 + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", 1489 1489 + "ScaleUnit": "100%" 1490 1490 + }, 1491 1491 + { 1492 1492 + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", 1493 1493 + "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * tma_info_core_core_clks)", 1494 1494 + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", 1495 1495 + "MetricName": "tma_store_op_utilization", 1496 1496 + "MetricThreshold": "tma_store_op_utilization > 0.6", 1497 1497 + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8", 1498 1498 + "ScaleUnit": "100%" 1499 1499 + }, 1500 1500 + { 1501 1501 + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", 1502 1502 + "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", 1503 1503 + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", 1504 1504 + "MetricName": "tma_store_stlb_hit", 1505 1505 + "MetricThreshold": "tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", 1506 1506 + "ScaleUnit": "100%" 1507 1507 + }, 1508 1508 + { 1509 1509 + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", 1510 1510 + "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_core_clks", 1511 1511 + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", 1512 1512 + "MetricName": "tma_store_stlb_miss", 1513 1513 + "MetricThreshold": "tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", 1514 1514 + "ScaleUnit": "100%" 1515 1515 + }, 1516 1516 + { 1517 1517 + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores", 1518 1518 + "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_thread_clks", 1519 1519 + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group", 1520 1520 + "MetricName": "tma_streaming_stores", 1521 1521 + "MetricThreshold": "tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", 1522 1522 + "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full", 1523 1523 + "ScaleUnit": "100%" 1524 1524 + }, 1525 1525 + { 1526 1526 + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", 1527 1527 + "MetricExpr": "10 * BACLEARS.ANY / tma_info_thread_clks", 1528 1528 + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", 1529 1529 + "MetricName": "tma_unknown_branches", 1530 1530 + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", 1531 1531 + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: BACLEARS.ANY", 1532 1532 + "ScaleUnit": "100%" 1533 1533 + }, 1534 1534 + { 1535 1535 + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", 1536 1536 + "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", 1537 1537 + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", 1538 1538 + "MetricName": "tma_x87_use", 1539 1539 + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", 1540 1540 + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", 1541 1541 + "ScaleUnit": "100%" 1542 1542 + }, 1543 1543 + { 1544 1544 + "BriefDescription": "Percentage of cycles in aborted transactions.", 1545 1545 + "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)", 1546 1546 + "MetricGroup": "transaction", 1547 1547 + "MetricName": "tsx_aborted_cycles", 1548 1548 + "ScaleUnit": "100%" 1549 1549 + }, 1550 1550 + { 1551 1551 + "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", 1552 1552 + "MetricExpr": "(cycles\\-t / el\\-start if has_event(cycles\\-t) else 0)", 1553 1553 + "MetricGroup": "transaction", 1554 1554 + "MetricName": "tsx_cycles_per_elision", 1555 1555 + "ScaleUnit": "1cycles / elision" 1556 1556 + }, 1557 1557 + { 1558 1558 + "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", 1559 1559 + "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)", 1560 1560 + "MetricGroup": "transaction", 1561 1561 + "MetricName": "tsx_cycles_per_transaction", 1562 1562 + "ScaleUnit": "1cycles / transaction" 1563 1563 + }, 1564 1564 + { 1565 1565 + "BriefDescription": "Percentage of cycles within a transaction region.", 1566 1566 + "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)", 1567 1567 + "MetricGroup": "transaction", 1568 1568 + "MetricName": "tsx_transactional_cycles", 1569 1569 + "ScaleUnit": "100%" 1570 1570 + } 1571 1571 + ]

+74

tools/perf/pmu-events/arch/x86/rocketlake/uncore-interconnect.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, etc.", 4 4 + "EventCode": "0x84", 5 5 + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", 6 6 + "PerPkg": "1", 7 7 + "UMask": "0x1", 8 8 + "Unit": "ARB" 9 9 + }, 10 10 + { 11 11 + "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products.", 12 12 + "EventCode": "0x85", 13 13 + "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", 14 14 + "PerPkg": "1", 15 15 + "UMask": "0x1", 16 16 + "Unit": "ARB" 17 17 + }, 18 18 + { 19 19 + "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products.", 20 20 + "EventCode": "0x85", 21 21 + "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", 22 22 + "PerPkg": "1", 23 23 + "UMask": "0x2", 24 24 + "Unit": "ARB" 25 25 + }, 26 26 + { 27 27 + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.", 28 28 + "EventCode": "0x80", 29 29 + "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", 30 30 + "PerPkg": "1", 31 31 + "UMask": "0x2", 32 32 + "Unit": "ARB" 33 33 + }, 34 34 + { 35 35 + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches", 36 36 + "EventCode": "0x81", 37 37 + "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", 38 38 + "PerPkg": "1", 39 39 + "UMask": "0x2", 40 40 + "Unit": "ARB" 41 41 + }, 42 42 + { 43 43 + "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. This event is not supported on ICL products but is supported on RKL products.", 44 44 + "EventCode": "0x80", 45 45 + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", 46 46 + "PerPkg": "1", 47 47 + "UMask": "0x1", 48 48 + "Unit": "ARB" 49 49 + }, 50 50 + { 51 51 + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.", 52 52 + "EventCode": "0x80", 53 53 + "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", 54 54 + "PerPkg": "1", 55 55 + "UMask": "0x2", 56 56 + "Unit": "ARB" 57 57 + }, 58 58 + { 59 59 + "BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", 60 60 + "EventCode": "0x81", 61 61 + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", 62 62 + "PerPkg": "1", 63 63 + "UMask": "0x1", 64 64 + "Unit": "ARB" 65 65 + }, 66 66 + { 67 67 + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.", 68 68 + "EventCode": "0x81", 69 69 + "EventName": "UNC_ARB_TRK_REQUESTS.RD", 70 70 + "PerPkg": "1", 71 71 + "UMask": "0x2", 72 72 + "Unit": "ARB" 73 73 + } 74 74 + ]

+9

tools/perf/pmu-events/arch/x86/rocketlake/uncore-other.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "UNC_CLOCK.SOCKET", 4 4 + "EventCode": "0xff", 5 5 + "EventName": "UNC_CLOCK.SOCKET", 6 6 + "PerPkg": "1", 7 7 + "Unit": "CLOCK" 8 8 + } 9 9 + ]

+165

tools/perf/pmu-events/arch/x86/rocketlake/virtual-memory.json

reviewed

··· 1 1 + [ 2 2 + { 3 3 + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", 4 4 + "EventCode": "0x08", 5 5 + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", 6 6 + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", 7 7 + "SampleAfterValue": "100003", 8 8 + "UMask": "0x20" 9 9 + }, 10 10 + { 11 11 + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", 12 12 + "CounterMask": "1", 13 13 + "EventCode": "0x08", 14 14 + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", 15 15 + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.", 16 16 + "SampleAfterValue": "100003", 17 17 + "UMask": "0x10" 18 18 + }, 19 19 + { 20 20 + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", 21 21 + "EventCode": "0x08", 22 22 + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", 23 23 + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 24 24 + "SampleAfterValue": "100003", 25 25 + "UMask": "0xe" 26 26 + }, 27 27 + { 28 28 + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", 29 29 + "EventCode": "0x08", 30 30 + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 31 31 + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 32 32 + "SampleAfterValue": "100003", 33 33 + "UMask": "0x4" 34 34 + }, 35 35 + { 36 36 + "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", 37 37 + "EventCode": "0x08", 38 38 + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 39 39 + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 40 40 + "SampleAfterValue": "100003", 41 41 + "UMask": "0x2" 42 42 + }, 43 43 + { 44 44 + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", 45 45 + "EventCode": "0x08", 46 46 + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", 47 47 + "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", 48 48 + "SampleAfterValue": "100003", 49 49 + "UMask": "0x10" 50 50 + }, 51 51 + { 52 52 + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", 53 53 + "EventCode": "0x49", 54 54 + "EventName": "DTLB_STORE_MISSES.STLB_HIT", 55 55 + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", 56 56 + "SampleAfterValue": "100003", 57 57 + "UMask": "0x20" 58 58 + }, 59 59 + { 60 60 + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", 61 61 + "CounterMask": "1", 62 62 + "EventCode": "0x49", 63 63 + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", 64 64 + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", 65 65 + "SampleAfterValue": "100003", 66 66 + "UMask": "0x10" 67 67 + }, 68 68 + { 69 69 + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", 70 70 + "EventCode": "0x49", 71 71 + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", 72 72 + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 73 73 + "SampleAfterValue": "100003", 74 74 + "UMask": "0xe" 75 75 + }, 76 76 + { 77 77 + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", 78 78 + "EventCode": "0x49", 79 79 + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 80 80 + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 81 81 + "SampleAfterValue": "100003", 82 82 + "UMask": "0x4" 83 83 + }, 84 84 + { 85 85 + "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", 86 86 + "EventCode": "0x49", 87 87 + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 88 88 + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", 89 89 + "SampleAfterValue": "100003", 90 90 + "UMask": "0x2" 91 91 + }, 92 92 + { 93 93 + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", 94 94 + "EventCode": "0x49", 95 95 + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", 96 96 + "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", 97 97 + "SampleAfterValue": "100003", 98 98 + "UMask": "0x10" 99 99 + }, 100 100 + { 101 101 + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", 102 102 + "EventCode": "0x85", 103 103 + "EventName": "ITLB_MISSES.STLB_HIT", 104 104 + "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", 105 105 + "SampleAfterValue": "100003", 106 106 + "UMask": "0x20" 107 107 + }, 108 108 + { 109 109 + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", 110 110 + "CounterMask": "1", 111 111 + "EventCode": "0x85", 112 112 + "EventName": "ITLB_MISSES.WALK_ACTIVE", 113 113 + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", 114 114 + "SampleAfterValue": "100003", 115 115 + "UMask": "0x10" 116 116 + }, 117 117 + { 118 118 + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", 119 119 + "EventCode": "0x85", 120 120 + "EventName": "ITLB_MISSES.WALK_COMPLETED", 121 121 + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", 122 122 + "SampleAfterValue": "100003", 123 123 + "UMask": "0xe" 124 124 + }, 125 125 + { 126 126 + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", 127 127 + "EventCode": "0x85", 128 128 + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", 129 129 + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", 130 130 + "SampleAfterValue": "100003", 131 131 + "UMask": "0x4" 132 132 + }, 133 133 + { 134 134 + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", 135 135 + "EventCode": "0x85", 136 136 + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", 137 137 + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", 138 138 + "SampleAfterValue": "100003", 139 139 + "UMask": "0x2" 140 140 + }, 141 141 + { 142 142 + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", 143 143 + "EventCode": "0x85", 144 144 + "EventName": "ITLB_MISSES.WALK_PENDING", 145 145 + "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", 146 146 + "SampleAfterValue": "100003", 147 147 + "UMask": "0x10" 148 148 + }, 149 149 + { 150 150 + "BriefDescription": "DTLB flush attempts of the thread-specific entries", 151 151 + "EventCode": "0xBD", 152 152 + "EventName": "TLB_FLUSH.DTLB_THREAD", 153 153 + "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", 154 154 + "SampleAfterValue": "100007", 155 155 + "UMask": "0x1" 156 156 + }, 157 157 + { 158 158 + "BriefDescription": "STLB flush attempts", 159 159 + "EventCode": "0xBD", 160 160 + "EventName": "TLB_FLUSH.STLB_ANY", 161 161 + "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", 162 162 + "SampleAfterValue": "100007", 163 163 + "UMask": "0x20" 164 164 + } 165 165 + ]

+1 -1

tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json

reviewed

··· 706 706 "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", 707 707 "EventCode": "0xa4", 708 708 "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", 709 709 - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of specualtive operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.", 709 709 + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.", 710 710 "SampleAfterValue": "10000003", 711 711 "UMask": "0x8" 712 712 },

+4 -4

tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json

reviewed

··· 1938 1938 }, 1939 1939 { 1940 1940 "BriefDescription": "Percentage of cycles in aborted transactions.", 1941 1941 - "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", 1941 1941 + "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)", 1942 1942 "MetricGroup": "transaction", 1943 1943 "MetricName": "tsx_aborted_cycles", 1944 1944 "ScaleUnit": "100%" 1945 1945 }, 1946 1946 { 1947 1947 "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", 1948 1948 - "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", 1948 1948 + "MetricExpr": "(cycles\\-t / el\\-start if has_event(cycles\\-t) else 0)", 1949 1949 "MetricGroup": "transaction", 1950 1950 "MetricName": "tsx_cycles_per_elision", 1951 1951 "ScaleUnit": "1cycles / elision" 1952 1952 }, 1953 1953 { 1954 1954 "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", 1955 1955 - "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", 1955 1955 + "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)", 1956 1956 "MetricGroup": "transaction", 1957 1957 "MetricName": "tsx_cycles_per_transaction", 1958 1958 "ScaleUnit": "1cycles / transaction" 1959 1959 }, 1960 1960 { 1961 1961 "BriefDescription": "Percentage of cycles within a transaction region.", 1962 1962 - "MetricExpr": "cpu@cycles\\-t@ / cycles", 1962 1962 + "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)", 1963 1963 "MetricGroup": "transaction", 1964 1964 "MetricName": "tsx_transactional_cycles", 1965 1965 "ScaleUnit": "100%"

+308

tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json

reviewed

··· 3157 3157 "Unit": "CHA" 3158 3158 }, 3159 3159 { 3160 3160 + "BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", 3161 3161 + "EventCode": "0x35", 3162 3162 + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC", 3163 3163 + "PerPkg": "1", 3164 3164 + "UMask": "0x10c0018101", 3165 3165 + "Unit": "CHA" 3166 3166 + }, 3167 3167 + { 3168 3168 + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL", 3169 3169 + "EventCode": "0x35", 3170 3170 + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL", 3171 3171 + "PerPkg": "1", 3172 3172 + "PortMask": "0x000", 3173 3173 + "UMask": "0x10c0008101", 3174 3174 + "Unit": "CHA" 3175 3175 + }, 3176 3176 + { 3160 3177 "BriefDescription": "TOR Inserts; DRd hits from local IA", 3161 3178 "EventCode": "0x35", 3162 3179 "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", ··· 3389 3372 "Unit": "CHA" 3390 3373 }, 3391 3374 { 3375 3375 + "BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", 3376 3376 + "EventCode": "0x35", 3377 3377 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC", 3378 3378 + "PerPkg": "1", 3379 3379 + "UMask": "0x10c0018201", 3380 3380 + "Unit": "CHA" 3381 3381 + }, 3382 3382 + { 3383 3383 + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC_LOCAL", 3384 3384 + "EventCode": "0x35", 3385 3385 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC_LOCAL", 3386 3386 + "PerPkg": "1", 3387 3387 + "PortMask": "0x000", 3388 3388 + "UMask": "0x10c0008201", 3389 3389 + "Unit": "CHA" 3390 3390 + }, 3391 3391 + { 3392 3392 "BriefDescription": "TOR Inserts for DRd misses from local IA", 3393 3393 "EventCode": "0x35", 3394 3394 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", ··· 3429 3395 "PerPkg": "1", 3430 3396 "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", 3431 3397 "UMask": "0xc837fe01", 3398 3398 + "Unit": "CHA" 3399 3399 + }, 3400 3400 + { 3401 3401 + "BriefDescription": "DRds issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", 3402 3402 + "EventCode": "0x35", 3403 3403 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC", 3404 3404 + "PerPkg": "1", 3405 3405 + "UMask": "0x10c8178201", 3406 3406 + "Unit": "CHA" 3407 3407 + }, 3408 3408 + { 3409 3409 + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC_LOCAL", 3410 3410 + "EventCode": "0x35", 3411 3411 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC_LOCAL", 3412 3412 + "PerPkg": "1", 3413 3413 + "PortMask": "0x000", 3414 3414 + "UMask": "0x10c8168201", 3432 3415 "Unit": "CHA" 3433 3416 }, 3434 3417 { ··· 3494 3443 "Unit": "CHA" 3495 3444 }, 3496 3445 { 3446 3446 + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_CXL_ACC_LOCAL", 3447 3447 + "EventCode": "0x35", 3448 3448 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_CXL_ACC_LOCAL", 3449 3449 + "PerPkg": "1", 3450 3450 + "PortMask": "0x000", 3451 3451 + "UMask": "0x10c8268201", 3452 3452 + "Unit": "CHA" 3453 3453 + }, 3454 3454 + { 3497 3455 "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local IA", 3498 3456 "EventCode": "0x35", 3499 3457 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", 3500 3458 "PerPkg": "1", 3501 3459 "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter", 3502 3460 "UMask": "0xc8a7fe01", 3461 3461 + "Unit": "CHA" 3462 3462 + }, 3463 3463 + { 3464 3464 + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL", 3465 3465 + "EventCode": "0x35", 3466 3466 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL", 3467 3467 + "PerPkg": "1", 3468 3468 + "PortMask": "0x000", 3469 3469 + "UMask": "0x10c8a68201", 3503 3470 "Unit": "CHA" 3504 3471 }, 3505 3472 { ··· 3536 3467 "PerPkg": "1", 3537 3468 "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF", 3538 3469 "UMask": "0xc897fe01", 3470 3470 + "Unit": "CHA" 3471 3471 + }, 3472 3472 + { 3473 3473 + "BriefDescription": "L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", 3474 3474 + "EventCode": "0x35", 3475 3475 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC", 3476 3476 + "PerPkg": "1", 3477 3477 + "UMask": "0x10c8978201", 3478 3478 + "Unit": "CHA" 3479 3479 + }, 3480 3480 + { 3481 3481 + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC_LOCAL", 3482 3482 + "EventCode": "0x35", 3483 3483 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC_LOCAL", 3484 3484 + "PerPkg": "1", 3485 3485 + "PortMask": "0x000", 3486 3486 + "UMask": "0x10c8968201", 3539 3487 "Unit": "CHA" 3540 3488 }, 3541 3489 { ··· 3690 3604 "Unit": "CHA" 3691 3605 }, 3692 3606 { 3607 3607 + "BriefDescription": "LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", 3608 3608 + "EventCode": "0x35", 3609 3609 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC", 3610 3610 + "PerPkg": "1", 3611 3611 + "UMask": "0x10ccd78201", 3612 3612 + "Unit": "CHA" 3613 3613 + }, 3614 3614 + { 3615 3615 + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL", 3616 3616 + "EventCode": "0x35", 3617 3617 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL", 3618 3618 + "PerPkg": "1", 3619 3619 + "PortMask": "0x000", 3620 3620 + "UMask": "0x10ccd68201", 3621 3621 + "Unit": "CHA" 3622 3622 + }, 3623 3623 + { 3693 3624 "BriefDescription": "TOR Inserts; LLCPrefRFO misses from local IA", 3694 3625 "EventCode": "0x35", 3695 3626 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", 3696 3627 "PerPkg": "1", 3697 3628 "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", 3698 3629 "UMask": "0xccc7fe01", 3630 3630 + "Unit": "CHA" 3631 3631 + }, 3632 3632 + { 3633 3633 + "BriefDescription": "L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", 3634 3634 + "EventCode": "0x35", 3635 3635 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC", 3636 3636 + "PerPkg": "1", 3637 3637 + "UMask": "0x10c8878201", 3638 3638 + "Unit": "CHA" 3639 3639 + }, 3640 3640 + { 3641 3641 + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL", 3642 3642 + "EventCode": "0x35", 3643 3643 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL", 3644 3644 + "PerPkg": "1", 3645 3645 + "PortMask": "0x000", 3646 3646 + "UMask": "0x10c8868201", 3699 3647 "Unit": "CHA" 3700 3648 }, 3701 3649 { ··· 3822 3702 "Unit": "CHA" 3823 3703 }, 3824 3704 { 3705 3705 + "BriefDescription": "RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", 3706 3706 + "EventCode": "0x35", 3707 3707 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC", 3708 3708 + "PerPkg": "1", 3709 3709 + "UMask": "0x10c8078201", 3710 3710 + "Unit": "CHA" 3711 3711 + }, 3712 3712 + { 3713 3713 + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC_LOCAL", 3714 3714 + "EventCode": "0x35", 3715 3715 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC_LOCAL", 3716 3716 + "PerPkg": "1", 3717 3717 + "PortMask": "0x000", 3718 3718 + "UMask": "0x10c8068201", 3719 3719 + "Unit": "CHA" 3720 3720 + }, 3721 3721 + { 3825 3722 "BriefDescription": "TOR Inserts RFO misses from local IA", 3826 3723 "EventCode": "0x35", 3827 3724 "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", ··· 3854 3717 "PerPkg": "1", 3855 3718 "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", 3856 3719 "UMask": "0xc887fe01", 3720 3720 + "Unit": "CHA" 3721 3721 + }, 3722 3722 + { 3723 3723 + "BriefDescription": "LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", 3724 3724 + "EventCode": "0x35", 3725 3725 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC", 3726 3726 + "PerPkg": "1", 3727 3727 + "UMask": "0x10ccc78201", 3728 3728 + "Unit": "CHA" 3729 3729 + }, 3730 3730 + { 3731 3731 + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC_LOCAL", 3732 3732 + "EventCode": "0x35", 3733 3733 + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC_LOCAL", 3734 3734 + "PerPkg": "1", 3735 3735 + "PortMask": "0x000", 3736 3736 + "UMask": "0x10ccc68201", 3857 3737 "Unit": "CHA" 3858 3738 }, 3859 3739 { ··· 4582 4428 "Unit": "CHA" 4583 4429 }, 4584 4430 { 4431 4431 + "BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.", 4432 4432 + "EventCode": "0x36", 4433 4433 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC", 4434 4434 + "PerPkg": "1", 4435 4435 + "UMask": "0x10c0018101", 4436 4436 + "Unit": "CHA" 4437 4437 + }, 4438 4438 + { 4439 4439 + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC_LOCAL", 4440 4440 + "EventCode": "0x35", 4441 4441 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC_LOCAL", 4442 4442 + "PerPkg": "1", 4443 4443 + "PortMask": "0x000", 4444 4444 + "UMask": "0x10c0008101", 4445 4445 + "Unit": "CHA" 4446 4446 + }, 4447 4447 + { 4585 4448 "BriefDescription": "TOR Occupancy; DRd hits from local IA", 4586 4449 "EventCode": "0x36", 4587 4450 "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", ··· 4816 4645 "Unit": "CHA" 4817 4646 }, 4818 4647 { 4648 4648 + "BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.", 4649 4649 + "EventCode": "0x36", 4650 4650 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC", 4651 4651 + "PerPkg": "1", 4652 4652 + "UMask": "0x10c0018201", 4653 4653 + "Unit": "CHA" 4654 4654 + }, 4655 4655 + { 4656 4656 + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC_LOCAL", 4657 4657 + "EventCode": "0x35", 4658 4658 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC_LOCAL", 4659 4659 + "PerPkg": "1", 4660 4660 + "PortMask": "0x000", 4661 4661 + "UMask": "0x10c0008201", 4662 4662 + "Unit": "CHA" 4663 4663 + }, 4664 4664 + { 4819 4665 "BriefDescription": "TOR Occupancy for DRd misses from local IA", 4820 4666 "EventCode": "0x36", 4821 4667 "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", ··· 4858 4670 "PortMask": "0x00000000", 4859 4671 "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", 4860 4672 "UMask": "0xc837fe01", 4673 4673 + "Unit": "CHA" 4674 4674 + }, 4675 4675 + { 4676 4676 + "BriefDescription": "TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.", 4677 4677 + "EventCode": "0x36", 4678 4678 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC", 4679 4679 + "PerPkg": "1", 4680 4680 + "UMask": "0x10c8178201", 4681 4681 + "Unit": "CHA" 4682 4682 + }, 4683 4683 + { 4684 4684 + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC_LOCAL", 4685 4685 + "EventCode": "0x35", 4686 4686 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC_LOCAL", 4687 4687 + "PerPkg": "1", 4688 4688 + "PortMask": "0x000", 4689 4689 + "UMask": "0x10c8168201", 4861 4690 "Unit": "CHA" 4862 4691 }, 4863 4692 { ··· 4923 4718 "Unit": "CHA" 4924 4719 }, 4925 4720 { 4721 4721 + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_CXL_ACC_LOCAL", 4722 4722 + "EventCode": "0x35", 4723 4723 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_CXL_ACC_LOCAL", 4724 4724 + "PerPkg": "1", 4725 4725 + "PortMask": "0x000", 4726 4726 + "UMask": "0x10c8268201", 4727 4727 + "Unit": "CHA" 4728 4728 + }, 4729 4729 + { 4926 4730 "BriefDescription": "TOR Occupancy; DRd Opt Pref misses from local IA", 4927 4731 "EventCode": "0x36", 4928 4732 "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", 4929 4733 "PerPkg": "1", 4930 4734 "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter", 4931 4735 "UMask": "0xc8a7fe01", 4736 4736 + "Unit": "CHA" 4737 4737 + }, 4738 4738 + { 4739 4739 + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL", 4740 4740 + "EventCode": "0x35", 4741 4741 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOCAL", 4742 4742 + "PerPkg": "1", 4743 4743 + "PortMask": "0x000", 4744 4744 + "UMask": "0x10c8a68201", 4932 4745 "Unit": "CHA" 4933 4746 }, 4934 4747 { ··· 4965 4742 "PerPkg": "1", 4966 4743 "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", 4967 4744 "UMask": "0xc897fe01", 4745 4745 + "Unit": "CHA" 4746 4746 + }, 4747 4747 + { 4748 4748 + "BriefDescription": "TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", 4749 4749 + "EventCode": "0x36", 4750 4750 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC", 4751 4751 + "PerPkg": "1", 4752 4752 + "UMask": "0x10c8978201", 4753 4753 + "Unit": "CHA" 4754 4754 + }, 4755 4755 + { 4756 4756 + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC_LOCAL", 4757 4757 + "EventCode": "0x35", 4758 4758 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC_LOCAL", 4759 4759 + "PerPkg": "1", 4760 4760 + "PortMask": "0x000", 4761 4761 + "UMask": "0x10c8968201", 4968 4762 "Unit": "CHA" 4969 4763 }, 4970 4764 { ··· 5119 4879 "Unit": "CHA" 5120 4880 }, 5121 4881 { 4882 4882 + "BriefDescription": "TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", 4883 4883 + "EventCode": "0x36", 4884 4884 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC", 4885 4885 + "PerPkg": "1", 4886 4886 + "UMask": "0x10ccd78201", 4887 4887 + "Unit": "CHA" 4888 4888 + }, 4889 4889 + { 4890 4890 + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL", 4891 4891 + "EventCode": "0x35", 4892 4892 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC_LOCAL", 4893 4893 + "PerPkg": "1", 4894 4894 + "PortMask": "0x000", 4895 4895 + "UMask": "0x10ccd68201", 4896 4896 + "Unit": "CHA" 4897 4897 + }, 4898 4898 + { 5122 4899 "BriefDescription": "TOR Occupancy; LLCPrefRFO misses from local IA", 5123 4900 "EventCode": "0x36", 5124 4901 "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", 5125 4902 "PerPkg": "1", 5126 4903 "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", 5127 4904 "UMask": "0xccc7fe01", 4905 4905 + "Unit": "CHA" 4906 4906 + }, 4907 4907 + { 4908 4908 + "BriefDescription": "TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", 4909 4909 + "EventCode": "0x36", 4910 4910 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC", 4911 4911 + "PerPkg": "1", 4912 4912 + "UMask": "0x10c8878201", 4913 4913 + "Unit": "CHA" 4914 4914 + }, 4915 4915 + { 4916 4916 + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL", 4917 4917 + "EventCode": "0x35", 4918 4918 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL", 4919 4919 + "PerPkg": "1", 4920 4920 + "PortMask": "0x000", 4921 4921 + "UMask": "0x10c8868201", 5128 4922 "Unit": "CHA" 5129 4923 }, 5130 4924 { ··· 5251 4977 "Unit": "CHA" 5252 4978 }, 5253 4979 { 4980 4980 + "BriefDescription": "TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", 4981 4981 + "EventCode": "0x36", 4982 4982 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC", 4983 4983 + "PerPkg": "1", 4984 4984 + "UMask": "0x10c8078201", 4985 4985 + "Unit": "CHA" 4986 4986 + }, 4987 4987 + { 4988 4988 + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC_LOCAL", 4989 4989 + "EventCode": "0x35", 4990 4990 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC_LOCAL", 4991 4991 + "PerPkg": "1", 4992 4992 + "PortMask": "0x000", 4993 4993 + "UMask": "0x10c8068201", 4994 4994 + "Unit": "CHA" 4995 4995 + }, 4996 4996 + { 5254 4997 "BriefDescription": "TOR Occupancy; RFO misses from local IA", 5255 4998 "EventCode": "0x36", 5256 4999 "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", ··· 5283 4992 "PerPkg": "1", 5284 4993 "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", 5285 4994 "UMask": "0xc887fe01", 4995 4995 + "Unit": "CHA" 4996 4996 + }, 4997 4997 + { 4998 4998 + "BriefDescription": "TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", 4999 4999 + "EventCode": "0x36", 5000 5000 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC", 5001 5001 + "PerPkg": "1", 5002 5002 + "UMask": "0x10ccc78201", 5003 5003 + "Unit": "CHA" 5004 5004 + }, 5005 5005 + { 5006 5006 + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC_LOCAL", 5007 5007 + "EventCode": "0x35", 5008 5008 + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC_LOCAL", 5009 5009 + "PerPkg": "1", 5010 5010 + "PortMask": "0x000", 5011 5011 + "UMask": "0x10ccc68201", 5286 5012 "Unit": "CHA" 5287 5013 }, 5288 5014 {

+1 -1

tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconnect.json

reviewed

··· 3326 3326 "EventCode": "0x50", 3327 3327 "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", 3328 3328 "PerPkg": "1", 3329 3329 - "PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in paralle", 3329 3329 + "PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in parallel", 3330 3330 "UMask": "0x8", 3331 3331 "Unit": "M3UPI" 3332 3332 },

+38 -5

tools/perf/pmu-events/arch/x86/skylake/frontend.json

reviewed

··· 8 8 "UMask": "0x1" 9 9 }, 10 10 { 11 11 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]", 12 12 + "EventCode": "0x87", 13 13 + "EventName": "DECODE.LCP", 14 14 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]", 15 15 + "SampleAfterValue": "2000003", 16 16 + "UMask": "0x1" 17 17 + }, 18 18 + { 11 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 12 20 "EventCode": "0xAB", 13 21 "EventName": "DSB2MITE_SWITCHES.COUNT", ··· 253 245 "UMask": "0x2" 254 246 }, 255 247 { 256 256 - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 248 248 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", 257 249 "EventCode": "0x83", 258 250 "EventName": "ICACHE_64B.IFTAG_STALL", 259 251 "SampleAfterValue": "200003", 260 252 "UMask": "0x4" 261 253 }, 262 254 { 263 263 - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 255 255 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", 256 256 + "EventCode": "0x83", 257 257 + "EventName": "ICACHE_TAG.STALLS", 258 258 + "SampleAfterValue": "200003", 259 259 + "UMask": "0x4" 260 260 + }, 261 261 + { 262 262 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.DSB_CYCLES_OK]", 264 263 "CounterMask": "4", 265 264 "EventCode": "0x79", 266 265 "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", 267 267 - "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.", 266 266 + "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK]", 268 267 "SampleAfterValue": "2000003", 269 268 "UMask": "0x18" 270 269 }, 271 270 { 272 272 - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 271 271 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.DSB_CYCLES_ANY]", 273 272 "CounterMask": "1", 274 273 "EventCode": "0x79", 275 274 "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", 276 276 - "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.", 275 275 + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_ANY]", 277 276 "SampleAfterValue": "2000003", 278 277 "UMask": "0x18" 279 278 }, ··· 310 295 "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", 311 296 "SampleAfterValue": "2000003", 312 297 "UMask": "0x8" 298 298 + }, 299 299 + { 300 300 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]", 301 301 + "CounterMask": "1", 302 302 + "EventCode": "0x79", 303 303 + "EventName": "IDQ.DSB_CYCLES_ANY", 304 304 + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]", 305 305 + "SampleAfterValue": "2000003", 306 306 + "UMask": "0x18" 307 307 + }, 308 308 + { 309 309 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]", 310 310 + "CounterMask": "4", 311 311 + "EventCode": "0x79", 312 312 + "EventName": "IDQ.DSB_CYCLES_OK", 313 313 + "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]", 314 314 + "SampleAfterValue": "2000003", 315 315 + "UMask": "0x18" 313 316 }, 314 317 { 315 318 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+13 -4

tools/perf/pmu-events/arch/x86/skylake/pipeline.json

reviewed

··· 352 352 "UMask": "0x1" 353 353 }, 354 354 { 355 355 - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", 355 355 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]", 356 356 "EventCode": "0x87", 357 357 "EventName": "ILD_STALL.LCP", 358 358 - "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", 358 358 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]", 359 359 "SampleAfterValue": "2000003", 360 360 "UMask": "0x1" 361 361 }, ··· 479 479 "UMask": "0x1" 480 480 }, 481 481 { 482 482 - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", 482 482 + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_OK]", 483 483 "CounterMask": "4", 484 484 "EventCode": "0xA8", 485 485 "EventName": "LSD.CYCLES_4_UOPS", 486 486 - "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector).", 486 486 + "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_OK]", 487 487 "SampleAfterValue": "2000003", 488 488 "UMask": "0x1" 489 489 }, ··· 493 493 "EventCode": "0xA8", 494 494 "EventName": "LSD.CYCLES_ACTIVE", 495 495 "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", 496 496 + "SampleAfterValue": "2000003", 497 497 + "UMask": "0x1" 498 498 + }, 499 499 + { 500 500 + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS]", 501 501 + "CounterMask": "4", 502 502 + "EventCode": "0xA8", 503 503 + "EventName": "LSD.CYCLES_OK", 504 504 + "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_4_UOPS]", 496 505 "SampleAfterValue": "2000003", 497 506 "UMask": "0x1" 498 507 },

+4 -4

tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json

reviewed

··· 1466 1466 }, 1467 1467 { 1468 1468 "BriefDescription": "Percentage of cycles in aborted transactions.", 1469 1469 - "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", 1469 1469 + "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)", 1470 1470 "MetricGroup": "transaction", 1471 1471 "MetricName": "tsx_aborted_cycles", 1472 1472 "ScaleUnit": "100%" 1473 1473 }, 1474 1474 { 1475 1475 "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", 1476 1476 - "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", 1476 1476 + "MetricExpr": "(cycles\\-t / el\\-start if has_event(cycles\\-t) else 0)", 1477 1477 "MetricGroup": "transaction", 1478 1478 "MetricName": "tsx_cycles_per_elision", 1479 1479 "ScaleUnit": "1cycles / elision" 1480 1480 }, 1481 1481 { 1482 1482 "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", 1483 1483 - "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", 1483 1483 + "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)", 1484 1484 "MetricGroup": "transaction", 1485 1485 "MetricName": "tsx_cycles_per_transaction", 1486 1486 "ScaleUnit": "1cycles / transaction" 1487 1487 }, 1488 1488 { 1489 1489 "BriefDescription": "Percentage of cycles within a transaction region.", 1490 1490 - "MetricExpr": "cpu@cycles\\-t@ / cycles", 1490 1490 + "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)", 1491 1491 "MetricGroup": "transaction", 1492 1492 "MetricName": "tsx_transactional_cycles", 1493 1493 "ScaleUnit": "100%"

+38 -5

tools/perf/pmu-events/arch/x86/skylakex/frontend.json

reviewed

··· 8 8 "UMask": "0x1" 9 9 }, 10 10 { 11 11 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]", 12 12 + "EventCode": "0x87", 13 13 + "EventName": "DECODE.LCP", 14 14 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]", 15 15 + "SampleAfterValue": "2000003", 16 16 + "UMask": "0x1" 17 17 + }, 18 18 + { 11 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", 12 20 "EventCode": "0xAB", 13 21 "EventName": "DSB2MITE_SWITCHES.COUNT", ··· 253 245 "UMask": "0x2" 254 246 }, 255 247 { 256 256 - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 248 248 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", 257 249 "EventCode": "0x83", 258 250 "EventName": "ICACHE_64B.IFTAG_STALL", 259 251 "SampleAfterValue": "200003", 260 252 "UMask": "0x4" 261 253 }, 262 254 { 263 263 - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", 255 255 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", 256 256 + "EventCode": "0x83", 257 257 + "EventName": "ICACHE_TAG.STALLS", 258 258 + "SampleAfterValue": "200003", 259 259 + "UMask": "0x4" 260 260 + }, 261 261 + { 262 262 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.DSB_CYCLES_OK]", 264 263 "CounterMask": "4", 265 264 "EventCode": "0x79", 266 265 "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", 267 267 - "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.", 266 266 + "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK]", 268 267 "SampleAfterValue": "2000003", 269 268 "UMask": "0x18" 270 269 }, 271 270 { 272 272 - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", 271 271 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.DSB_CYCLES_ANY]", 273 272 "CounterMask": "1", 274 273 "EventCode": "0x79", 275 274 "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", 276 276 - "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.", 275 275 + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_ANY]", 277 276 "SampleAfterValue": "2000003", 278 277 "UMask": "0x18" 279 278 }, ··· 310 295 "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", 311 296 "SampleAfterValue": "2000003", 312 297 "UMask": "0x8" 298 298 + }, 299 299 + { 300 300 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]", 301 301 + "CounterMask": "1", 302 302 + "EventCode": "0x79", 303 303 + "EventName": "IDQ.DSB_CYCLES_ANY", 304 304 + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]", 305 305 + "SampleAfterValue": "2000003", 306 306 + "UMask": "0x18" 307 307 + }, 308 308 + { 309 309 + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]", 310 310 + "CounterMask": "4", 311 311 + "EventCode": "0x79", 312 312 + "EventName": "IDQ.DSB_CYCLES_OK", 313 313 + "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]", 314 314 + "SampleAfterValue": "2000003", 315 315 + "UMask": "0x18" 313 316 }, 314 317 { 315 318 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",

+13 -4

tools/perf/pmu-events/arch/x86/skylakex/pipeline.json

reviewed

··· 361 361 "UMask": "0x1" 362 362 }, 363 363 { 364 364 - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", 364 364 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]", 365 365 "EventCode": "0x87", 366 366 "EventName": "ILD_STALL.LCP", 367 367 - "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", 367 367 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]", 368 368 "SampleAfterValue": "2000003", 369 369 "UMask": "0x1" 370 370 }, ··· 488 488 "UMask": "0x1" 489 489 }, 490 490 { 491 491 - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", 491 491 + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_OK]", 492 492 "CounterMask": "4", 493 493 "EventCode": "0xA8", 494 494 "EventName": "LSD.CYCLES_4_UOPS", 495 495 - "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector).", 495 495 + "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_OK]", 496 496 "SampleAfterValue": "2000003", 497 497 "UMask": "0x1" 498 498 }, ··· 502 502 "EventCode": "0xA8", 503 503 "EventName": "LSD.CYCLES_ACTIVE", 504 504 "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", 505 505 + "SampleAfterValue": "2000003", 506 506 + "UMask": "0x1" 507 507 + }, 508 508 + { 509 509 + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS]", 510 510 + "CounterMask": "4", 511 511 + "EventCode": "0xA8", 512 512 + "EventName": "LSD.CYCLES_OK", 513 513 + "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_4_UOPS]", 505 514 "SampleAfterValue": "2000003", 506 515 "UMask": "0x1" 507 516 },

+4 -4

tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json

reviewed

··· 1774 1774 }, 1775 1775 { 1776 1776 "BriefDescription": "Percentage of cycles in aborted transactions.", 1777 1777 - "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", 1777 1777 + "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)", 1778 1778 "MetricGroup": "transaction", 1779 1779 "MetricName": "tsx_aborted_cycles", 1780 1780 "ScaleUnit": "100%" 1781 1781 }, 1782 1782 { 1783 1783 "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", 1784 1784 - "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", 1784 1784 + "MetricExpr": "(cycles\\-t / el\\-start if has_event(cycles\\-t) else 0)", 1785 1785 "MetricGroup": "transaction", 1786 1786 "MetricName": "tsx_cycles_per_elision", 1787 1787 "ScaleUnit": "1cycles / elision" 1788 1788 }, 1789 1789 { 1790 1790 "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", 1791 1791 - "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", 1791 1791 + "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)", 1792 1792 "MetricGroup": "transaction", 1793 1793 "MetricName": "tsx_cycles_per_transaction", 1794 1794 "ScaleUnit": "1cycles / transaction" 1795 1795 }, 1796 1796 { 1797 1797 "BriefDescription": "Percentage of cycles within a transaction region.", 1798 1798 - "MetricExpr": "cpu@cycles\\-t@ / cycles", 1798 1798 + "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)", 1799 1799 "MetricGroup": "transaction", 1800 1800 "MetricName": "tsx_transactional_cycles", 1801 1801 "ScaleUnit": "100%"

+1 -1

tools/perf/pmu-events/arch/x86/skylakex/uncore-interconnect.json

reviewed

··· 6504 6504 "EventCode": "0x52", 6505 6505 "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", 6506 6506 "PerPkg": "1", 6507 6507 - "PublicDescription": "ad and bl messages were actually slotted into the same flit in paralle", 6507 6507 + "PublicDescription": "ad and bl messages were actually slotted into the same flit in parallel", 6508 6508 "UMask": "0x8", 6509 6509 "Unit": "M3UPI" 6510 6510 },

+1 -1

tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json

reviewed

··· 1952 1952 "EventCode": "0x81", 1953 1953 "EventName": "UNC_M_WPQ_OCCUPANCY", 1954 1954 "PerPkg": "1", 1955 1955 - "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts?", 1955 1955 + "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", 1956 1956 "Unit": "iMC" 1957 1957 }, 1958 1958 {

+28 -4

tools/perf/pmu-events/arch/x86/tigerlake/frontend.json

reviewed

··· 8 8 "UMask": "0x1" 9 9 }, 10 10 { 11 11 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]", 12 12 + "EventCode": "0x87", 13 13 + "EventName": "DECODE.LCP", 14 14 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]", 15 15 + "SampleAfterValue": "500009", 16 16 + "UMask": "0x1" 17 17 + }, 18 18 + { 11 19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", 12 20 "CounterMask": "1", 13 21 "EdgeDetect": "1", ··· 221 213 "UMask": "0x1" 222 214 }, 223 215 { 224 224 - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", 216 216 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]", 225 217 "EventCode": "0x80", 226 218 "EventName": "ICACHE_16B.IFDATA_STALL", 227 227 - "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.", 219 219 + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]", 228 220 "SampleAfterValue": "500009", 229 221 "UMask": "0x4" 230 222 }, ··· 245 237 "UMask": "0x2" 246 238 }, 247 239 { 248 248 - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 240 240 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", 249 241 "EventCode": "0x83", 250 242 "EventName": "ICACHE_64B.IFTAG_STALL", 251 251 - "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.", 243 243 + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", 244 244 + "SampleAfterValue": "200003", 245 245 + "UMask": "0x4" 246 246 + }, 247 247 + { 248 248 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]", 249 249 + "EventCode": "0x80", 250 250 + "EventName": "ICACHE_DATA.STALLS", 251 251 + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]", 252 252 + "SampleAfterValue": "500009", 253 253 + "UMask": "0x4" 254 254 + }, 255 255 + { 256 256 + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", 257 257 + "EventCode": "0x83", 258 258 + "EventName": "ICACHE_TAG.STALLS", 259 259 + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]", 252 260 "SampleAfterValue": "200003", 253 261 "UMask": "0x4" 254 262 },

+3 -3

tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json

reviewed

··· 335 335 "UMask": "0x80" 336 336 }, 337 337 { 338 338 - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", 338 338 + "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]", 339 339 "EventCode": "0x87", 340 340 "EventName": "ILD_STALL.LCP", 341 341 - "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", 341 341 + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]", 342 342 "SampleAfterValue": "500009", 343 343 "UMask": "0x1" 344 344 }, ··· 564 564 "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", 565 565 "EventCode": "0xa4", 566 566 "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", 567 567 - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", 567 567 + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the speculative path as well as the out-of-order engine recovery past a branch misprediction.", 568 568 "SampleAfterValue": "10000003", 569 569 "UMask": "0x8" 570 570 },

+4 -4

tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json

reviewed

··· 1530 1530 }, 1531 1531 { 1532 1532 "BriefDescription": "Percentage of cycles in aborted transactions.", 1533 1533 - "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", 1533 1533 + "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)", 1534 1534 "MetricGroup": "transaction", 1535 1535 "MetricName": "tsx_aborted_cycles", 1536 1536 "ScaleUnit": "100%" 1537 1537 }, 1538 1538 { 1539 1539 "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", 1540 1540 - "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", 1540 1540 + "MetricExpr": "(cycles\\-t / el\\-start if has_event(cycles\\-t) else 0)", 1541 1541 "MetricGroup": "transaction", 1542 1542 "MetricName": "tsx_cycles_per_elision", 1543 1543 "ScaleUnit": "1cycles / elision" 1544 1544 }, 1545 1545 { 1546 1546 "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", 1547 1547 - "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", 1547 1547 + "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) else 0)", 1548 1548 "MetricGroup": "transaction", 1549 1549 "MetricName": "tsx_cycles_per_transaction", 1550 1550 "ScaleUnit": "1cycles / transaction" 1551 1551 }, 1552 1552 { 1553 1553 "BriefDescription": "Percentage of cycles within a transaction region.", 1554 1554 - "MetricExpr": "cpu@cycles\\-t@ / cycles", 1554 1554 + "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else 0)", 1555 1555 "MetricGroup": "transaction", 1556 1556 "MetricName": "tsx_transactional_cycles", 1557 1557 "ScaleUnit": "100%"

+7 -1

tools/perf/pmu-events/metric.py

reviewed

··· 408 408 return Function('source_count', event) 409 409 410 410 411 411 + def has_event(event: Event) -> Function: 412 412 + # pylint: disable=redefined-builtin 413 413 + # pylint: disable=invalid-name 414 414 + return Function('has_event', event) 415 415 + 416 416 + 411 417 class Metric: 412 418 """An individual metric that will specifiable on the perf command line.""" 413 419 groups: Set[str] ··· 545 539 r'Event(r"\1")', py) 546 540 py = re.sub(r'#Event\(r"([^"]*)"\)', r'Literal("#\1")', py) 547 541 py = re.sub(r'([0-9]+)Event\(r"(e[0-9]+)"\)', r'\1\2', py) 548 548 - keywords = ['if', 'else', 'min', 'max', 'd_ratio', 'source_count'] 542 542 + keywords = ['if', 'else', 'min', 'max', 'd_ratio', 'source_count', 'has_event'] 549 543 for kw in keywords: 550 544 py = re.sub(rf'Event\(r"{kw}"\)', kw, py) 551 545

-1

tools/perf/tests/builtin-test.c

reviewed

··· 542 542 return run_workload(workload, argc, argv); 543 543 544 544 symbol_conf.priv_size = sizeof(int); 545 545 - symbol_conf.sort_by_name = true; 546 545 symbol_conf.try_vmlinux_path = true; 547 546 548 547 if (symbol__init(NULL) < 0)

+4

tools/perf/tests/expr.c

reviewed

··· 254 254 TEST_ASSERT_VAL("source count", hashmap__size(ctx->ids) == 1); 255 255 TEST_ASSERT_VAL("source count", hashmap__find(ctx->ids, "EVENT1", &val_ptr)); 256 256 257 257 + /* has_event returns 1 when an event exists. */ 258 258 + expr__add_id_val(ctx, strdup("cycles"), 2); 259 259 + ret = test(ctx, "has_event(cycles)", 1); 260 260 + 257 261 expr__ctx_free(ctx); 258 262 259 263 return 0;

+4

tools/perf/tests/make

reviewed

··· 70 70 make_debug := DEBUG=1 71 71 make_nondistro := BUILD_NONDISTRO=1 72 72 make_extra_tests := EXTRA_TESTS=1 73 73 + make_bpf_skel := BUILD_BPF_SKEL=1 74 74 + make_gen_vmlinux_h := BUILD_BPF_SKEL=1 GEN_VMLINUX_H=1 73 75 make_no_libperl := NO_LIBPERL=1 74 76 make_no_libpython := NO_LIBPYTHON=1 75 77 make_no_scripts := NO_LIBPYTHON=1 NO_LIBPERL=1 ··· 139 137 run += make_python_perf_so 140 138 run += make_debug 141 139 run += make_nondistro 140 140 + run += make_build_bpf_skel 141 141 + run += make_gen_vmlinux_h 142 142 run += make_no_libperl 143 143 run += make_no_libpython 144 144 run += make_no_scripts

+63 -37

tools/perf/tests/parse-events.c

reviewed

··· 20 20 #define PERF_TP_SAMPLE_TYPE (PERF_SAMPLE_RAW | PERF_SAMPLE_TIME | \ 21 21 PERF_SAMPLE_CPU | PERF_SAMPLE_PERIOD) 22 22 23 23 + static int num_core_entries(void) 24 24 + { 25 25 + /* 26 26 + * If the kernel supports extended type, expect events to be 27 27 + * opened once for each core PMU type. Otherwise fall back to the legacy 28 28 + * behavior of opening only one event even though there are multiple 29 29 + * PMUs 30 30 + */ 31 31 + if (perf_pmus__supports_extended_type()) 32 32 + return perf_pmus__num_core_pmus(); 33 33 + 34 34 + return 1; 35 35 + } 36 36 + 23 37 static bool test_config(const struct evsel *evsel, __u64 expected_config) 24 38 { 25 39 __u32 type = evsel->core.attr.type; ··· 122 108 TEST_ASSERT_VAL("wrong number of entries", 0 != evlist->core.nr_entries); 123 109 124 110 perf_evlist__for_each_evsel(&evlist->core, evsel) { 125 125 - struct perf_pmu *pmu = NULL; 111 111 + struct perf_pmu *pmu __maybe_unused = NULL; 126 112 bool type_matched = false; 127 113 128 114 TEST_ASSERT_VAL("wrong config", test_perf_config(evsel, 0x1a)); 115 115 + TEST_ASSERT_VAL("event not parsed as raw type", 116 116 + evsel->attr.type == PERF_TYPE_RAW); 117 117 + #if defined(__aarch64__) 118 118 + /* 119 119 + * Arm doesn't have a real raw type PMU in sysfs, so raw events 120 120 + * would never match any PMU. However, RAW events on Arm will 121 121 + * always successfully open on the first available core PMU 122 122 + * so no need to test for a matching type here. 123 123 + */ 124 124 + type_matched = raw_type_match = true; 125 125 + #else 129 126 while ((pmu = perf_pmus__scan(pmu)) != NULL) { 130 127 if (pmu->type == evsel->attr.type) { 131 128 TEST_ASSERT_VAL("PMU type expected once", !type_matched); ··· 145 120 raw_type_match = true; 146 121 } 147 122 } 123 123 + #endif 148 124 TEST_ASSERT_VAL("No PMU found for type", type_matched); 149 125 } 150 126 TEST_ASSERT_VAL("Raw PMU not matched", raw_type_match); ··· 353 327 struct perf_evsel *evsel; 354 328 355 329 TEST_ASSERT_VAL("wrong number of entries", 356 356 - evlist->core.nr_entries == perf_pmus__num_core_pmus()); 330 330 + evlist->core.nr_entries == num_core_entries()); 357 331 358 332 perf_evlist__for_each_entry(&evlist->core, evsel) { 359 333 TEST_ASSERT_VAL("wrong exclude_user", evsel->attr.exclude_user); ··· 856 830 struct evsel *evsel, *leader; 857 831 858 832 TEST_ASSERT_VAL("wrong number of entries", 859 859 - evlist->core.nr_entries == (perf_pmus__num_core_pmus() * 2)); 833 833 + evlist->core.nr_entries == (num_core_entries() * 2)); 860 834 TEST_ASSERT_VAL("wrong number of groups", 861 861 - evlist__nr_groups(evlist) == perf_pmus__num_core_pmus()); 835 835 + evlist__nr_groups(evlist) == num_core_entries()); 862 836 863 863 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 837 837 + for (int i = 0; i < num_core_entries(); i++) { 864 838 /* instructions:k */ 865 839 evsel = leader = (i == 0 ? evlist__first(evlist) : evsel__next(evsel)); 866 840 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 899 873 struct evsel *evsel, *leader = NULL; 900 874 901 875 TEST_ASSERT_VAL("wrong number of entries", 902 902 - evlist->core.nr_entries == (2 * perf_pmus__num_core_pmus() + 1)); 876 876 + evlist->core.nr_entries == (2 * num_core_entries() + 1)); 903 877 /* 904 878 * TODO: Currently the software event won't be grouped with the hardware 905 879 * event except for 1 PMU. ··· 1065 1039 struct evsel *evsel, *leader; 1066 1040 1067 1041 TEST_ASSERT_VAL("wrong number of entries", 1068 1068 - evlist->core.nr_entries == (perf_pmus__num_core_pmus() * 2)); 1042 1042 + evlist->core.nr_entries == (num_core_entries() * 2)); 1069 1043 TEST_ASSERT_VAL("wrong number of groups", 1070 1070 - perf_pmus__num_core_pmus() == evlist__nr_groups(evlist)); 1044 1044 + num_core_entries() == evlist__nr_groups(evlist)); 1071 1045 1072 1072 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1046 1046 + for (int i = 0; i < num_core_entries(); i++) { 1073 1047 /* cycles:u + p */ 1074 1048 evsel = leader = (i == 0 ? evlist__first(evlist) : evsel__next(evsel)); 1075 1049 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 1110 1084 struct evsel *evsel = NULL, *leader; 1111 1085 1112 1086 TEST_ASSERT_VAL("wrong number of entries", 1113 1113 - evlist->core.nr_entries == (5 * perf_pmus__num_core_pmus())); 1087 1087 + evlist->core.nr_entries == (5 * num_core_entries())); 1114 1088 TEST_ASSERT_VAL("wrong number of groups", 1115 1115 - evlist__nr_groups(evlist) == (2 * perf_pmus__num_core_pmus())); 1089 1089 + evlist__nr_groups(evlist) == (2 * num_core_entries())); 1116 1090 1117 1117 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1091 1091 + for (int i = 0; i < num_core_entries(); i++) { 1118 1092 /* cycles + G */ 1119 1093 evsel = leader = (i == 0 ? evlist__first(evlist) : evsel__next(evsel)); 1120 1094 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 1145 1119 TEST_ASSERT_VAL("wrong group_idx", evsel__group_idx(evsel) == 1); 1146 1120 TEST_ASSERT_VAL("wrong sample_read", !evsel->sample_read); 1147 1121 } 1148 1148 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1122 1122 + for (int i = 0; i < num_core_entries(); i++) { 1149 1123 /* cycles:G */ 1150 1124 evsel = leader = evsel__next(evsel); 1151 1125 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 1175 1149 TEST_ASSERT_VAL("wrong leader", evsel__has_leader(evsel, leader)); 1176 1150 TEST_ASSERT_VAL("wrong group_idx", evsel__group_idx(evsel) == 1); 1177 1151 } 1178 1178 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1152 1152 + for (int i = 0; i < num_core_entries(); i++) { 1179 1153 /* cycles */ 1180 1154 evsel = evsel__next(evsel); 1181 1155 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 1196 1170 struct evsel *evsel = NULL, *leader; 1197 1171 1198 1172 TEST_ASSERT_VAL("wrong number of entries", 1199 1199 - evlist->core.nr_entries == (2 * perf_pmus__num_core_pmus())); 1173 1173 + evlist->core.nr_entries == (2 * num_core_entries())); 1200 1174 TEST_ASSERT_VAL("wrong number of groups", 1201 1201 - evlist__nr_groups(evlist) == perf_pmus__num_core_pmus()); 1175 1175 + evlist__nr_groups(evlist) == num_core_entries()); 1202 1176 1203 1203 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1177 1177 + for (int i = 0; i < num_core_entries(); i++) { 1204 1178 /* cycles + :H group modifier */ 1205 1179 evsel = leader = (i == 0 ? evlist__first(evlist) : evsel__next(evsel)); 1206 1180 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 1237 1211 struct evsel *evsel = NULL, *leader; 1238 1212 1239 1213 TEST_ASSERT_VAL("wrong number of entries", 1240 1240 - evlist->core.nr_entries == (2 * perf_pmus__num_core_pmus())); 1214 1214 + evlist->core.nr_entries == (2 * num_core_entries())); 1241 1215 TEST_ASSERT_VAL("wrong number of groups", 1242 1242 - evlist__nr_groups(evlist) == perf_pmus__num_core_pmus()); 1216 1216 + evlist__nr_groups(evlist) == num_core_entries()); 1243 1217 1244 1244 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1218 1218 + for (int i = 0; i < num_core_entries(); i++) { 1245 1219 /* cycles + :G group modifier */ 1246 1220 evsel = leader = (i == 0 ? evlist__first(evlist) : evsel__next(evsel)); 1247 1221 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 1278 1252 struct evsel *evsel = NULL, *leader; 1279 1253 1280 1254 TEST_ASSERT_VAL("wrong number of entries", 1281 1281 - evlist->core.nr_entries == (2 * perf_pmus__num_core_pmus())); 1255 1255 + evlist->core.nr_entries == (2 * num_core_entries())); 1282 1256 TEST_ASSERT_VAL("wrong number of groups", 1283 1283 - evlist__nr_groups(evlist) == perf_pmus__num_core_pmus()); 1257 1257 + evlist__nr_groups(evlist) == num_core_entries()); 1284 1258 1285 1285 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1259 1259 + for (int i = 0; i < num_core_entries(); i++) { 1286 1260 /* cycles:G + :u group modifier */ 1287 1261 evsel = leader = (i == 0 ? evlist__first(evlist) : evsel__next(evsel)); 1288 1262 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 1319 1293 struct evsel *evsel = NULL, *leader; 1320 1294 1321 1295 TEST_ASSERT_VAL("wrong number of entries", 1322 1322 - evlist->core.nr_entries == (2 * perf_pmus__num_core_pmus())); 1296 1296 + evlist->core.nr_entries == (2 * num_core_entries())); 1323 1297 TEST_ASSERT_VAL("wrong number of groups", 1324 1324 - evlist__nr_groups(evlist) == perf_pmus__num_core_pmus()); 1298 1298 + evlist__nr_groups(evlist) == num_core_entries()); 1325 1299 1326 1326 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1300 1300 + for (int i = 0; i < num_core_entries(); i++) { 1327 1301 /* cycles:G + :uG group modifier */ 1328 1302 evsel = leader = (i == 0 ? evlist__first(evlist) : evsel__next(evsel)); 1329 1303 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 1360 1334 struct evsel *evsel = NULL, *leader; 1361 1335 1362 1336 TEST_ASSERT_VAL("wrong number of entries", 1363 1363 - evlist->core.nr_entries == (3 * perf_pmus__num_core_pmus())); 1337 1337 + evlist->core.nr_entries == (3 * num_core_entries())); 1364 1338 1365 1365 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1339 1339 + for (int i = 0; i < num_core_entries(); i++) { 1366 1340 /* cycles - sampling group leader */ 1367 1341 evsel = leader = (i == 0 ? evlist__first(evlist) : evsel__next(evsel)); 1368 1342 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 1412 1386 struct evsel *evsel = NULL, *leader; 1413 1387 1414 1388 TEST_ASSERT_VAL("wrong number of entries", 1415 1415 - evlist->core.nr_entries == (2 * perf_pmus__num_core_pmus())); 1389 1389 + evlist->core.nr_entries == (2 * num_core_entries())); 1416 1390 1417 1417 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1391 1391 + for (int i = 0; i < num_core_entries(); i++) { 1418 1392 /* instructions - sampling group leader */ 1419 1393 evsel = leader = (i == 0 ? evlist__first(evlist) : evsel__next(evsel)); 1420 1394 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 1451 1425 struct evsel *evsel = NULL; 1452 1426 1453 1427 TEST_ASSERT_VAL("wrong number of entries", 1454 1454 - evlist->core.nr_entries == perf_pmus__num_core_pmus()); 1428 1428 + evlist->core.nr_entries == num_core_entries()); 1455 1429 1456 1456 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1430 1430 + for (int i = 0; i < num_core_entries(); i++) { 1457 1431 evsel = (i == 0 ? evlist__first(evlist) : evsel__next(evsel)); 1458 1432 TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); 1459 1433 TEST_ASSERT_VAL("wrong exclude_kernel", evsel->core.attr.exclude_kernel); ··· 1469 1443 struct evsel *evsel = NULL, *leader; 1470 1444 1471 1445 TEST_ASSERT_VAL("wrong number of entries", 1472 1472 - evlist->core.nr_entries == (3 * perf_pmus__num_core_pmus())); 1446 1446 + evlist->core.nr_entries == (3 * num_core_entries())); 1473 1447 1474 1474 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1448 1448 + for (int i = 0; i < num_core_entries(); i++) { 1475 1449 /* cycles - group leader */ 1476 1450 evsel = leader = (i == 0 ? evlist__first(evlist) : evsel__next(evsel)); 1477 1451 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 1514 1488 struct evsel *evsel = NULL, *leader; 1515 1489 1516 1490 TEST_ASSERT_VAL("wrong number of entries", 1517 1517 - evlist->core.nr_entries == (3 * perf_pmus__num_core_pmus())); 1491 1491 + evlist->core.nr_entries == 3 * num_core_entries()); 1518 1492 1519 1519 - for (int i = 0; i < perf_pmus__num_core_pmus(); i++) { 1493 1493 + for (int i = 0; i < num_core_entries(); i++) { 1520 1494 /* cycles - group leader */ 1521 1495 evsel = leader = (i == 0 ? evlist__first(evlist) : evsel__next(evsel)); 1522 1496 TEST_ASSERT_VAL("wrong type", PERF_TYPE_HARDWARE == evsel->core.attr.type); ··· 1588 1562 struct evsel *evsel = evlist__first(evlist); 1589 1563 1590 1564 TEST_ASSERT_VAL("wrong number of entries", 1591 1591 - evlist->core.nr_entries == (1 + perf_pmus__num_core_pmus())); 1565 1565 + evlist->core.nr_entries == 1 + num_core_entries()); 1592 1566 TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE == evsel->core.attr.type); 1593 1567 TEST_ASSERT_VAL("wrong config", test_config(evsel, PERF_COUNT_SW_TASK_CLOCK)); 1594 1568 return TEST_OK;

+2 -1

tools/perf/tests/pe-file-parsing.c

reviewed

··· 34 34 struct dso *dso; 35 35 struct symbol *sym; 36 36 int ret; 37 37 + size_t idx; 37 38 38 39 scnprintf(filename, PATH_MAX, "%s/pe-file.exe", d); 39 40 ret = filename__read_build_id(filename, &bid); ··· 62 61 TEST_ASSERT_VAL("Failed to load symbols", ret == 0); 63 62 64 63 dso__sort_by_name(dso); 65 65 - sym = dso__find_symbol_by_name(dso, "main"); 64 64 + sym = dso__find_symbol_by_name(dso, "main", &idx); 66 65 TEST_ASSERT_VAL("Failed to find main", sym); 67 66 dso__delete(dso); 68 67

+36

tools/perf/tests/shell/lock_contention.sh

reviewed

··· 233 233 fi 234 234 } 235 235 236 236 + test_csv_output() 237 237 + { 238 238 + echo "Testing perf lock contention CSV output" 239 239 + perf lock contention -i ${perfdata} -E 1 -x , --output ${result} 240 240 + # count the number of commas in the header 241 241 + # it should have 5: contended, total-wait, max-wait, avg-wait, type, caller 242 242 + header=$(grep "# output:" ${result} | tr -d -c , | wc -c) 243 243 + if [ "${header}" != "5" ]; then 244 244 + echo "[Fail] Recorded result does not have enough output columns: ${header} != 5" 245 245 + err=1 246 246 + exit 247 247 + fi 248 248 + # count the number of commas in the output 249 249 + output=$(grep -v "^#" ${result} | tr -d -c , | wc -c) 250 250 + if [ "${header}" != "${output}" ]; then 251 251 + echo "[Fail] Recorded result does not match the number of commas: ${header} != ${output}" 252 252 + err=1 253 253 + exit 254 254 + fi 255 255 + 256 256 + if ! perf lock con -b true > /dev/null 2>&1 ; then 257 257 + echo "[Skip] No BPF support" 258 258 + return 259 259 + fi 260 260 + 261 261 + # the perf lock contention output goes to the stderr 262 262 + perf lock con -a -b -E 1 -x , --output ${result} -- perf bench sched messaging > /dev/null 2>&1 263 263 + output=$(grep -v "^#" ${result} | tr -d -c , | wc -c) 264 264 + if [ "${header}" != "${output}" ]; then 265 265 + echo "[Fail] BPF result does not match the number of commas: ${header} != ${output}" 266 266 + err=1 267 267 + exit 268 268 + fi 269 269 + } 270 270 + 236 271 check 237 272 238 273 test_record ··· 279 244 test_lock_filter 280 245 test_stack_filter 281 246 test_aggr_task_stack_filter 247 247 + test_csv_output 282 248 283 249 exit ${err}

+1

tools/perf/util/bpf_skel/.gitignore

reviewed

··· 1 1 # SPDX-License-Identifier: GPL-2.0-only 2 2 .tmp 3 3 *.skel.h 4 4 + vmlinux.h

-2

tools/perf/util/bpf_skel/lock_contention.bpf.c

reviewed

··· 416 416 return 0; 417 417 } 418 418 419 419 - struct rq {}; 420 420 - 421 419 extern struct rq runqueues __ksym; 422 420 423 421 struct rq___old {

+10

tools/perf/util/bpf_skel/vmlinux.h tools/perf/util/bpf_skel/vmlinux/vmlinux.h

reviewed

··· 171 171 struct perf_sample_data *data; 172 172 struct perf_event *event; 173 173 } __attribute__((preserve_access_index)); 174 174 + 175 175 + /* 176 176 + * If 'struct rq' isn't defined for lock_contention.bpf.c, for the sake of 177 177 + * rq___old and rq___new, then the type for the 'runqueue' variable ends up 178 178 + * being a forward declaration (BTF_KIND_FWD) while the kernel has it defined 179 179 + * (BTF_KIND_STRUCT). The definition appears in vmlinux.h rather than 180 180 + * lock_contention.bpf.c for consistency with a generated vmlinux.h. 181 181 + */ 182 182 + struct rq {}; 183 183 + 174 184 #endif // __VMLINUX_H

+5 -2

tools/perf/util/dso.c

reviewed

··· 1320 1320 dso->id = *id; 1321 1321 dso__set_long_name_id(dso, dso->name, id, false); 1322 1322 dso__set_short_name(dso, dso->name, false); 1323 1323 - dso->symbols = dso->symbol_names = RB_ROOT_CACHED; 1323 1323 + dso->symbols = RB_ROOT_CACHED; 1324 1324 + dso->symbol_names = NULL; 1325 1325 + dso->symbol_names_len = 0; 1324 1326 dso->data.cache = RB_ROOT; 1325 1327 dso->inlined_nodes = RB_ROOT_CACHED; 1326 1328 dso->srclines = RB_ROOT_CACHED; ··· 1366 1364 inlines__tree_delete(&dso->inlined_nodes); 1367 1365 srcline__tree_delete(&dso->srclines); 1368 1366 symbols__delete(&dso->symbols); 1369 1369 - 1367 1367 + dso->symbol_names_len = 0; 1368 1368 + zfree(&dso->symbol_names); 1370 1369 if (dso->short_name_allocated) { 1371 1370 zfree((char **)&dso->short_name); 1372 1371 dso->short_name_allocated = false;

+2 -1

tools/perf/util/dso.h

reviewed

··· 150 150 struct rb_node rb_node; /* rbtree node sorted by long name */ 151 151 struct rb_root *root; /* root of rbtree that rb_node is in */ 152 152 struct rb_root_cached symbols; 153 153 - struct rb_root_cached symbol_names; 153 153 + struct symbol **symbol_names; 154 154 + size_t symbol_names_len; 154 155 struct rb_root_cached inlined_nodes; 155 156 struct rb_root_cached srclines; 156 157 struct {

+2 -5

tools/perf/util/event.c

reviewed

··· 581 581 maps__zput(al->maps); 582 582 map__zput(al->map); 583 583 thread__zput(al->thread); 584 584 + al->thread = thread__get(thread); 584 585 585 586 al->addr = addr; 586 587 al->cpumode = cpumode; 587 588 al->filtered = 0; 588 589 589 589 - if (machine == NULL) { 590 590 - al->map = NULL; 590 590 + if (machine == NULL) 591 591 return NULL; 592 592 - } 593 592 594 593 if (cpumode == PERF_RECORD_MISC_KERNEL && perf_host) { 595 594 al->level = 'k'; ··· 604 605 al->level = 'u'; 605 606 } else { 606 607 al->level = 'H'; 607 607 - al->map = NULL; 608 608 609 609 if ((cpumode == PERF_RECORD_MISC_GUEST_USER || 610 610 cpumode == PERF_RECORD_MISC_GUEST_KERNEL) && ··· 617 619 return NULL; 618 620 } 619 621 al->maps = maps__get(maps); 620 620 - al->thread = thread__get(thread); 621 622 al->map = map__get(maps__find(maps, al->addr)); 622 623 if (al->map != NULL) { 623 624 /*

+9 -21

tools/perf/util/evsel.c

reviewed

··· 2924 2924 return ret ? false : true; 2925 2925 } 2926 2926 2927 2927 - static bool is_amd(const char *arch, const char *cpuid) 2927 2927 + int __weak arch_evsel__open_strerror(struct evsel *evsel __maybe_unused, 2928 2928 + char *msg __maybe_unused, 2929 2929 + size_t size __maybe_unused) 2928 2930 { 2929 2929 - return arch && !strcmp("x86", arch) && cpuid && strstarts(cpuid, "AuthenticAMD"); 2930 2930 - } 2931 2931 - 2932 2932 - static bool is_amd_ibs(struct evsel *evsel) 2933 2933 - { 2934 2934 - return evsel->core.attr.precise_ip 2935 2935 - || (evsel->pmu_name && !strncmp(evsel->pmu_name, "ibs", 3)); 2931 2931 + return 0; 2936 2932 } 2937 2933 2938 2934 int evsel__open_strerror(struct evsel *evsel, struct target *target, 2939 2935 int err, char *msg, size_t size) 2940 2936 { 2941 2941 - struct perf_env *env = evsel__env(evsel); 2942 2942 - const char *arch = perf_env__arch(env); 2943 2943 - const char *cpuid = perf_env__cpuid(env); 2944 2937 char sbuf[STRERR_BUFSIZE]; 2945 2938 int printed = 0, enforced = 0; 2939 2939 + int ret; 2946 2940 2947 2941 switch (err) { 2948 2942 case EPERM: ··· 3038 3044 return scnprintf(msg, size, 3039 3045 "Invalid event (%s) in per-thread mode, enable system wide with '-a'.", 3040 3046 evsel__name(evsel)); 3041 3041 - if (is_amd(arch, cpuid)) { 3042 3042 - if (is_amd_ibs(evsel)) { 3043 3043 - if (evsel->core.attr.exclude_kernel) 3044 3044 - return scnprintf(msg, size, 3045 3045 - "AMD IBS can't exclude kernel events. Try running at a higher privilege level."); 3046 3046 - if (!evsel->core.system_wide) 3047 3047 - return scnprintf(msg, size, 3048 3048 - "AMD IBS may only be available in system-wide/per-cpu mode. Try using -a, or -C and workload affinity"); 3049 3049 - } 3050 3050 - } 3051 3047 3052 3048 break; 3053 3049 case ENODATA: ··· 3046 3062 default: 3047 3063 break; 3048 3064 } 3065 3065 + 3066 3066 + ret = arch_evsel__open_strerror(evsel, msg, size); 3067 3067 + if (ret) 3068 3068 + return ret; 3049 3069 3050 3070 return scnprintf(msg, size, 3051 3071 "The sys_perf_event_open() syscall returned with %d (%s) for event (%s).\n"

+1

tools/perf/util/evsel.h

reviewed

··· 311 311 312 312 void arch_evsel__set_sample_weight(struct evsel *evsel); 313 313 void arch__post_evsel_config(struct evsel *evsel, struct perf_event_attr *attr); 314 314 + int arch_evsel__open_strerror(struct evsel *evsel, char *msg, size_t size); 314 315 315 316 int evsel__set_filter(struct evsel *evsel, const char *filter); 316 317 int evsel__append_tp_filter(struct evsel *evsel, const char *filter);

+21

tools/perf/util/expr.c

reviewed

··· 8 8 #include "cpumap.h" 9 9 #include "cputopo.h" 10 10 #include "debug.h" 11 11 + #include "evlist.h" 11 12 #include "expr.h" 12 13 #include "expr-bison.h" 13 14 #include "expr-flex.h" ··· 474 473 out: 475 474 pr_debug2("literal: %s = %f\n", literal, result); 476 475 return result; 476 476 + } 477 477 + 478 478 + /* Does the event 'id' parse? Determine via ctx->ids if possible. */ 479 479 + double expr__has_event(const struct expr_parse_ctx *ctx, bool compute_ids, const char *id) 480 480 + { 481 481 + struct evlist *tmp; 482 482 + double ret; 483 483 + 484 484 + if (hashmap__find(ctx->ids, id, /*value=*/NULL)) 485 485 + return 1.0; 486 486 + 487 487 + if (!compute_ids) 488 488 + return 0.0; 489 489 + 490 490 + tmp = evlist__new(); 491 491 + if (!tmp) 492 492 + return NAN; 493 493 + ret = parse_event(tmp, id) ? 0 : 1; 494 494 + evlist__delete(tmp); 495 495 + return ret; 477 496 }

+1

tools/perf/util/expr.h

reviewed

··· 54 54 double expr_id_data__value(const struct expr_id_data *data); 55 55 double expr_id_data__source_count(const struct expr_id_data *data); 56 56 double expr__get_literal(const char *literal, const struct expr_scanner_ctx *ctx); 57 57 + double expr__has_event(const struct expr_parse_ctx *ctx, bool compute_ids, const char *id); 57 58 58 59 #endif

+1

tools/perf/util/expr.l

reviewed

··· 113 113 if { return IF; } 114 114 else { return ELSE; } 115 115 source_count { return SOURCE_COUNT; } 116 116 + has_event { return HAS_EVENT; } 116 117 {literal} { return literal(yyscanner, sctx); } 117 118 {number} { return value(yyscanner); } 118 119 {symbol} { return str(yyscanner, ID, sctx->runtime); }

+7 -1

tools/perf/util/expr.y

reviewed

··· 37 37 } ids; 38 38 } 39 39 40 40 - %token ID NUMBER MIN MAX IF ELSE LITERAL D_RATIO SOURCE_COUNT EXPR_ERROR 40 40 + %token ID NUMBER MIN MAX IF ELSE LITERAL D_RATIO SOURCE_COUNT HAS_EVENT EXPR_ERROR 41 41 %left MIN MAX IF 42 42 %left '|' 43 43 %left '^' ··· 199 199 } 200 200 | ID { $$ = handle_id(ctx, $1, compute_ids, /*source_count=*/false); } 201 201 | SOURCE_COUNT '(' ID ')' { $$ = handle_id(ctx, $3, compute_ids, /*source_count=*/true); } 202 202 + | HAS_EVENT '(' ID ')' 203 203 + { 204 204 + $$.val = expr__has_event(ctx, compute_ids, $3); 205 205 + $$.ids = NULL; 206 206 + free($3); 207 207 + } 202 208 | expr '|' expr 203 209 { 204 210 if (is_const($1.val) && is_const($3.val)) {

+2 -2

tools/perf/util/llvm-utils.c

reviewed

··· 25 25 "$CLANG_OPTIONS $PERF_BPF_INC_OPTIONS $KERNEL_INC_OPTIONS " \ 26 26 "-Wno-unused-value -Wno-pointer-sign " \ 27 27 "-working-directory $WORKING_DIR " \ 28 28 - "-c \"$CLANG_SOURCE\" -target bpf $CLANG_EMIT_LLVM -g -O2 -o - $LLVM_OPTIONS_PIPE" 28 28 + "-c \"$CLANG_SOURCE\" --target=bpf $CLANG_EMIT_LLVM -g -O2 -o - $LLVM_OPTIONS_PIPE" 29 29 30 30 struct llvm_param llvm_param = { 31 31 .clang_path = "clang", ··· 569 569 pr_err("ERROR:\tunable to compile %s\n", path); 570 570 pr_err("Hint:\tCheck error message shown above.\n"); 571 571 pr_err("Hint:\tYou can also pre-compile it into .o using:\n"); 572 572 - pr_err(" \t\tclang -target bpf -O2 -c %s\n", path); 572 572 + pr_err(" \t\tclang --target=bpf -O2 -c %s\n", path); 573 573 pr_err(" \twith proper -I and -D options.\n"); 574 574 goto errout; 575 575 }

+10 -4

tools/perf/util/map.c

reviewed

··· 390 390 return dso__find_symbol(map__dso(map), addr); 391 391 } 392 392 393 393 - struct symbol *map__find_symbol_by_name(struct map *map, const char *name) 393 393 + struct symbol *map__find_symbol_by_name_idx(struct map *map, const char *name, size_t *idx) 394 394 { 395 395 struct dso *dso; 396 396 ··· 398 398 return NULL; 399 399 400 400 dso = map__dso(map); 401 401 - if (!dso__sorted_by_name(dso)) 402 402 - dso__sort_by_name(dso); 401 401 + dso__sort_by_name(dso); 403 402 404 404 - return dso__find_symbol_by_name(dso, name); 403 403 + return dso__find_symbol_by_name(dso, name, idx); 404 404 + } 405 405 + 406 406 + struct symbol *map__find_symbol_by_name(struct map *map, const char *name) 407 407 + { 408 408 + size_t idx; 409 409 + 410 410 + return map__find_symbol_by_name_idx(map, name, &idx); 405 411 } 406 412 407 413 struct map *map__clone(struct map *from)

+7 -5

tools/perf/util/map.h

reviewed

··· 148 148 * @map: the 'struct map *' in which symbols are iterated 149 149 * @sym_name: the symbol name 150 150 * @pos: the 'struct symbol *' to use as a loop cursor 151 151 + * @idx: the cursor index in the symbol names array 151 152 */ 152 152 - #define __map__for_each_symbol_by_name(map, sym_name, pos) \ 153 153 - for (pos = map__find_symbol_by_name(map, sym_name); \ 153 153 + #define __map__for_each_symbol_by_name(map, sym_name, pos, idx) \ 154 154 + for (pos = map__find_symbol_by_name_idx(map, sym_name, &idx); \ 154 155 pos && \ 155 156 !symbol__match_symbol_name(pos->name, sym_name, \ 156 157 SYMBOL_TAG_INCLUDE__DEFAULT_ONLY); \ 157 157 - pos = symbol__next_by_name(pos)) 158 158 + pos = dso__next_symbol_by_name(map__dso(map), &idx)) 158 159 159 159 - #define map__for_each_symbol_by_name(map, sym_name, pos) \ 160 160 - __map__for_each_symbol_by_name(map, sym_name, (pos)) 160 160 + #define map__for_each_symbol_by_name(map, sym_name, pos, idx) \ 161 161 + __map__for_each_symbol_by_name(map, sym_name, (pos), idx) 161 162 162 163 void map__init(struct map *map, 163 164 u64 start, u64 end, u64 pgoff, struct dso *dso); ··· 203 202 int map__load(struct map *map); 204 203 struct symbol *map__find_symbol(struct map *map, u64 addr); 205 204 struct symbol *map__find_symbol_by_name(struct map *map, const char *name); 205 205 + struct symbol *map__find_symbol_by_name_idx(struct map *map, const char *name, size_t *idx); 206 206 void map__fixup_start(struct map *map); 207 207 void map__fixup_end(struct map *map); 208 208

+177 -9

tools/perf/util/perf_event_attr_fprintf.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 #include <inttypes.h> 3 3 #include <stdio.h> 4 4 + #include <stdlib.h> 4 5 #include <stdbool.h> 5 6 #include <linux/kernel.h> 6 7 #include <linux/types.h> 7 8 #include <linux/perf_event.h> 8 9 #include "util/evsel_fprintf.h" 10 10 + #include "trace-event.h" 9 11 10 12 struct bit_names { 11 13 int bit; ··· 73 71 __p_bits(buf, size, value, bits); 74 72 } 75 73 74 74 + #define ENUM_ID_TO_STR_CASE(x) case x: return (#x); 75 75 + static const char *stringify_perf_type_id(u64 value) 76 76 + { 77 77 + switch (value) { 78 78 + ENUM_ID_TO_STR_CASE(PERF_TYPE_HARDWARE) 79 79 + ENUM_ID_TO_STR_CASE(PERF_TYPE_SOFTWARE) 80 80 + ENUM_ID_TO_STR_CASE(PERF_TYPE_TRACEPOINT) 81 81 + ENUM_ID_TO_STR_CASE(PERF_TYPE_HW_CACHE) 82 82 + ENUM_ID_TO_STR_CASE(PERF_TYPE_RAW) 83 83 + ENUM_ID_TO_STR_CASE(PERF_TYPE_BREAKPOINT) 84 84 + default: 85 85 + return NULL; 86 86 + } 87 87 + } 88 88 + 89 89 + static const char *stringify_perf_hw_id(u64 value) 90 90 + { 91 91 + switch (value) { 92 92 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CPU_CYCLES) 93 93 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_INSTRUCTIONS) 94 94 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_REFERENCES) 95 95 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_MISSES) 96 96 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_BRANCH_INSTRUCTIONS) 97 97 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_BRANCH_MISSES) 98 98 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_BUS_CYCLES) 99 99 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_STALLED_CYCLES_FRONTEND) 100 100 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_STALLED_CYCLES_BACKEND) 101 101 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_REF_CPU_CYCLES) 102 102 + default: 103 103 + return NULL; 104 104 + } 105 105 + } 106 106 + 107 107 + static const char *stringify_perf_hw_cache_id(u64 value) 108 108 + { 109 109 + switch (value) { 110 110 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_L1D) 111 111 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_L1I) 112 112 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_LL) 113 113 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_DTLB) 114 114 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_ITLB) 115 115 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_BPU) 116 116 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_NODE) 117 117 + default: 118 118 + return NULL; 119 119 + } 120 120 + } 121 121 + 122 122 + static const char *stringify_perf_hw_cache_op_id(u64 value) 123 123 + { 124 124 + switch (value) { 125 125 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_OP_READ) 126 126 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_OP_WRITE) 127 127 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_OP_PREFETCH) 128 128 + default: 129 129 + return NULL; 130 130 + } 131 131 + } 132 132 + 133 133 + static const char *stringify_perf_hw_cache_op_result_id(u64 value) 134 134 + { 135 135 + switch (value) { 136 136 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_RESULT_ACCESS) 137 137 + ENUM_ID_TO_STR_CASE(PERF_COUNT_HW_CACHE_RESULT_MISS) 138 138 + default: 139 139 + return NULL; 140 140 + } 141 141 + } 142 142 + 143 143 + static const char *stringify_perf_sw_id(u64 value) 144 144 + { 145 145 + switch (value) { 146 146 + ENUM_ID_TO_STR_CASE(PERF_COUNT_SW_CPU_CLOCK) 147 147 + ENUM_ID_TO_STR_CASE(PERF_COUNT_SW_TASK_CLOCK) 148 148 + ENUM_ID_TO_STR_CASE(PERF_COUNT_SW_PAGE_FAULTS) 149 149 + ENUM_ID_TO_STR_CASE(PERF_COUNT_SW_CONTEXT_SWITCHES) 150 150 + ENUM_ID_TO_STR_CASE(PERF_COUNT_SW_CPU_MIGRATIONS) 151 151 + ENUM_ID_TO_STR_CASE(PERF_COUNT_SW_PAGE_FAULTS_MIN) 152 152 + ENUM_ID_TO_STR_CASE(PERF_COUNT_SW_PAGE_FAULTS_MAJ) 153 153 + ENUM_ID_TO_STR_CASE(PERF_COUNT_SW_ALIGNMENT_FAULTS) 154 154 + ENUM_ID_TO_STR_CASE(PERF_COUNT_SW_EMULATION_FAULTS) 155 155 + ENUM_ID_TO_STR_CASE(PERF_COUNT_SW_DUMMY) 156 156 + ENUM_ID_TO_STR_CASE(PERF_COUNT_SW_BPF_OUTPUT) 157 157 + ENUM_ID_TO_STR_CASE(PERF_COUNT_SW_CGROUP_SWITCHES) 158 158 + default: 159 159 + return NULL; 160 160 + } 161 161 + } 162 162 + #undef ENUM_ID_TO_STR_CASE 163 163 + 164 164 + #define PRINT_ID(_s, _f) \ 165 165 + do { \ 166 166 + const char *__s = _s; \ 167 167 + if (__s == NULL) \ 168 168 + snprintf(buf, size, _f, value); \ 169 169 + else \ 170 170 + snprintf(buf, size, _f" (%s)", value, __s); \ 171 171 + } while (0) 172 172 + #define print_id_unsigned(_s) PRINT_ID(_s, "%"PRIu64) 173 173 + #define print_id_hex(_s) PRINT_ID(_s, "%#"PRIx64) 174 174 + 175 175 + static void __p_type_id(char *buf, size_t size, u64 value) 176 176 + { 177 177 + print_id_unsigned(stringify_perf_type_id(value)); 178 178 + } 179 179 + 180 180 + static void __p_config_hw_id(char *buf, size_t size, u64 value) 181 181 + { 182 182 + print_id_hex(stringify_perf_hw_id(value)); 183 183 + } 184 184 + 185 185 + static void __p_config_sw_id(char *buf, size_t size, u64 value) 186 186 + { 187 187 + print_id_hex(stringify_perf_sw_id(value)); 188 188 + } 189 189 + 190 190 + static void __p_config_hw_cache_id(char *buf, size_t size, u64 value) 191 191 + { 192 192 + const char *hw_cache_str = stringify_perf_hw_cache_id(value & 0xff); 193 193 + const char *hw_cache_op_str = 194 194 + stringify_perf_hw_cache_op_id((value & 0xff00) >> 8); 195 195 + const char *hw_cache_op_result_str = 196 196 + stringify_perf_hw_cache_op_result_id((value & 0xff0000) >> 16); 197 197 + 198 198 + if (hw_cache_str == NULL || hw_cache_op_str == NULL || 199 199 + hw_cache_op_result_str == NULL) { 200 200 + snprintf(buf, size, "%#"PRIx64, value); 201 201 + } else { 202 202 + snprintf(buf, size, "%#"PRIx64" (%s | %s | %s)", value, 203 203 + hw_cache_op_result_str, hw_cache_op_str, hw_cache_str); 204 204 + } 205 205 + } 206 206 + 207 207 + #ifdef HAVE_LIBTRACEEVENT 208 208 + static void __p_config_tracepoint_id(char *buf, size_t size, u64 value) 209 209 + { 210 210 + char *str = tracepoint_id_to_name(value); 211 211 + 212 212 + print_id_hex(str); 213 213 + free(str); 214 214 + } 215 215 + #endif 216 216 + 217 217 + static void __p_config_id(char *buf, size_t size, u32 type, u64 value) 218 218 + { 219 219 + switch (type) { 220 220 + case PERF_TYPE_HARDWARE: 221 221 + return __p_config_hw_id(buf, size, value); 222 222 + case PERF_TYPE_SOFTWARE: 223 223 + return __p_config_sw_id(buf, size, value); 224 224 + case PERF_TYPE_HW_CACHE: 225 225 + return __p_config_hw_cache_id(buf, size, value); 226 226 + case PERF_TYPE_TRACEPOINT: 227 227 + #ifdef HAVE_LIBTRACEEVENT 228 228 + return __p_config_tracepoint_id(buf, size, value); 229 229 + #endif 230 230 + case PERF_TYPE_RAW: 231 231 + case PERF_TYPE_BREAKPOINT: 232 232 + default: 233 233 + snprintf(buf, size, "%#"PRIx64, value); 234 234 + return; 235 235 + } 236 236 + } 237 237 + 76 238 #define BUF_SIZE 1024 77 239 78 240 #define p_hex(val) snprintf(buf, BUF_SIZE, "%#"PRIx64, (uint64_t)(val)) ··· 245 79 #define p_sample_type(val) __p_sample_type(buf, BUF_SIZE, val) 246 80 #define p_branch_sample_type(val) __p_branch_sample_type(buf, BUF_SIZE, val) 247 81 #define p_read_format(val) __p_read_format(buf, BUF_SIZE, val) 82 82 + #define p_type_id(val) __p_type_id(buf, BUF_SIZE, val) 83 83 + #define p_config_id(val) __p_config_id(buf, BUF_SIZE, attr->type, val) 248 84 249 249 - #define PRINT_ATTRn(_n, _f, _p) \ 85 85 + #define PRINT_ATTRn(_n, _f, _p, _a) \ 250 86 do { \ 251 251 - if (attr->_f) { \ 87 87 + if (_a || attr->_f) { \ 252 88 _p(attr->_f); \ 253 89 ret += attr__fprintf(fp, _n, buf, priv);\ 254 90 } \ 255 91 } while (0) 256 92 257 257 - #define PRINT_ATTRf(_f, _p) PRINT_ATTRn(#_f, _f, _p) 93 93 + #define PRINT_ATTRf(_f, _p) PRINT_ATTRn(#_f, _f, _p, false) 258 94 259 95 int perf_event_attr__fprintf(FILE *fp, struct perf_event_attr *attr, 260 96 attr__fprintf_f attr__fprintf, void *priv) ··· 264 96 char buf[BUF_SIZE]; 265 97 int ret = 0; 266 98 267 267 - PRINT_ATTRf(type, p_unsigned); 99 99 + PRINT_ATTRn("type", type, p_type_id, true); 268 100 PRINT_ATTRf(size, p_unsigned); 269 269 - PRINT_ATTRf(config, p_hex); 270 270 - PRINT_ATTRn("{ sample_period, sample_freq }", sample_period, p_unsigned); 101 101 + PRINT_ATTRn("config", config, p_config_id, true); 102 102 + PRINT_ATTRn("{ sample_period, sample_freq }", sample_period, p_unsigned, false); 271 103 PRINT_ATTRf(sample_type, p_sample_type); 272 104 PRINT_ATTRf(read_format, p_read_format); 273 105 ··· 309 141 PRINT_ATTRf(remove_on_exec, p_unsigned); 310 142 PRINT_ATTRf(sigtrap, p_unsigned); 311 143 312 312 - PRINT_ATTRn("{ wakeup_events, wakeup_watermark }", wakeup_events, p_unsigned); 144 144 + PRINT_ATTRn("{ wakeup_events, wakeup_watermark }", wakeup_events, p_unsigned, false); 313 145 PRINT_ATTRf(bp_type, p_unsigned); 314 314 - PRINT_ATTRn("{ bp_addr, config1 }", bp_addr, p_hex); 315 315 - PRINT_ATTRn("{ bp_len, config2 }", bp_len, p_hex); 146 146 + PRINT_ATTRn("{ bp_addr, config1 }", bp_addr, p_hex, false); 147 147 + PRINT_ATTRn("{ bp_len, config2 }", bp_len, p_hex, false); 316 148 PRINT_ATTRf(branch_sample_type, p_branch_sample_type); 317 149 PRINT_ATTRf(sample_regs_user, p_hex); 318 150 PRINT_ATTRf(sample_stack_user, p_unsigned);

+26 -1

tools/perf/util/pmu.c

reviewed

··· 928 928 return NULL; 929 929 } 930 930 931 931 + /* Creates the PMU when sysfs scanning fails. */ 932 932 + struct perf_pmu *perf_pmu__create_placeholder_core_pmu(struct list_head *core_pmus) 933 933 + { 934 934 + struct perf_pmu *pmu = zalloc(sizeof(*pmu)); 935 935 + 936 936 + if (!pmu) 937 937 + return NULL; 938 938 + 939 939 + pmu->name = strdup("cpu"); 940 940 + if (!pmu->name) { 941 941 + free(pmu); 942 942 + return NULL; 943 943 + } 944 944 + 945 945 + pmu->is_core = true; 946 946 + pmu->type = PERF_TYPE_RAW; 947 947 + pmu->cpus = cpu_map__online(); 948 948 + 949 949 + INIT_LIST_HEAD(&pmu->format); 950 950 + INIT_LIST_HEAD(&pmu->aliases); 951 951 + INIT_LIST_HEAD(&pmu->caps); 952 952 + list_add_tail(&pmu->list, core_pmus); 953 953 + return pmu; 954 954 + } 955 955 + 931 956 void perf_pmu__warn_invalid_formats(struct perf_pmu *pmu) 932 957 { 933 958 struct perf_pmu_format *format; ··· 1452 1427 1453 1428 bool perf_pmu__auto_merge_stats(const struct perf_pmu *pmu) 1454 1429 { 1455 1455 - return pmu->is_core && perf_pmus__num_core_pmus() == 1; 1430 1430 + return !pmu->is_core || perf_pmus__num_core_pmus() == 1; 1456 1431 } 1457 1432 1458 1433 bool perf_pmu__have_event(const struct perf_pmu *pmu, const char *name)

+1

tools/perf/util/pmu.h

reviewed

··· 286 286 int perf_pmu__pathname_fd(int dirfd, const char *pmu_name, const char *filename, int flags); 287 287 288 288 struct perf_pmu *perf_pmu__lookup(struct list_head *pmus, int dirfd, const char *lookup_name); 289 289 + struct perf_pmu *perf_pmu__create_placeholder_core_pmu(struct list_head *core_pmus); 289 290 void perf_pmu__delete(struct perf_pmu *pmu); 290 291 291 292 #endif /* __PMU_H */

+6 -1

tools/perf/util/pmus.c

reviewed

··· 153 153 154 154 closedir(dir); 155 155 if (core_only) { 156 156 - read_sysfs_core_pmus = true; 156 156 + if (!list_empty(&core_pmus)) 157 157 + read_sysfs_core_pmus = true; 158 158 + else { 159 159 + if (perf_pmu__create_placeholder_core_pmu(&core_pmus)) 160 160 + read_sysfs_core_pmus = true; 161 161 + } 157 162 } else { 158 163 read_sysfs_core_pmus = true; 159 164 read_sysfs_all_pmus = true;

+7 -9

tools/perf/util/probe-event.c

reviewed

··· 74 74 { 75 75 int ret; 76 76 77 77 - symbol_conf.sort_by_name = true; 78 77 symbol_conf.allow_aliases = true; 79 78 ret = symbol__init(NULL); 80 79 if (ret < 0) { ··· 381 382 struct symbol *sym; 382 383 u64 address = 0; 383 384 int ret = -ENOENT; 385 385 + size_t idx; 384 386 385 387 /* This can work only for function-name based one */ 386 388 if (!pp->function || pp->file) ··· 392 392 return -EINVAL; 393 393 394 394 /* Find the address of given function */ 395 395 - map__for_each_symbol_by_name(map, pp->function, sym) { 395 395 + map__for_each_symbol_by_name(map, pp->function, sym, idx) { 396 396 if (uprobes) { 397 397 address = sym->start; 398 398 if (sym->type == STT_GNU_IFUNC) ··· 3738 3738 int show_available_funcs(const char *target, struct nsinfo *nsi, 3739 3739 struct strfilter *_filter, bool user) 3740 3740 { 3741 3741 - struct rb_node *nd; 3742 3741 struct map *map; 3743 3742 struct dso *dso; 3744 3743 int ret; ··· 3766 3767 goto end; 3767 3768 } 3768 3769 dso = map__dso(map); 3769 3769 - if (!dso__sorted_by_name(dso)) 3770 3770 - dso__sort_by_name(dso); 3770 3770 + dso__sort_by_name(dso); 3771 3771 3772 3772 /* Show all (filtered) symbols */ 3773 3773 setup_pager(); 3774 3774 3775 3775 - for (nd = rb_first_cached(&dso->symbol_names); nd; nd = rb_next(nd)) { 3776 3776 - struct symbol_name_rb_node *pos = rb_entry(nd, struct symbol_name_rb_node, rb_node); 3775 3775 + for (size_t i = 0; i < dso->symbol_names_len; i++) { 3776 3776 + struct symbol *pos = dso->symbol_names[i]; 3777 3777 3778 3778 - if (strfilter__compare(_filter, pos->sym.name)) 3779 3779 - printf("%s\n", pos->sym.name); 3778 3778 + if (strfilter__compare(_filter, pos->name)) 3779 3779 + printf("%s\n", pos->name); 3780 3780 } 3781 3781 end: 3782 3782 map__put(map);

+8

tools/perf/util/python.c

reviewed

··· 124 124 } 125 125 126 126 /* 127 127 + * Add this one here not to drag util/trace-event-info.c 128 128 + */ 129 129 + char *tracepoint_id_to_name(u64 config) 130 130 + { 131 131 + return NULL; 132 132 + } 133 133 + 134 134 + /* 127 135 * XXX: All these evsel destructors need some better mechanism, like a linked 128 136 * list of destructors registered when the relevant code indeed is used instead 129 137 * of having more and more calls in perf_evsel__delete(). -- acme

+74 -66

tools/perf/util/symbol.c

reviewed

··· 440 440 return NULL; 441 441 } 442 442 443 443 - static void symbols__insert_by_name(struct rb_root_cached *symbols, struct symbol *sym) 443 443 + static int symbols__sort_name_cmp(const void *vlhs, const void *vrhs) 444 444 { 445 445 - struct rb_node **p = &symbols->rb_root.rb_node; 446 446 - struct rb_node *parent = NULL; 447 447 - struct symbol_name_rb_node *symn, *s; 448 448 - bool leftmost = true; 445 445 + const struct symbol *lhs = *((const struct symbol **)vlhs); 446 446 + const struct symbol *rhs = *((const struct symbol **)vrhs); 449 447 450 450 - symn = container_of(sym, struct symbol_name_rb_node, sym); 451 451 - 452 452 - while (*p != NULL) { 453 453 - parent = *p; 454 454 - s = rb_entry(parent, struct symbol_name_rb_node, rb_node); 455 455 - if (strcmp(sym->name, s->sym.name) < 0) 456 456 - p = &(*p)->rb_left; 457 457 - else { 458 458 - p = &(*p)->rb_right; 459 459 - leftmost = false; 460 460 - } 461 461 - } 462 462 - rb_link_node(&symn->rb_node, parent, p); 463 463 - rb_insert_color_cached(&symn->rb_node, symbols, leftmost); 448 448 + return strcmp(lhs->name, rhs->name); 464 449 } 465 450 466 466 - static void symbols__sort_by_name(struct rb_root_cached *symbols, 467 467 - struct rb_root_cached *source) 451 451 + static struct symbol **symbols__sort_by_name(struct rb_root_cached *source, size_t *len) 468 452 { 469 453 struct rb_node *nd; 454 454 + struct symbol **result; 455 455 + size_t i = 0, size = 0; 456 456 + 457 457 + for (nd = rb_first_cached(source); nd; nd = rb_next(nd)) 458 458 + size++; 459 459 + 460 460 + result = malloc(sizeof(*result) * size); 461 461 + if (!result) 462 462 + return NULL; 470 463 471 464 for (nd = rb_first_cached(source); nd; nd = rb_next(nd)) { 472 465 struct symbol *pos = rb_entry(nd, struct symbol, rb_node); 473 473 - symbols__insert_by_name(symbols, pos); 466 466 + 467 467 + result[i++] = pos; 474 468 } 469 469 + qsort(result, size, sizeof(*result), symbols__sort_name_cmp); 470 470 + *len = size; 471 471 + return result; 475 472 } 476 473 477 474 int symbol__match_symbol_name(const char *name, const char *str, ··· 488 491 return arch__compare_symbol_names(name, str); 489 492 } 490 493 491 491 - static struct symbol *symbols__find_by_name(struct rb_root_cached *symbols, 494 494 + static struct symbol *symbols__find_by_name(struct symbol *symbols[], 495 495 + size_t symbols_len, 492 496 const char *name, 493 493 - enum symbol_tag_include includes) 497 497 + enum symbol_tag_include includes, 498 498 + size_t *found_idx) 494 499 { 495 495 - struct rb_node *n; 496 496 - struct symbol_name_rb_node *s = NULL; 500 500 + size_t i, lower = 0, upper = symbols_len; 501 501 + struct symbol *s = NULL; 497 502 498 498 - if (symbols == NULL) 503 503 + if (found_idx) 504 504 + *found_idx = SIZE_MAX; 505 505 + 506 506 + if (!symbols_len) 499 507 return NULL; 500 508 501 501 - n = symbols->rb_root.rb_node; 502 502 - 503 503 - while (n) { 509 509 + while (lower < upper) { 504 510 int cmp; 505 511 506 506 - s = rb_entry(n, struct symbol_name_rb_node, rb_node); 507 507 - cmp = symbol__match_symbol_name(s->sym.name, name, includes); 512 512 + i = (lower + upper) / 2; 513 513 + cmp = symbol__match_symbol_name(symbols[i]->name, name, includes); 508 514 509 515 if (cmp > 0) 510 510 - n = n->rb_left; 516 516 + upper = i; 511 517 else if (cmp < 0) 512 512 - n = n->rb_right; 513 513 - else 518 518 + lower = i + 1; 519 519 + else { 520 520 + if (found_idx) 521 521 + *found_idx = i; 522 522 + s = symbols[i]; 514 523 break; 515 515 - } 516 516 - 517 517 - if (n == NULL) 518 518 - return NULL; 519 519 - 520 520 - if (includes != SYMBOL_TAG_INCLUDE__DEFAULT_ONLY) 521 521 - /* return first symbol that has same name (if any) */ 522 522 - for (n = rb_prev(n); n; n = rb_prev(n)) { 523 523 - struct symbol_name_rb_node *tmp; 524 524 - 525 525 - tmp = rb_entry(n, struct symbol_name_rb_node, rb_node); 526 526 - if (arch__compare_symbol_names(tmp->sym.name, s->sym.name)) 527 527 - break; 528 528 - 529 529 - s = tmp; 530 524 } 525 525 + } 526 526 + if (s && includes != SYMBOL_TAG_INCLUDE__DEFAULT_ONLY) { 527 527 + /* return first symbol that has same name (if any) */ 528 528 + for (; i > 0; i--) { 529 529 + struct symbol *tmp = symbols[i - 1]; 531 530 532 532 - return &s->sym; 531 531 + if (!arch__compare_symbol_names(tmp->name, s->name)) { 532 532 + if (found_idx) 533 533 + *found_idx = i - 1; 534 534 + s = tmp; 535 535 + } else 536 536 + break; 537 537 + } 538 538 + } 539 539 + assert(!found_idx || !s || s == symbols[*found_idx]); 540 540 + return s; 533 541 } 534 542 535 543 void dso__reset_find_symbol_cache(struct dso *dso) ··· 592 590 return symbols__next(sym); 593 591 } 594 592 595 595 - struct symbol *symbol__next_by_name(struct symbol *sym) 593 593 + struct symbol *dso__next_symbol_by_name(struct dso *dso, size_t *idx) 596 594 { 597 597 - struct symbol_name_rb_node *s = container_of(sym, struct symbol_name_rb_node, sym); 598 598 - struct rb_node *n = rb_next(&s->rb_node); 595 595 + if (*idx + 1 >= dso->symbol_names_len) 596 596 + return NULL; 599 597 600 600 - return n ? &rb_entry(n, struct symbol_name_rb_node, rb_node)->sym : NULL; 598 598 + ++*idx; 599 599 + return dso->symbol_names[*idx]; 601 600 } 602 601 603 602 /* 604 603 * Returns first symbol that matched with @name. 605 604 */ 606 606 - struct symbol *dso__find_symbol_by_name(struct dso *dso, const char *name) 605 605 + struct symbol *dso__find_symbol_by_name(struct dso *dso, const char *name, size_t *idx) 607 606 { 608 608 - struct symbol *s = symbols__find_by_name(&dso->symbol_names, name, 609 609 - SYMBOL_TAG_INCLUDE__NONE); 607 607 + struct symbol *s = symbols__find_by_name(dso->symbol_names, dso->symbol_names_len, 608 608 + name, SYMBOL_TAG_INCLUDE__NONE, idx); 610 609 if (!s) 611 611 - s = symbols__find_by_name(&dso->symbol_names, name, 612 612 - SYMBOL_TAG_INCLUDE__DEFAULT_ONLY); 610 610 + s = symbols__find_by_name(dso->symbol_names, dso->symbol_names_len, 611 611 + name, SYMBOL_TAG_INCLUDE__DEFAULT_ONLY, idx); 613 612 return s; 614 613 } 615 614 616 615 void dso__sort_by_name(struct dso *dso) 617 616 { 618 618 - dso__set_sorted_by_name(dso); 619 619 - return symbols__sort_by_name(&dso->symbol_names, &dso->symbols); 617 617 + mutex_lock(&dso->lock); 618 618 + if (!dso__sorted_by_name(dso)) { 619 619 + size_t len; 620 620 + 621 621 + dso->symbol_names = symbols__sort_by_name(&dso->symbols, &len); 622 622 + if (dso->symbol_names) { 623 623 + dso->symbol_names_len = len; 624 624 + dso__set_sorted_by_name(dso); 625 625 + } 626 626 + } 627 627 + mutex_unlock(&dso->lock); 620 628 } 621 629 622 630 /* ··· 2667 2655 symbol_conf.priv_size = PERF_ALIGN(symbol_conf.priv_size, sizeof(u64)); 2668 2656 2669 2657 symbol__elf_init(); 2670 2670 - 2671 2671 - if (symbol_conf.sort_by_name) 2672 2672 - symbol_conf.priv_size += (sizeof(struct symbol_name_rb_node) - 2673 2673 - sizeof(struct symbol)); 2674 2658 2675 2659 if (symbol_conf.try_vmlinux_path && vmlinux_path__init(env) < 0) 2676 2660 return -1;

+3 -9

tools/perf/util/symbol.h

reviewed

··· 43 43 44 44 /** 45 45 * A symtab entry. When allocated this may be preceded by an annotation (see 46 46 - * symbol__annotation), a browser_index (see symbol__browser_index) and rb_node 47 47 - * to sort by name (see struct symbol_name_rb_node). 46 46 + * symbol__annotation) and/or a browser_index (see symbol__browser_index). 48 47 */ 49 48 struct symbol { 50 49 struct rb_node rb_node; ··· 94 95 struct strlist; 95 96 struct intlist; 96 97 97 97 - struct symbol_name_rb_node { 98 98 - struct rb_node rb_node; 99 99 - struct symbol sym; 100 100 - }; 101 101 - 102 98 static inline int __symbol__join_symfs(char *bf, size_t size, const char *path) 103 99 { 104 100 return path__join(bf, size, symbol_conf.symfs, path); ··· 130 136 131 137 struct symbol *dso__find_symbol(struct dso *dso, u64 addr); 132 138 struct symbol *dso__find_symbol_nocache(struct dso *dso, u64 addr); 133 133 - struct symbol *dso__find_symbol_by_name(struct dso *dso, const char *name); 134 139 135 135 - struct symbol *symbol__next_by_name(struct symbol *sym); 140 140 + struct symbol *dso__next_symbol_by_name(struct dso *dso, size_t *idx); 141 141 + struct symbol *dso__find_symbol_by_name(struct dso *dso, const char *name, size_t *idx); 136 142 137 143 struct symbol *dso__first_symbol(struct dso *dso); 138 144 struct symbol *dso__last_symbol(struct dso *dso);

-1

tools/perf/util/symbol_conf.h

reviewed

··· 18 18 show_kernel_path, 19 19 use_modules, 20 20 allow_aliases, 21 21 - sort_by_name, 22 21 show_nr_samples, 23 22 show_total_period, 24 23 use_callchain,

+4 -6

tools/perf/util/symbol_fprintf.c

reviewed

··· 63 63 FILE *fp) 64 64 { 65 65 size_t ret = 0; 66 66 - struct rb_node *nd; 67 67 - struct symbol_name_rb_node *pos; 68 66 69 69 - for (nd = rb_first_cached(&dso->symbol_names); nd; nd = rb_next(nd)) { 70 70 - pos = rb_entry(nd, struct symbol_name_rb_node, rb_node); 71 71 - ret += fprintf(fp, "%s\n", pos->sym.name); 67 67 + for (size_t i = 0; i < dso->symbol_names_len; i++) { 68 68 + struct symbol *pos = dso->symbol_names[i]; 69 69 + 70 70 + ret += fprintf(fp, "%s\n", pos->name); 72 71 } 73 73 - 74 72 return ret; 75 73 }

+12

tools/perf/util/trace-event-info.c

reviewed

··· 466 466 return NULL; 467 467 } 468 468 469 469 + char *tracepoint_id_to_name(u64 config) 470 470 + { 471 471 + struct tracepoint_path *path = tracepoint_id_to_path(config); 472 472 + char *buf = NULL; 473 473 + 474 474 + if (path && asprintf(&buf, "%s:%s", path->system, path->name) < 0) 475 475 + buf = NULL; 476 476 + 477 477 + put_tracepoints_path(path); 478 478 + return buf; 479 479 + } 480 480 + 469 481 static struct tracepoint_path *tracepoint_name_to_path(const char *name) 470 482 { 471 483 struct tracepoint_path *path = zalloc(sizeof(*path));

+6

tools/perf/util/trace-event.h

reviewed

··· 62 62 63 63 int read_tracing_data(int fd, struct list_head *pattrs); 64 64 65 65 + /* 66 66 + * Return the tracepoint name in the format "subsystem:event_name", 67 67 + * callers should free the returned string. 68 68 + */ 69 69 + char *tracepoint_id_to_name(u64 config); 70 70 + 65 71 struct tracing_data { 66 72 /* size is only valid if temp is 'true' */ 67 73 ssize_t size;

+6 -2

tools/perf/util/unwind-libdw.c

reviewed

··· 66 66 mod = 0; 67 67 } 68 68 69 69 - if (!mod) 70 70 - mod = dwfl_report_elf(ui->dwfl, dso->short_name, dso->long_name, -1, 69 69 + if (!mod) { 70 70 + char filename[PATH_MAX]; 71 71 + 72 72 + __symbol__join_symfs(filename, sizeof(filename), dso->long_name); 73 73 + mod = dwfl_report_elf(ui->dwfl, dso->short_name, filename, -1, 71 74 map__start(al->map) - map__pgoff(al->map), false); 75 75 + } 72 76 if (!mod) { 73 77 char filename[PATH_MAX]; 74 78