tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon:
"Here are another three arm64 fixes for 5.6, all pretty minor. Main
thing is fixing a silly bug in the fsl_imx8_ddr PMU driver where we
would zero the counters when disabling them.

- Fix misreporting of ASID limit when KPTI is enabled

- Fix busted NULL pointer checks for GICC structure in ACPI PMU code

- Avoid nobbling the "fsl_imx8_ddr" PMU counters when disabling them"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: context: Fix ASID limit in boot messages
drivers/perf: arm_pmu_acpi: Fix incorrect checking of gicc pointer
drivers/perf: fsl_imx8_ddr: Correct the CLEAR bit definition

Linus Torvalds c20c4a08 aeb542a1

+23 -14
+15 -5
arch/arm64/mm/context.c
··· 260 260 CONFIG_CAVIUM_ERRATUM_27456)); 261 261 } 262 262 263 - static int asids_init(void) 263 + static int asids_update_limit(void) 264 264 { 265 - asid_bits = get_cpu_asid_bits(); 265 + unsigned long num_available_asids = NUM_USER_ASIDS; 266 + 267 + if (arm64_kernel_unmapped_at_el0()) 268 + num_available_asids /= 2; 266 269 /* 267 270 * Expect allocation after rollover to fail if we don't have at least 268 271 * one more ASID than CPUs. ASID #0 is reserved for init_mm. 269 272 */ 270 - WARN_ON(NUM_USER_ASIDS - 1 <= num_possible_cpus()); 273 + WARN_ON(num_available_asids - 1 <= num_possible_cpus()); 274 + pr_info("ASID allocator initialised with %lu entries\n", 275 + num_available_asids); 276 + return 0; 277 + } 278 + arch_initcall(asids_update_limit); 279 + 280 + static int asids_init(void) 281 + { 282 + asid_bits = get_cpu_asid_bits(); 271 283 atomic64_set(&asid_generation, ASID_FIRST_VERSION); 272 284 asid_map = kcalloc(BITS_TO_LONGS(NUM_USER_ASIDS), sizeof(*asid_map), 273 285 GFP_KERNEL); ··· 294 282 */ 295 283 if (IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) 296 284 set_kpti_asid_bits(); 297 - 298 - pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS); 299 285 return 0; 300 286 } 301 287 early_initcall(asids_init);
+2 -5
drivers/perf/arm_pmu_acpi.c
··· 24 24 int gsi, trigger; 25 25 26 26 gicc = acpi_cpu_get_madt_gicc(cpu); 27 - if (WARN_ON(!gicc)) 28 - return -EINVAL; 29 27 30 28 gsi = gicc->performance_interrupt; 31 29 ··· 62 64 int gsi; 63 65 64 66 gicc = acpi_cpu_get_madt_gicc(cpu); 65 - if (!gicc) 66 - return; 67 67 68 68 gsi = gicc->performance_interrupt; 69 - acpi_unregister_gsi(gsi); 69 + if (gsi) 70 + acpi_unregister_gsi(gsi); 70 71 } 71 72 72 73 #if IS_ENABLED(CONFIG_ARM_SPE_PMU)
+6 -4
drivers/perf/fsl_imx8_ddr_perf.c
··· 388 388 389 389 if (enable) { 390 390 /* 391 - * must disable first, then enable again 392 - * otherwise, cycle counter will not work 393 - * if previous state is enabled. 391 + * cycle counter is special which should firstly write 0 then 392 + * write 1 into CLEAR bit to clear it. Other counters only 393 + * need write 0 into CLEAR bit and it turns out to be 1 by 394 + * hardware. Below enable flow is harmless for all counters. 394 395 */ 395 396 writel(0, pmu->base + reg); 396 397 val = CNTL_EN | CNTL_CLEAR; ··· 399 398 writel(val, pmu->base + reg); 400 399 } else { 401 400 /* Disable counter */ 402 - writel(0, pmu->base + reg); 401 + val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; 402 + writel(val, pmu->base + reg); 403 403 } 404 404 } 405 405