Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu/gfx9: Implement cleaner shader support for GFX9 hardware
The patch modifies the gfx_v9_0_kiq_set_resources function to write
the cleaner shader's memory controller address to the ring buffer. It
also adds a new function, gfx_v9_0_ring_emit_cleaner_shader, which
emits the PACKET3_RUN_CLEANER_SHADER packet to the ring buffer.
This patch adds support for the PACKET3_RUN_CLEANER_SHADER packet in the
gfx_v9_0 module. This packet is used to emit the cleaner shader, which
is used to clear GPU memory before it's reused, helping to prevent data
leakage between different processes.
Finally, the patch updates the ring function structures to include the
new gfx_v9_0_ring_emit_cleaner_shader function. This allows the
cleaner shader to be emitted as part of the ring's operations.
Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Srinivasan Shanmugam
and committed by
Alex Deucher
c2e70d30
22ff907d
+66
-5
+40
-5
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+40
-5
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
···
50
50
#include "amdgpu_ring_mux.h"
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51
#include "gfx_v9_4.h"
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#include "gfx_v9_0.h"
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+
#include "gfx_v9_0_cleaner_shader.h"
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#include "gfx_v9_4_2.h"
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#include "asic_reg/pwr/pwr_10_0_offset.h"
···
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899
static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring,
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uint64_t queue_mask)
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901
{
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struct amdgpu_device *adev = kiq_ring->adev;
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+
u64 shader_mc_addr;
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+
905
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/* Cleaner shader MC address */
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+
shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8;
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+
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amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
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amdgpu_ring_write(kiq_ring,
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PACKET3_SET_RESOURCES_VMID_MASK(0) |
···
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908
lower_32_bits(queue_mask)); /* queue mask lo */
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amdgpu_ring_write(kiq_ring,
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upper_32_bits(queue_mask)); /* queue mask hi */
918
-
amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
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-
amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
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+
amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
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+
amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */
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amdgpu_ring_write(kiq_ring, 0); /* oac mask */
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amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
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}
···
2218
2211
break;
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}
2220
2213
2214
+
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2215
+
default:
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+
adev->gfx.enable_cleaner_shader = false;
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+
break;
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+
}
2219
+
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adev->gfx.mec.num_pipe_per_mec = 4;
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2221
adev->gfx.mec.num_queue_per_pipe = 8;
2223
2222
···
2386
2373
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gfx_v9_0_alloc_ip_dump(adev);
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+
r = amdgpu_gfx_sysfs_isolation_shader_init(adev);
2377
+
if (r)
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+
return r;
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+
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return 0;
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}
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···
2424
2407
(void **)&adev->gfx.rlc.cp_table_ptr);
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}
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gfx_v9_0_free_microcode(adev);
2410
+
2411
+
amdgpu_gfx_sysfs_isolation_shader_fini(adev);
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2412
2428
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kfree(adev->gfx.ip_dump_core);
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kfree(adev->gfx.ip_dump_compute_queues);
···
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3951
{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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+
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+
amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size,
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+
adev->gfx.cleaner_shader_ptr);
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if (!amdgpu_sriov_vf(adev))
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gfx_v9_0_init_golden_registers(adev);
···
7390
7368
7391
7369
}
7392
7370
7371
+
static void gfx_v9_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
7372
+
{
7373
+
/* Emit the cleaner shader */
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+
amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
7375
+
amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */
7376
+
}
7377
+
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static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
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.name = "gfx_v9_0",
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.early_init = gfx_v9_0_early_init,
···
7446
7417
5 + /* HDP_INVL */
7447
7418
8 + 8 + /* FENCE x2 */
7448
7419
2 + /* SWITCH_BUFFER */
7449
-
7, /* gfx_v9_0_emit_mem_sync */
7420
+
7 + /* gfx_v9_0_emit_mem_sync */
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+
2, /* gfx_v9_0_ring_emit_cleaner_shader */
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.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
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.emit_ib = gfx_v9_0_ring_emit_ib_gfx,
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.emit_fence = gfx_v9_0_ring_emit_fence,
···
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7439
.soft_recovery = gfx_v9_0_ring_soft_recovery,
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.emit_mem_sync = gfx_v9_0_emit_mem_sync,
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.reset = gfx_v9_0_reset_kgq,
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+
.emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader,
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};
7473
7444
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static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = {
···
7502
7471
5 + /* HDP_INVL */
7503
7472
8 + 8 + /* FENCE x2 */
7504
7473
2 + /* SWITCH_BUFFER */
7505
-
7, /* gfx_v9_0_emit_mem_sync */
7474
+
7 + /* gfx_v9_0_emit_mem_sync */
7475
+
2, /* gfx_v9_0_ring_emit_cleaner_shader */
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.emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
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.emit_ib = gfx_v9_0_ring_emit_ib_gfx,
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.emit_fence = gfx_v9_0_ring_emit_fence,
···
7527
7495
.patch_cntl = gfx_v9_0_ring_patch_cntl,
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7496
.patch_de = gfx_v9_0_ring_patch_de_meta,
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7497
.patch_ce = gfx_v9_0_ring_patch_ce_meta,
7498
+
.emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader,
7530
7499
};
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7500
7532
7501
static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
···
7548
7515
8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
7549
7516
7 + /* gfx_v9_0_emit_mem_sync */
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7517
5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */
7551
-
15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */
7518
+
15 + /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */
7519
+
2, /* gfx_v9_0_ring_emit_cleaner_shader */
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7520
.emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */
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7521
.emit_ib = gfx_v9_0_ring_emit_ib_compute,
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7522
.emit_fence = gfx_v9_0_ring_emit_fence,
···
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7534
.emit_mem_sync = gfx_v9_0_emit_mem_sync,
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7535
.emit_wave_limit = gfx_v9_0_emit_wave_limit,
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7536
.reset = gfx_v9_0_reset_kcq,
7537
+
.emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader,
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7538
};
7572
7539
7573
7540
static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
+26
drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h
+26
drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h
···
1
+
/* SPDX-License-Identifier: MIT */
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+
/*
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+
* Copyright 2018 Advanced Micro Devices, Inc.
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+
*
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+
* Permission is hereby granted, free of charge, to any person obtaining a
6
+
* copy of this software and associated documentation files (the "Software"),
7
+
* to deal in the Software without restriction, including without limitation
8
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9
+
* and/or sell copies of the Software, and to permit persons to whom the
10
+
* Software is furnished to do so, subject to the following conditions:
11
+
*
12
+
* The above copyright notice and this permission notice shall be included in
13
+
* all copies or substantial portions of the Software.
14
+
*
15
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21
+
* OTHER DEALINGS IN THE SOFTWARE.
22
+
*/
23
+
/* Define the cleaner shader gfx_9_0 */
24
+
static const u32 __maybe_unused gfx_9_0_cleaner_shader_hex[] = {
25
+
/* Add the cleaner shader code here */
26
+
};