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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Malta: Enable tickless and highres timers.
[MIPS] Bigsur: Enable tickless and and highres timers.
qemu: do not enable IP7 blindly
[MIPS] Alchemy: Fix Au1x SD controller IRQ
[MIPS] Don't byteswap writes to display when running bigendian

+25 -5
+9
arch/mips/configs/bigsur_defconfig
··· 76 76 CONFIG_GENERIC_FIND_NEXT_BIT=y 77 77 CONFIG_GENERIC_HWEIGHT=y 78 78 CONFIG_GENERIC_CALIBRATE_DELAY=y 79 + CONFIG_GENERIC_CLOCKEVENTS=y 79 80 CONFIG_GENERIC_TIME=y 81 + CONFIG_GENERIC_CMOS_UPDATE=y 80 82 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 81 83 # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set 84 + CONFIG_CEVT_BCM1480=y 85 + CONFIG_CSRC_BCM1480=y 82 86 CONFIG_DMA_COHERENT=y 83 87 CONFIG_CPU_BIG_ENDIAN=y 84 88 # CONFIG_CPU_LITTLE_ENDIAN is not set ··· 95 91 # 96 92 # CPU selection 97 93 # 94 + CONFIG_TICK_ONESHOT=y 95 + CONFIG_NO_HZ=y 96 + CONFIG_HIGH_RES_TIMERS=y 97 + CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 98 + # CONFIG_CPU_LOONGSON2 is not set 98 99 # CONFIG_CPU_MIPS32_R1 is not set 99 100 # CONFIG_CPU_MIPS32_R2 is not set 100 101 # CONFIG_CPU_MIPS64_R1 is not set
+8
arch/mips/configs/malta_defconfig
··· 49 49 CONFIG_GENERIC_FIND_NEXT_BIT=y 50 50 CONFIG_GENERIC_HWEIGHT=y 51 51 CONFIG_GENERIC_CALIBRATE_DELAY=y 52 + CONFIG_GENERIC_CLOCKEVENTS=y 52 53 CONFIG_GENERIC_TIME=y 54 + CONFIG_GENERIC_CMOS_UPDATE=y 53 55 CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 54 56 # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set 55 57 CONFIG_ARCH_MAY_HAVE_PC_FDC=y 58 + CONFIG_CEVT_R4K=y 56 59 CONFIG_DMA_NONCOHERENT=y 57 60 CONFIG_DMA_NEED_PCI_MAP_STATE=y 58 61 CONFIG_EARLY_PRINTK=y ··· 79 76 # 80 77 # CPU selection 81 78 # 79 + CONFIG_TICK_ONESHOT=y 80 + CONFIG_NO_HZ=y 81 + CONFIG_HIGH_RES_TIMERS=y 82 + CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 82 83 # CONFIG_CPU_LOONGSON2 is not set 83 84 # CONFIG_CPU_MIPS32_R1 is not set 84 85 CONFIG_CPU_MIPS32_R2=y ··· 260 253 CONFIG_PCI=y 261 254 # CONFIG_ARCH_SUPPORTS_MSI is not set 262 255 CONFIG_MMU=y 256 + CONFIG_I8253=y 263 257 264 258 # 265 259 # PCCARD (PCMCIA/CardBus) support
+2 -2
arch/mips/mips-boards/generic/display.c
··· 37 37 38 38 for (i = 0; i <= 14; i=i+2) { 39 39 if (*str) 40 - writel(*str++, display + i); 40 + __raw_writel(*str++, display + i); 41 41 else 42 - writel(' ', display + i); 42 + __raw_writel(' ', display + i); 43 43 } 44 44 } 45 45
+1 -1
arch/mips/qemu/q-irq.c
··· 33 33 34 34 mips_cpu_irq_init(); 35 35 init_i8259_irqs(); 36 - set_c0_status(0x8400); 36 + set_c0_status(0x400); 37 37 }
+5 -2
include/asm-mips/mach-au1x00/au1100_mmc.h
··· 41 41 42 42 #define NUM_AU1100_MMC_CONTROLLERS 2 43 43 44 - 45 - #define AU1100_SD_IRQ 2 44 + #if defined(CONFIG_SOC_AU1100) 45 + #define AU1100_SD_IRQ AU1100_SD_INT 46 + #elif defined(CONFIG_SOC_AU1200) 47 + #define AU1100_SD_IRQ AU1200_SD_INT 48 + #endif 46 49 47 50 48 51 #define SD0_BASE 0xB0600000