Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: add DCN support for aarch64
This adds ARM64 support into the DCN. This mainly enables support
for Navi graphics cards. The dcn10 changes haven't been tested,
since I don't have the relevant hardware available, but there
is no way to conditionally disable them, so I've done them anyway.
Signed-off-by: Daniel Kolesa <daniel@octaforge.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Daniel Kolesa
and committed by
Alex Deucher
c38d444e
fbd7cda0
+102
-32
+1
-1
drivers/gpu/drm/amd/display/Kconfig
+1
-1
drivers/gpu/drm/amd/display/Kconfig
···
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bool "AMD DC - Enable new display engine"
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default y
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select SND_HDA_COMPONENT if SND_HDA_CORE
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-
select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
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+
select DRM_AMD_DC_DCN if (X86 || PPC64 || (ARM64 && KERNEL_MODE_NEON)) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
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help
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Choose this option if you want to use the new display engine
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support for AMDGPU. This adds required support for Vega and
+7
drivers/gpu/drm/amd/display/dc/calcs/Makefile
+7
drivers/gpu/drm/amd/display/dc/calcs/Makefile
···
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calcs_ccflags := -mhard-float -maltivec
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endif
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+
ifdef CONFIG_ARM64
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calcs_rcflags := -mgeneral-regs-only
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endif
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+
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ifdef CONFIG_CC_IS_GCC
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ifeq ($(call cc-ifversion, -lt, 0701, y), y)
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IS_OLD_GCC = 1
···
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CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/calcs/dcn_calc_math.o := $(calcs_rcflags)
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BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
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+7
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+7
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
···
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CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)
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endif
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# prevent build errors:
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# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types
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# this file is unused on arm64, just like on ppc64
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ifdef CONFIG_ARM64
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := -mgeneral-regs-only
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endif
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+
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AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21))
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AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)
+7
drivers/gpu/drm/amd/display/dc/dcn10/Makefile
+7
drivers/gpu/drm/amd/display/dc/dcn10/Makefile
···
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AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
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# fix:
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# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types
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# aarch64 does not support soft-float, so use hard-float and handle this in code
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ifdef CONFIG_ARM64
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn10/dcn10_resource.o := -mgeneral-regs-only
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endif
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AMD_DISPLAY_FILES += $(AMD_DAL_DCN10)
+50
-31
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+50
-31
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
···
1331
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return value;
1332
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}
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+
/*
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* Some architectures don't support soft-float (e.g. aarch64), on those
1336
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* this function has to be called with hardfloat enabled, make sure not
1337
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* to inline it so whatever fp stuff is done stays inside
1338
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*/
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static noinline void dcn10_resource_construct_fp(
1340
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struct dc *dc)
1341
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{
1342
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if (dc->ctx->dce_version == DCN_VERSION_1_01) {
1343
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struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
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struct dcn_ip_params *dcn_ip = dc->dcn_ip;
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struct display_mode_lib *dml = &dc->dml;
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+
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dml->ip.max_num_dpp = 3;
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/* TODO how to handle 23.84? */
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dcn_soc->dram_clock_change_latency = 23;
1350
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dcn_ip->max_num_dpp = 3;
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}
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if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1353
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dc->dcn_soc->urgent_latency = 3;
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dc->debug.disable_dmcu = true;
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dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
1356
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}
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dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
1360
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ASSERT(dc->dcn_soc->number_of_channels < 3);
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if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
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dc->dcn_soc->number_of_channels = 2;
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+
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if (dc->dcn_soc->number_of_channels == 1) {
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dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
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dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
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dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
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dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
1369
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if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
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dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
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}
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}
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}
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static bool dcn10_resource_construct(
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uint8_t num_virtual_links,
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struct dc *dc,
···
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memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
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memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
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-
if (dc->ctx->dce_version == DCN_VERSION_1_01) {
1527
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struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
1528
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struct dcn_ip_params *dcn_ip = dc->dcn_ip;
1529
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struct display_mode_lib *dml = &dc->dml;
1530
-
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dml->ip.max_num_dpp = 3;
1532
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/* TODO how to handle 23.84? */
1533
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dcn_soc->dram_clock_change_latency = 23;
1534
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dcn_ip->max_num_dpp = 3;
1535
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}
1536
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if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1537
-
dc->dcn_soc->urgent_latency = 3;
1538
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dc->debug.disable_dmcu = true;
1539
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dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
1540
-
}
1541
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-
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dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
1544
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ASSERT(dc->dcn_soc->number_of_channels < 3);
1545
-
if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/
1546
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dc->dcn_soc->number_of_channels = 2;
1547
-
1548
-
if (dc->dcn_soc->number_of_channels == 1) {
1549
-
dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f;
1550
-
dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
1551
-
dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
1552
-
dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
1553
-
if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
1554
-
dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
1555
-
}
1556
-
}
1485
+
#if defined(CONFIG_ARM64)
1486
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/* Aarch64 does not support -msoft-float/-mfloat-abi=soft */
1487
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DC_FP_START();
1488
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dcn10_resource_construct_fp(dc);
1489
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DC_FP_END();
1490
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#else
1491
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/* Other architectures we build for build this with soft-float */
1492
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dcn10_resource_construct_fp(dc);
1493
+
#endif
1557
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pool->base.pp_smu = dcn10_pp_smu_create(ctx);
1559
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+4
drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+4
drivers/gpu/drm/amd/display/dc/dcn20/Makefile
···
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CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -maltivec
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endif
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+
ifdef CONFIG_ARM64
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mgeneral-regs-only
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endif
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+
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ifdef CONFIG_CC_IS_GCC
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ifeq ($(call cc-ifversion, -lt, 0701, y), y)
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IS_OLD_GCC = 1
+4
drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+4
drivers/gpu/drm/amd/display/dc/dcn21/Makefile
···
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CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -maltivec
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endif
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ifdef CONFIG_ARM64
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mgeneral-regs-only
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endif
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+
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ifdef CONFIG_CC_IS_GCC
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ifeq ($(call cc-ifversion, -lt, 0701, y), y)
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IS_OLD_GCC = 1
+13
drivers/gpu/drm/amd/display/dc/dml/Makefile
+13
drivers/gpu/drm/amd/display/dc/dml/Makefile
···
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dml_ccflags := -mhard-float -maltivec
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endif
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+
ifdef CONFIG_ARM64
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dml_rcflags := -mgeneral-regs-only
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+
endif
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+
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ifdef CONFIG_CC_IS_GCC
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ifeq ($(call cc-ifversion, -lt, 0701, y), y)
38
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IS_OLD_GCC = 1
···
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_rcflags)
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endif
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ifdef CONFIG_DRM_AMD_DC_DCN3_0
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) -Wframe-larger-than=2048
···
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endif
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CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_ccflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_rcflags)
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+
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_rcflags)
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DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
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+5
drivers/gpu/drm/amd/display/dc/dsc/Makefile
+5
drivers/gpu/drm/amd/display/dc/dsc/Makefile
···
10
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dsc_ccflags := -mhard-float -maltivec
11
11
endif
12
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13
+
ifdef CONFIG_ARM64
14
+
dsc_rcflags := -mgeneral-regs-only
15
+
endif
16
+
13
17
ifdef CONFIG_CC_IS_GCC
14
18
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
15
19
IS_OLD_GCC = 1
···
32
28
endif
33
29
34
30
CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
31
+
CFLAGS_REMOVE_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_rcflags)
35
32
36
33
DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o
37
34
+4
drivers/gpu/drm/amd/display/dc/os_types.h
+4
drivers/gpu/drm/amd/display/dc/os_types.h
···
55
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#include <asm/fpu/api.h>
56
56
#define DC_FP_START() kernel_fpu_begin()
57
57
#define DC_FP_END() kernel_fpu_end()
58
+
#elif defined(CONFIG_ARM64)
59
+
#include <asm/neon.h>
60
+
#define DC_FP_START() kernel_neon_begin()
61
+
#define DC_FP_END() kernel_neon_end()
58
62
#elif defined(CONFIG_PPC64)
59
63
#include <asm/switch_to.h>
60
64
#include <asm/cputable.h>