tjh.dev / kernel
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Merge git://git.infradead.org/intel-iommu

Pull VT-d hardware workarounds from David Woodhouse:
"This contains a workaround for hardware issues which I *thought* were
never going to be seen on production hardware. I'm glad I checked
that before the 4.1 release...

Firstly, PASID support is so broken on existing chips that we're just
going to declare the old capability bit 28 as 'reserved' and change
the VT-d spec to move PASID support to another bit. So any existing
hardware doesn't support SVM; it only sets that (now) meaningless bit
28.

That patch *wasn't* imperative for 4.1 because we don't have PASID
support yet. But *even* the extended context tables are broken — if
you just enable the wider tables and use none of the new bits in them,
which is precisely what 4.1 does, you find that translations don't
work. It's this problem which I thought was caught in time to be
fixed before production, but wasn't.

To avoid triggering this issue, we now *only* enable the extended
context tables on hardware which also advertises "we have PASID
support and we actually tested it this time" with the new PASID
feature bit.

In addition, I've added an 'intel_iommu=ecs_off' command line
parameter to allow us to disable it manually if we need to"

* git://git.infradead.org/intel-iommu:
iommu/vt-d: Only enable extended context tables if PASID is supported
iommu/vt-d: Change PASID support to bit 40 of Extended Capability Register

Linus Torvalds c39f3bc6 df5f4158

+23 -4
+6
Documentation/kernel-parameters.txt
··· 1481 1481 By default, super page will be supported if Intel IOMMU 1482 1482 has the capability. With this option, super page will 1483 1483 not be supported. 1484 + ecs_off [Default Off] 1485 + By default, extended context tables will be supported if 1486 + the hardware advertises that it has support both for the 1487 + extended tables themselves, and also PASID support. With 1488 + this option set, extended tables will not be used even 1489 + on hardware which claims to support them. 1484 1490 1485 1491 intel_idle.max_cstate= [KNL,HW,ACPI,X86] 1486 1492 0 disables intel_idle and fall back on acpi_idle.
+15 -3
drivers/iommu/intel-iommu.c
··· 422 422 static int dmar_forcedac; 423 423 static int intel_iommu_strict; 424 424 static int intel_iommu_superpage = 1; 425 + static int intel_iommu_ecs = 1; 426 + 427 + /* We only actually use ECS when PASID support (on the new bit 40) 428 + * is also advertised. Some early implementations — the ones with 429 + * PASID support on bit 28 — have issues even when we *only* use 430 + * extended root/context tables. */ 431 + #define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \ 432 + ecap_pasid(iommu->ecap)) 425 433 426 434 int intel_iommu_gfx_mapped; 427 435 EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped); ··· 473 465 printk(KERN_INFO 474 466 "Intel-IOMMU: disable supported super page\n"); 475 467 intel_iommu_superpage = 0; 468 + } else if (!strncmp(str, "ecs_off", 7)) { 469 + printk(KERN_INFO 470 + "Intel-IOMMU: disable extended context table support\n"); 471 + intel_iommu_ecs = 0; 476 472 } 477 473 478 474 str += strcspn(str, ","); ··· 681 669 struct context_entry *context; 682 670 u64 *entry; 683 671 684 - if (ecap_ecs(iommu->ecap)) { 672 + if (ecs_enabled(iommu)) { 685 673 if (devfn >= 0x80) { 686 674 devfn -= 0x80; 687 675 entry = &root->hi; ··· 818 806 if (context) 819 807 free_pgtable_page(context); 820 808 821 - if (!ecap_ecs(iommu->ecap)) 809 + if (!ecs_enabled(iommu)) 822 810 continue; 823 811 824 812 context = iommu_context_addr(iommu, i, 0x80, 0); ··· 1153 1141 unsigned long flag; 1154 1142 1155 1143 addr = virt_to_phys(iommu->root_entry); 1156 - if (ecap_ecs(iommu->ecap)) 1144 + if (ecs_enabled(iommu)) 1157 1145 addr |= DMA_RTADDR_RTT; 1158 1146 1159 1147 raw_spin_lock_irqsave(&iommu->register_lock, flag);
+2 -1
include/linux/intel-iommu.h
··· 115 115 * Extended Capability Register 116 116 */ 117 117 118 + #define ecap_pasid(e) ((e >> 40) & 0x1) 118 119 #define ecap_pss(e) ((e >> 35) & 0x1f) 119 120 #define ecap_eafs(e) ((e >> 34) & 0x1) 120 121 #define ecap_nwfs(e) ((e >> 33) & 0x1) 121 122 #define ecap_srs(e) ((e >> 31) & 0x1) 122 123 #define ecap_ers(e) ((e >> 30) & 0x1) 123 124 #define ecap_prs(e) ((e >> 29) & 0x1) 124 - #define ecap_pasid(e) ((e >> 28) & 0x1) 125 + /* PASID support used to be on bit 28 */ 125 126 #define ecap_dis(e) ((e >> 27) & 0x1) 126 127 #define ecap_nest(e) ((e >> 26) & 0x1) 127 128 #define ecap_mts(e) ((e >> 25) & 0x1)