clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS

+2

drivers/clk/meson/Kconfig

··· 108 108 tristate "Amlogic A1 SoC PLL controller support" 109 109 depends on ARM64 110 110 select COMMON_CLK_MESON_REGMAP 111 + select COMMON_CLK_MESON_CLKC_UTILS 111 112 select COMMON_CLK_MESON_PLL 112 113 help 113 114 Support for the PLL clock controller on Amlogic A113L based ··· 120 119 depends on ARM64 121 120 select COMMON_CLK_MESON_DUALDIV 122 121 select COMMON_CLK_MESON_REGMAP 122 + select COMMON_CLK_MESON_CLKC_UTILS 123 123 help 124 124 Support for the Peripherals clock controller on Amlogic A113L based 125 125 device, A1 SoC Family. Say Y if you want A1 Peripherals clock

+162 -161

drivers/clk/meson/a1-peripherals.c

··· 13 13 #include "a1-peripherals.h" 14 14 #include "clk-dualdiv.h" 15 15 #include "clk-regmap.h" 16 + #include "meson-clkc-utils.h" 16 17 17 18 static struct clk_regmap xtal_in = { 18 19 .data = &(struct clk_regmap_gate_data){ ··· 1867 1866 static MESON_GATE(prod_i2c, AXI_CLK_EN, 12); 1868 1867 1869 1868 /* Array of all clocks registered by this provider */ 1870 - static struct clk_hw_onecell_data a1_periphs_clks = { 1871 - .hws = { 1872 - [CLKID_XTAL_IN] = &xtal_in.hw, 1873 - [CLKID_FIXPLL_IN] = &fixpll_in.hw, 1874 - [CLKID_USB_PHY_IN] = &usb_phy_in.hw, 1875 - [CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw, 1876 - [CLKID_HIFIPLL_IN] = &hifipll_in.hw, 1877 - [CLKID_SYSPLL_IN] = &syspll_in.hw, 1878 - [CLKID_DDS_IN] = &dds_in.hw, 1879 - [CLKID_SYS] = &sys.hw, 1880 - [CLKID_CLKTREE] = &clktree.hw, 1881 - [CLKID_RESET_CTRL] = &reset_ctrl.hw, 1882 - [CLKID_ANALOG_CTRL] = &analog_ctrl.hw, 1883 - [CLKID_PWR_CTRL] = &pwr_ctrl.hw, 1884 - [CLKID_PAD_CTRL] = &pad_ctrl.hw, 1885 - [CLKID_SYS_CTRL] = &sys_ctrl.hw, 1886 - [CLKID_TEMP_SENSOR] = &temp_sensor.hw, 1887 - [CLKID_AM2AXI_DIV] = &am2axi_dev.hw, 1888 - [CLKID_SPICC_B] = &spicc_b.hw, 1889 - [CLKID_SPICC_A] = &spicc_a.hw, 1890 - [CLKID_MSR] = &msr.hw, 1891 - [CLKID_AUDIO] = &audio.hw, 1892 - [CLKID_JTAG_CTRL] = &jtag_ctrl.hw, 1893 - [CLKID_SARADC_EN] = &saradc_en.hw, 1894 - [CLKID_PWM_EF] = &pwm_ef.hw, 1895 - [CLKID_PWM_CD] = &pwm_cd.hw, 1896 - [CLKID_PWM_AB] = &pwm_ab.hw, 1897 - [CLKID_CEC] = &cec.hw, 1898 - [CLKID_I2C_S] = &i2c_s.hw, 1899 - [CLKID_IR_CTRL] = &ir_ctrl.hw, 1900 - [CLKID_I2C_M_D] = &i2c_m_d.hw, 1901 - [CLKID_I2C_M_C] = &i2c_m_c.hw, 1902 - [CLKID_I2C_M_B] = &i2c_m_b.hw, 1903 - [CLKID_I2C_M_A] = &i2c_m_a.hw, 1904 - [CLKID_ACODEC] = &acodec.hw, 1905 - [CLKID_OTP] = &otp.hw, 1906 - [CLKID_SD_EMMC_A] = &sd_emmc_a.hw, 1907 - [CLKID_USB_PHY] = &usb_phy.hw, 1908 - [CLKID_USB_CTRL] = &usb_ctrl.hw, 1909 - [CLKID_SYS_DSPB] = &sys_dspb.hw, 1910 - [CLKID_SYS_DSPA] = &sys_dspa.hw, 1911 - [CLKID_DMA] = &dma.hw, 1912 - [CLKID_IRQ_CTRL] = &irq_ctrl.hw, 1913 - [CLKID_NIC] = &nic.hw, 1914 - [CLKID_GIC] = &gic.hw, 1915 - [CLKID_UART_C] = &uart_c.hw, 1916 - [CLKID_UART_B] = &uart_b.hw, 1917 - [CLKID_UART_A] = &uart_a.hw, 1918 - [CLKID_SYS_PSRAM] = &sys_psram.hw, 1919 - [CLKID_RSA] = &rsa.hw, 1920 - [CLKID_CORESIGHT] = &coresight.hw, 1921 - [CLKID_AM2AXI_VAD] = &am2axi_vad.hw, 1922 - [CLKID_AUDIO_VAD] = &audio_vad.hw, 1923 - [CLKID_AXI_DMC] = &axi_dmc.hw, 1924 - [CLKID_AXI_PSRAM] = &axi_psram.hw, 1925 - [CLKID_RAMB] = &ramb.hw, 1926 - [CLKID_RAMA] = &rama.hw, 1927 - [CLKID_AXI_SPIFC] = &axi_spifc.hw, 1928 - [CLKID_AXI_NIC] = &axi_nic.hw, 1929 - [CLKID_AXI_DMA] = &axi_dma.hw, 1930 - [CLKID_CPU_CTRL] = &cpu_ctrl.hw, 1931 - [CLKID_ROM] = &rom.hw, 1932 - [CLKID_PROC_I2C] = &prod_i2c.hw, 1933 - [CLKID_DSPA_SEL] = &dspa_sel.hw, 1934 - [CLKID_DSPB_SEL] = &dspb_sel.hw, 1935 - [CLKID_DSPA_EN] = &dspa_en.hw, 1936 - [CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw, 1937 - [CLKID_DSPB_EN] = &dspb_en.hw, 1938 - [CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw, 1939 - [CLKID_RTC] = &rtc.hw, 1940 - [CLKID_CECA_32K] = &ceca_32k_out.hw, 1941 - [CLKID_CECB_32K] = &cecb_32k_out.hw, 1942 - [CLKID_24M] = &clk_24m.hw, 1943 - [CLKID_12M] = &clk_12m.hw, 1944 - [CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw, 1945 - [CLKID_GEN] = &gen.hw, 1946 - [CLKID_SARADC_SEL] = &saradc_sel.hw, 1947 - [CLKID_SARADC] = &saradc.hw, 1948 - [CLKID_PWM_A] = &pwm_a.hw, 1949 - [CLKID_PWM_B] = &pwm_b.hw, 1950 - [CLKID_PWM_C] = &pwm_c.hw, 1951 - [CLKID_PWM_D] = &pwm_d.hw, 1952 - [CLKID_PWM_E] = &pwm_e.hw, 1953 - [CLKID_PWM_F] = &pwm_f.hw, 1954 - [CLKID_SPICC] = &spicc.hw, 1955 - [CLKID_TS] = &ts.hw, 1956 - [CLKID_SPIFC] = &spifc.hw, 1957 - [CLKID_USB_BUS] = &usb_bus.hw, 1958 - [CLKID_SD_EMMC] = &sd_emmc.hw, 1959 - [CLKID_PSRAM] = &psram.hw, 1960 - [CLKID_DMC] = &dmc.hw, 1961 - [CLKID_SYS_A_SEL] = &sys_a_sel.hw, 1962 - [CLKID_SYS_A_DIV] = &sys_a_div.hw, 1963 - [CLKID_SYS_A] = &sys_a.hw, 1964 - [CLKID_SYS_B_SEL] = &sys_b_sel.hw, 1965 - [CLKID_SYS_B_DIV] = &sys_b_div.hw, 1966 - [CLKID_SYS_B] = &sys_b.hw, 1967 - [CLKID_DSPA_A_SEL] = &dspa_a_sel.hw, 1968 - [CLKID_DSPA_A_DIV] = &dspa_a_div.hw, 1969 - [CLKID_DSPA_A] = &dspa_a.hw, 1970 - [CLKID_DSPA_B_SEL] = &dspa_b_sel.hw, 1971 - [CLKID_DSPA_B_DIV] = &dspa_b_div.hw, 1972 - [CLKID_DSPA_B] = &dspa_b.hw, 1973 - [CLKID_DSPB_A_SEL] = &dspb_a_sel.hw, 1974 - [CLKID_DSPB_A_DIV] = &dspb_a_div.hw, 1975 - [CLKID_DSPB_A] = &dspb_a.hw, 1976 - [CLKID_DSPB_B_SEL] = &dspb_b_sel.hw, 1977 - [CLKID_DSPB_B_DIV] = &dspb_b_div.hw, 1978 - [CLKID_DSPB_B] = &dspb_b.hw, 1979 - [CLKID_RTC_32K_IN] = &rtc_32k_in.hw, 1980 - [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw, 1981 - [CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw, 1982 - [CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw, 1983 - [CLKID_CECB_32K_IN] = &cecb_32k_in.hw, 1984 - [CLKID_CECB_32K_DIV] = &cecb_32k_div.hw, 1985 - [CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw, 1986 - [CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw, 1987 - [CLKID_CECA_32K_IN] = &ceca_32k_in.hw, 1988 - [CLKID_CECA_32K_DIV] = &ceca_32k_div.hw, 1989 - [CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw, 1990 - [CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw, 1991 - [CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw, 1992 - [CLKID_24M_DIV2] = &clk_24m_div2.hw, 1993 - [CLKID_GEN_SEL] = &gen_sel.hw, 1994 - [CLKID_GEN_DIV] = &gen_div.hw, 1995 - [CLKID_SARADC_DIV] = &saradc_div.hw, 1996 - [CLKID_PWM_A_SEL] = &pwm_a_sel.hw, 1997 - [CLKID_PWM_A_DIV] = &pwm_a_div.hw, 1998 - [CLKID_PWM_B_SEL] = &pwm_b_sel.hw, 1999 - [CLKID_PWM_B_DIV] = &pwm_b_div.hw, 2000 - [CLKID_PWM_C_SEL] = &pwm_c_sel.hw, 2001 - [CLKID_PWM_C_DIV] = &pwm_c_div.hw, 2002 - [CLKID_PWM_D_SEL] = &pwm_d_sel.hw, 2003 - [CLKID_PWM_D_DIV] = &pwm_d_div.hw, 2004 - [CLKID_PWM_E_SEL] = &pwm_e_sel.hw, 2005 - [CLKID_PWM_E_DIV] = &pwm_e_div.hw, 2006 - [CLKID_PWM_F_SEL] = &pwm_f_sel.hw, 2007 - [CLKID_PWM_F_DIV] = &pwm_f_div.hw, 2008 - [CLKID_SPICC_SEL] = &spicc_sel.hw, 2009 - [CLKID_SPICC_DIV] = &spicc_div.hw, 2010 - [CLKID_SPICC_SEL2] = &spicc_sel2.hw, 2011 - [CLKID_TS_DIV] = &ts_div.hw, 2012 - [CLKID_SPIFC_SEL] = &spifc_sel.hw, 2013 - [CLKID_SPIFC_DIV] = &spifc_div.hw, 2014 - [CLKID_SPIFC_SEL2] = &spifc_sel2.hw, 2015 - [CLKID_USB_BUS_SEL] = &usb_bus_sel.hw, 2016 - [CLKID_USB_BUS_DIV] = &usb_bus_div.hw, 2017 - [CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw, 2018 - [CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw, 2019 - [CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw, 2020 - [CLKID_PSRAM_SEL] = &psram_sel.hw, 2021 - [CLKID_PSRAM_DIV] = &psram_div.hw, 2022 - [CLKID_PSRAM_SEL2] = &psram_sel2.hw, 2023 - [CLKID_DMC_SEL] = &dmc_sel.hw, 2024 - [CLKID_DMC_DIV] = &dmc_div.hw, 2025 - [CLKID_DMC_SEL2] = &dmc_sel2.hw, 2026 - [NR_CLKS] = NULL, 2027 - }, 2028 - .num = NR_CLKS, 1869 + static struct clk_hw *a1_periphs_hw_clks[] = { 1870 + [CLKID_XTAL_IN] = &xtal_in.hw, 1871 + [CLKID_FIXPLL_IN] = &fixpll_in.hw, 1872 + [CLKID_USB_PHY_IN] = &usb_phy_in.hw, 1873 + [CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw, 1874 + [CLKID_HIFIPLL_IN] = &hifipll_in.hw, 1875 + [CLKID_SYSPLL_IN] = &syspll_in.hw, 1876 + [CLKID_DDS_IN] = &dds_in.hw, 1877 + [CLKID_SYS] = &sys.hw, 1878 + [CLKID_CLKTREE] = &clktree.hw, 1879 + [CLKID_RESET_CTRL] = &reset_ctrl.hw, 1880 + [CLKID_ANALOG_CTRL] = &analog_ctrl.hw, 1881 + [CLKID_PWR_CTRL] = &pwr_ctrl.hw, 1882 + [CLKID_PAD_CTRL] = &pad_ctrl.hw, 1883 + [CLKID_SYS_CTRL] = &sys_ctrl.hw, 1884 + [CLKID_TEMP_SENSOR] = &temp_sensor.hw, 1885 + [CLKID_AM2AXI_DIV] = &am2axi_dev.hw, 1886 + [CLKID_SPICC_B] = &spicc_b.hw, 1887 + [CLKID_SPICC_A] = &spicc_a.hw, 1888 + [CLKID_MSR] = &msr.hw, 1889 + [CLKID_AUDIO] = &audio.hw, 1890 + [CLKID_JTAG_CTRL] = &jtag_ctrl.hw, 1891 + [CLKID_SARADC_EN] = &saradc_en.hw, 1892 + [CLKID_PWM_EF] = &pwm_ef.hw, 1893 + [CLKID_PWM_CD] = &pwm_cd.hw, 1894 + [CLKID_PWM_AB] = &pwm_ab.hw, 1895 + [CLKID_CEC] = &cec.hw, 1896 + [CLKID_I2C_S] = &i2c_s.hw, 1897 + [CLKID_IR_CTRL] = &ir_ctrl.hw, 1898 + [CLKID_I2C_M_D] = &i2c_m_d.hw, 1899 + [CLKID_I2C_M_C] = &i2c_m_c.hw, 1900 + [CLKID_I2C_M_B] = &i2c_m_b.hw, 1901 + [CLKID_I2C_M_A] = &i2c_m_a.hw, 1902 + [CLKID_ACODEC] = &acodec.hw, 1903 + [CLKID_OTP] = &otp.hw, 1904 + [CLKID_SD_EMMC_A] = &sd_emmc_a.hw, 1905 + [CLKID_USB_PHY] = &usb_phy.hw, 1906 + [CLKID_USB_CTRL] = &usb_ctrl.hw, 1907 + [CLKID_SYS_DSPB] = &sys_dspb.hw, 1908 + [CLKID_SYS_DSPA] = &sys_dspa.hw, 1909 + [CLKID_DMA] = &dma.hw, 1910 + [CLKID_IRQ_CTRL] = &irq_ctrl.hw, 1911 + [CLKID_NIC] = &nic.hw, 1912 + [CLKID_GIC] = &gic.hw, 1913 + [CLKID_UART_C] = &uart_c.hw, 1914 + [CLKID_UART_B] = &uart_b.hw, 1915 + [CLKID_UART_A] = &uart_a.hw, 1916 + [CLKID_SYS_PSRAM] = &sys_psram.hw, 1917 + [CLKID_RSA] = &rsa.hw, 1918 + [CLKID_CORESIGHT] = &coresight.hw, 1919 + [CLKID_AM2AXI_VAD] = &am2axi_vad.hw, 1920 + [CLKID_AUDIO_VAD] = &audio_vad.hw, 1921 + [CLKID_AXI_DMC] = &axi_dmc.hw, 1922 + [CLKID_AXI_PSRAM] = &axi_psram.hw, 1923 + [CLKID_RAMB] = &ramb.hw, 1924 + [CLKID_RAMA] = &rama.hw, 1925 + [CLKID_AXI_SPIFC] = &axi_spifc.hw, 1926 + [CLKID_AXI_NIC] = &axi_nic.hw, 1927 + [CLKID_AXI_DMA] = &axi_dma.hw, 1928 + [CLKID_CPU_CTRL] = &cpu_ctrl.hw, 1929 + [CLKID_ROM] = &rom.hw, 1930 + [CLKID_PROC_I2C] = &prod_i2c.hw, 1931 + [CLKID_DSPA_SEL] = &dspa_sel.hw, 1932 + [CLKID_DSPB_SEL] = &dspb_sel.hw, 1933 + [CLKID_DSPA_EN] = &dspa_en.hw, 1934 + [CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw, 1935 + [CLKID_DSPB_EN] = &dspb_en.hw, 1936 + [CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw, 1937 + [CLKID_RTC] = &rtc.hw, 1938 + [CLKID_CECA_32K] = &ceca_32k_out.hw, 1939 + [CLKID_CECB_32K] = &cecb_32k_out.hw, 1940 + [CLKID_24M] = &clk_24m.hw, 1941 + [CLKID_12M] = &clk_12m.hw, 1942 + [CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw, 1943 + [CLKID_GEN] = &gen.hw, 1944 + [CLKID_SARADC_SEL] = &saradc_sel.hw, 1945 + [CLKID_SARADC] = &saradc.hw, 1946 + [CLKID_PWM_A] = &pwm_a.hw, 1947 + [CLKID_PWM_B] = &pwm_b.hw, 1948 + [CLKID_PWM_C] = &pwm_c.hw, 1949 + [CLKID_PWM_D] = &pwm_d.hw, 1950 + [CLKID_PWM_E] = &pwm_e.hw, 1951 + [CLKID_PWM_F] = &pwm_f.hw, 1952 + [CLKID_SPICC] = &spicc.hw, 1953 + [CLKID_TS] = &ts.hw, 1954 + [CLKID_SPIFC] = &spifc.hw, 1955 + [CLKID_USB_BUS] = &usb_bus.hw, 1956 + [CLKID_SD_EMMC] = &sd_emmc.hw, 1957 + [CLKID_PSRAM] = &psram.hw, 1958 + [CLKID_DMC] = &dmc.hw, 1959 + [CLKID_SYS_A_SEL] = &sys_a_sel.hw, 1960 + [CLKID_SYS_A_DIV] = &sys_a_div.hw, 1961 + [CLKID_SYS_A] = &sys_a.hw, 1962 + [CLKID_SYS_B_SEL] = &sys_b_sel.hw, 1963 + [CLKID_SYS_B_DIV] = &sys_b_div.hw, 1964 + [CLKID_SYS_B] = &sys_b.hw, 1965 + [CLKID_DSPA_A_SEL] = &dspa_a_sel.hw, 1966 + [CLKID_DSPA_A_DIV] = &dspa_a_div.hw, 1967 + [CLKID_DSPA_A] = &dspa_a.hw, 1968 + [CLKID_DSPA_B_SEL] = &dspa_b_sel.hw, 1969 + [CLKID_DSPA_B_DIV] = &dspa_b_div.hw, 1970 + [CLKID_DSPA_B] = &dspa_b.hw, 1971 + [CLKID_DSPB_A_SEL] = &dspb_a_sel.hw, 1972 + [CLKID_DSPB_A_DIV] = &dspb_a_div.hw, 1973 + [CLKID_DSPB_A] = &dspb_a.hw, 1974 + [CLKID_DSPB_B_SEL] = &dspb_b_sel.hw, 1975 + [CLKID_DSPB_B_DIV] = &dspb_b_div.hw, 1976 + [CLKID_DSPB_B] = &dspb_b.hw, 1977 + [CLKID_RTC_32K_IN] = &rtc_32k_in.hw, 1978 + [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw, 1979 + [CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw, 1980 + [CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw, 1981 + [CLKID_CECB_32K_IN] = &cecb_32k_in.hw, 1982 + [CLKID_CECB_32K_DIV] = &cecb_32k_div.hw, 1983 + [CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw, 1984 + [CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw, 1985 + [CLKID_CECA_32K_IN] = &ceca_32k_in.hw, 1986 + [CLKID_CECA_32K_DIV] = &ceca_32k_div.hw, 1987 + [CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw, 1988 + [CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw, 1989 + [CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw, 1990 + [CLKID_24M_DIV2] = &clk_24m_div2.hw, 1991 + [CLKID_GEN_SEL] = &gen_sel.hw, 1992 + [CLKID_GEN_DIV] = &gen_div.hw, 1993 + [CLKID_SARADC_DIV] = &saradc_div.hw, 1994 + [CLKID_PWM_A_SEL] = &pwm_a_sel.hw, 1995 + [CLKID_PWM_A_DIV] = &pwm_a_div.hw, 1996 + [CLKID_PWM_B_SEL] = &pwm_b_sel.hw, 1997 + [CLKID_PWM_B_DIV] = &pwm_b_div.hw, 1998 + [CLKID_PWM_C_SEL] = &pwm_c_sel.hw, 1999 + [CLKID_PWM_C_DIV] = &pwm_c_div.hw, 2000 + [CLKID_PWM_D_SEL] = &pwm_d_sel.hw, 2001 + [CLKID_PWM_D_DIV] = &pwm_d_div.hw, 2002 + [CLKID_PWM_E_SEL] = &pwm_e_sel.hw, 2003 + [CLKID_PWM_E_DIV] = &pwm_e_div.hw, 2004 + [CLKID_PWM_F_SEL] = &pwm_f_sel.hw, 2005 + [CLKID_PWM_F_DIV] = &pwm_f_div.hw, 2006 + [CLKID_SPICC_SEL] = &spicc_sel.hw, 2007 + [CLKID_SPICC_DIV] = &spicc_div.hw, 2008 + [CLKID_SPICC_SEL2] = &spicc_sel2.hw, 2009 + [CLKID_TS_DIV] = &ts_div.hw, 2010 + [CLKID_SPIFC_SEL] = &spifc_sel.hw, 2011 + [CLKID_SPIFC_DIV] = &spifc_div.hw, 2012 + [CLKID_SPIFC_SEL2] = &spifc_sel2.hw, 2013 + [CLKID_USB_BUS_SEL] = &usb_bus_sel.hw, 2014 + [CLKID_USB_BUS_DIV] = &usb_bus_div.hw, 2015 + [CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw, 2016 + [CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw, 2017 + [CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw, 2018 + [CLKID_PSRAM_SEL] = &psram_sel.hw, 2019 + [CLKID_PSRAM_DIV] = &psram_div.hw, 2020 + [CLKID_PSRAM_SEL2] = &psram_sel2.hw, 2021 + [CLKID_DMC_SEL] = &dmc_sel.hw, 2022 + [CLKID_DMC_DIV] = &dmc_div.hw, 2023 + [CLKID_DMC_SEL2] = &dmc_sel2.hw, 2029 2024 }; 2030 2025 2031 2026 /* Convenience table to populate regmap in .probe */ ··· 2187 2190 .reg_stride = 4, 2188 2191 }; 2189 2192 2193 + static struct meson_clk_hw_data a1_periphs_clks = { 2194 + .hws = a1_periphs_hw_clks, 2195 + .num = ARRAY_SIZE(a1_periphs_hw_clks), 2196 + }; 2197 + 2190 2198 static int meson_a1_periphs_probe(struct platform_device *pdev) 2191 2199 { 2192 2200 struct device *dev = &pdev->dev; ··· 2221 2219 clkid); 2222 2220 } 2223 2221 2224 - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 2225 - &a1_periphs_clks); 2222 + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_periphs_clks); 2226 2223 } 2227 2224 2228 2225 static const struct of_device_id a1_periphs_clkc_match_table[] = {

-1

drivers/clk/meson/a1-peripherals.h

··· 108 108 #define CLKID_DMC_SEL 151 109 109 #define CLKID_DMC_DIV 152 110 110 #define CLKID_DMC_SEL2 153 111 - #define NR_CLKS 154 112 111 113 112 #endif /* __A1_PERIPHERALS_H */

+19 -17

drivers/clk/meson/a1-pll.c

··· 12 12 #include <linux/platform_device.h> 13 13 #include "a1-pll.h" 14 14 #include "clk-regmap.h" 15 + #include "meson-clkc-utils.h" 15 16 16 17 static struct clk_regmap fixed_pll_dco = { 17 18 .data = &(struct meson_clk_pll_data){ ··· 269 268 }; 270 269 271 270 /* Array of all clocks registered by this provider */ 272 - static struct clk_hw_onecell_data a1_pll_clks = { 273 - .hws = { 274 - [CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw, 275 - [CLKID_FIXED_PLL] = &fixed_pll.hw, 276 - [CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw, 277 - [CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw, 278 - [CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw, 279 - [CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw, 280 - [CLKID_FCLK_DIV2] = &fclk_div2.hw, 281 - [CLKID_FCLK_DIV3] = &fclk_div3.hw, 282 - [CLKID_FCLK_DIV5] = &fclk_div5.hw, 283 - [CLKID_FCLK_DIV7] = &fclk_div7.hw, 284 - [CLKID_HIFI_PLL] = &hifi_pll.hw, 285 - [NR_PLL_CLKS] = NULL, 286 - }, 287 - .num = NR_PLL_CLKS, 271 + static struct clk_hw *a1_pll_hw_clks[] = { 272 + [CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw, 273 + [CLKID_FIXED_PLL] = &fixed_pll.hw, 274 + [CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw, 275 + [CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw, 276 + [CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw, 277 + [CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw, 278 + [CLKID_FCLK_DIV2] = &fclk_div2.hw, 279 + [CLKID_FCLK_DIV3] = &fclk_div3.hw, 280 + [CLKID_FCLK_DIV5] = &fclk_div5.hw, 281 + [CLKID_FCLK_DIV7] = &fclk_div7.hw, 282 + [CLKID_HIFI_PLL] = &hifi_pll.hw, 288 283 }; 289 284 290 285 static struct clk_regmap *const a1_pll_regmaps[] = { ··· 297 300 .reg_bits = 32, 298 301 .val_bits = 32, 299 302 .reg_stride = 4, 303 + }; 304 + 305 + static struct meson_clk_hw_data a1_pll_clks = { 306 + .hws = a1_pll_hw_clks, 307 + .num = ARRAY_SIZE(a1_pll_hw_clks), 300 308 }; 301 309 302 310 static int meson_a1_pll_probe(struct platform_device *pdev) ··· 334 332 clkid); 335 333 } 336 334 337 - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 335 + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, 338 336 &a1_pll_clks); 339 337 } 340 338

-1

drivers/clk/meson/a1-pll.h

··· 42 42 #define CLKID_FCLK_DIV3_DIV 3 43 43 #define CLKID_FCLK_DIV5_DIV 4 44 44 #define CLKID_FCLK_DIV7_DIV 5 45 - #define NR_PLL_CLKS 11 46 45 47 46 #endif /* __A1_PLL_H */

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