Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: Add prefix for plane functions
This commit adds the amdgpu_dm_plane_ prefix for all functions in the
amdgpu_dm_plane.c. This change enables an easy way to filter code paths
via ftrace.
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Rodrigo Siqueira
and committed by
Alex Deucher
c4066d8b
6ce4f9ee
+262
-258
+1
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+1
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
9880
9880
9881
9881
/* Block top most plane from being a video plane */
9882
9882
if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9883
-
if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9883
+
if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9884
9884
return -EINVAL;
9885
9885
9886
9886
*is_top_most_overlay = false;
+260
-256
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+260
-256
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
···
139
139
}
140
140
}
141
141
142
-
static void add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod)
142
+
static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64_t *cap, uint64_t mod)
143
143
{
144
144
if (!*mods)
145
145
return;
···
164
164
*size += 1;
165
165
}
166
166
167
-
static bool modifier_has_dcc(uint64_t modifier)
167
+
static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier)
168
168
{
169
169
return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
170
170
}
171
171
172
-
static unsigned int modifier_gfx9_swizzle_mode(uint64_t modifier)
172
+
static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier)
173
173
{
174
174
if (modifier == DRM_FORMAT_MOD_LINEAR)
175
175
return 0;
···
177
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return AMD_FMT_MOD_GET(TILE, modifier);
178
178
}
179
179
180
-
static void fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
181
-
uint64_t tiling_flags)
180
+
static void amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(union dc_tiling_info *tiling_info,
181
+
uint64_t tiling_flags)
182
182
{
183
183
/* Fill GFX8 params */
184
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if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
···
209
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AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
210
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}
211
211
212
-
static void fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
213
-
union dc_tiling_info *tiling_info)
212
+
static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
213
+
union dc_tiling_info *tiling_info)
214
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{
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/* Fill GFX9 params */
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tiling_info->gfx9.num_pipes =
···
230
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tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
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}
232
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-
static void fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
234
-
union dc_tiling_info *tiling_info,
235
-
uint64_t modifier)
233
+
static void amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
234
+
union dc_tiling_info *tiling_info,
235
+
uint64_t modifier)
236
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{
237
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unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
238
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unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
···
241
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pipes_log2 = min(5u, mod_pipe_xor_bits);
243
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-
fill_gfx9_tiling_info_from_device(adev, tiling_info);
244
+
amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info);
245
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if (!IS_AMD_FMT_MOD(modifier))
247
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return;
···
258
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}
259
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}
260
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261
-
static int validate_dcc(struct amdgpu_device *adev,
262
-
const enum surface_pixel_format format,
263
-
const enum dc_rotation_angle rotation,
264
-
const union dc_tiling_info *tiling_info,
265
-
const struct dc_plane_dcc_param *dcc,
266
-
const struct dc_plane_address *address,
267
-
const struct plane_size *plane_size)
261
+
static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev,
262
+
const enum surface_pixel_format format,
263
+
const enum dc_rotation_angle rotation,
264
+
const union dc_tiling_info *tiling_info,
265
+
const struct dc_plane_dcc_param *dcc,
266
+
const struct dc_plane_address *address,
267
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const struct plane_size *plane_size)
268
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{
269
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struct dc *dc = adev->dm.dc;
270
270
struct dc_dcc_surface_param input;
···
303
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return 0;
304
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}
305
305
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-
static int fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
307
-
const struct amdgpu_framebuffer *afb,
308
-
const enum surface_pixel_format format,
309
-
const enum dc_rotation_angle rotation,
310
-
const struct plane_size *plane_size,
311
-
union dc_tiling_info *tiling_info,
312
-
struct dc_plane_dcc_param *dcc,
313
-
struct dc_plane_address *address,
314
-
const bool force_disable_dcc)
306
+
static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
307
+
const struct amdgpu_framebuffer *afb,
308
+
const enum surface_pixel_format format,
309
+
const enum dc_rotation_angle rotation,
310
+
const struct plane_size *plane_size,
311
+
union dc_tiling_info *tiling_info,
312
+
struct dc_plane_dcc_param *dcc,
313
+
struct dc_plane_address *address,
314
+
const bool force_disable_dcc)
315
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{
316
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const uint64_t modifier = afb->base.modifier;
317
317
int ret = 0;
318
318
319
-
fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
320
-
tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier);
319
+
amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
320
+
tiling_info->gfx9.swizzle = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier);
321
321
322
-
if (modifier_has_dcc(modifier) && !force_disable_dcc) {
322
+
if (amdgpu_dm_plane_modifier_has_dcc(modifier) && !force_disable_dcc) {
323
323
uint64_t dcc_address = afb->address + afb->base.offsets[1];
324
324
bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
325
325
bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);
···
347
347
address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
348
348
}
349
349
350
-
ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
350
+
ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
351
351
if (ret)
352
-
drm_dbg_kms(adev_to_drm(adev), "validate_dcc: returned error: %d\n", ret);
352
+
drm_dbg_kms(adev_to_drm(adev), "amdgpu_dm_plane_validate_dcc: returned error: %d\n", ret);
353
353
354
354
return ret;
355
355
}
356
356
357
-
static void add_gfx10_1_modifiers(const struct amdgpu_device *adev,
358
-
uint64_t **mods, uint64_t *size, uint64_t *capacity)
357
+
static void amdgpu_dm_plane_add_gfx10_1_modifiers(const struct amdgpu_device *adev,
358
+
uint64_t **mods,
359
+
uint64_t *size,
360
+
uint64_t *capacity)
359
361
{
360
362
int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
361
363
362
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
363
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
364
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
365
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
366
-
AMD_FMT_MOD_SET(DCC, 1) |
367
-
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
368
-
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
369
-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
364
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
365
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
366
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
367
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
368
+
AMD_FMT_MOD_SET(DCC, 1) |
369
+
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
370
+
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
371
+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
370
372
371
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
372
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
373
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
374
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
375
-
AMD_FMT_MOD_SET(DCC, 1) |
376
-
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
377
-
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
378
-
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
379
-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
373
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
374
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
375
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
376
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
377
+
AMD_FMT_MOD_SET(DCC, 1) |
378
+
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
379
+
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
380
+
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
381
+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
380
382
381
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
382
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
383
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
384
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
383
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
384
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
385
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
386
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
385
387
386
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
387
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
388
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
389
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
388
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
389
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
390
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10) |
391
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits));
390
392
391
393
392
-
/* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
393
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
394
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
395
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
394
+
/* Only supported for 64bpp, will be filtered in amdgpu_dm_plane_format_mod_supported */
395
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
396
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
397
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
396
398
397
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
398
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
399
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
399
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
400
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
401
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
400
402
}
401
403
402
-
static void add_gfx9_modifiers(const struct amdgpu_device *adev,
403
-
uint64_t **mods, uint64_t *size, uint64_t *capacity)
404
+
static void amdgpu_dm_plane_add_gfx9_modifiers(const struct amdgpu_device *adev,
405
+
uint64_t **mods,
406
+
uint64_t *size,
407
+
uint64_t *capacity)
404
408
{
405
409
int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
406
410
int pipe_xor_bits = min(8, pipes +
···
425
421
*/
426
422
427
423
if (has_constant_encode) {
428
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
429
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
430
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
431
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
432
-
AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
433
-
AMD_FMT_MOD_SET(DCC, 1) |
434
-
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
435
-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
436
-
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1));
424
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
425
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
426
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
427
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
428
+
AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
429
+
AMD_FMT_MOD_SET(DCC, 1) |
430
+
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
431
+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
432
+
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1));
437
433
}
438
434
439
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
440
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
441
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
442
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
443
-
AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
444
-
AMD_FMT_MOD_SET(DCC, 1) |
445
-
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
446
-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
447
-
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0));
435
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
436
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
437
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
438
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
439
+
AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
440
+
AMD_FMT_MOD_SET(DCC, 1) |
441
+
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
442
+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
443
+
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0));
448
444
449
445
if (has_constant_encode) {
450
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
451
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
452
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
453
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
454
-
AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
455
-
AMD_FMT_MOD_SET(DCC, 1) |
456
-
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
457
-
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
458
-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
459
-
460
-
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
461
-
AMD_FMT_MOD_SET(RB, rb) |
462
-
AMD_FMT_MOD_SET(PIPE, pipes));
446
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
447
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
448
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
449
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
450
+
AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
451
+
AMD_FMT_MOD_SET(DCC, 1) |
452
+
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
453
+
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
454
+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
455
+
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
456
+
AMD_FMT_MOD_SET(RB, rb) |
457
+
AMD_FMT_MOD_SET(PIPE, pipes));
463
458
}
464
459
465
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
466
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
467
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
468
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
469
-
AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
470
-
AMD_FMT_MOD_SET(DCC, 1) |
471
-
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
472
-
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
473
-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
474
-
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) |
475
-
AMD_FMT_MOD_SET(RB, rb) |
476
-
AMD_FMT_MOD_SET(PIPE, pipes));
460
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
461
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
462
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
463
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
464
+
AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
465
+
AMD_FMT_MOD_SET(DCC, 1) |
466
+
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
467
+
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
468
+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B) |
469
+
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 0) |
470
+
AMD_FMT_MOD_SET(RB, rb) |
471
+
AMD_FMT_MOD_SET(PIPE, pipes));
477
472
}
478
473
479
474
/*
480
475
* Only supported for 64bpp on Raven, will be filtered on format in
481
-
* dm_plane_format_mod_supported.
476
+
* amdgpu_dm_plane_format_mod_supported.
482
477
*/
483
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
484
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) |
485
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
486
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
487
-
AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
478
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
479
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D_X) |
480
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
481
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
482
+
AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
488
483
489
484
if (adev->family == AMDGPU_FAMILY_RV) {
490
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
491
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
492
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
493
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
494
-
AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
485
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
486
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
487
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9) |
488
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
489
+
AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits));
495
490
}
496
491
497
492
/*
498
493
* Only supported for 64bpp on Raven, will be filtered on format in
499
-
* dm_plane_format_mod_supported.
494
+
* amdgpu_dm_plane_format_mod_supported.
500
495
*/
501
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
502
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
503
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
496
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
497
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
498
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
504
499
505
500
if (adev->family == AMDGPU_FAMILY_RV) {
506
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
507
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
508
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
501
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
502
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
503
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
509
504
}
510
505
}
511
506
512
-
static void add_gfx10_3_modifiers(const struct amdgpu_device *adev,
513
-
uint64_t **mods, uint64_t *size, uint64_t *capacity)
507
+
static void amdgpu_dm_plane_add_gfx10_3_modifiers(const struct amdgpu_device *adev,
508
+
uint64_t **mods,
509
+
uint64_t *size,
510
+
uint64_t *capacity)
514
511
{
515
512
int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
516
513
int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);
517
514
518
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
519
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
520
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
521
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
522
-
AMD_FMT_MOD_SET(PACKERS, pkrs) |
523
-
AMD_FMT_MOD_SET(DCC, 1) |
524
-
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
525
-
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
526
-
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
527
-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
515
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
516
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
517
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
518
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
519
+
AMD_FMT_MOD_SET(PACKERS, pkrs) |
520
+
AMD_FMT_MOD_SET(DCC, 1) |
521
+
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
522
+
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
523
+
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
524
+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
528
525
529
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
530
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
531
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
532
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
533
-
AMD_FMT_MOD_SET(PACKERS, pkrs) |
534
-
AMD_FMT_MOD_SET(DCC, 1) |
535
-
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
536
-
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
537
-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
526
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
527
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
528
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
529
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
530
+
AMD_FMT_MOD_SET(PACKERS, pkrs) |
531
+
AMD_FMT_MOD_SET(DCC, 1) |
532
+
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
533
+
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
534
+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
538
535
539
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
540
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
541
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
542
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
543
-
AMD_FMT_MOD_SET(PACKERS, pkrs) |
544
-
AMD_FMT_MOD_SET(DCC, 1) |
545
-
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
546
-
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
547
-
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
548
-
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
549
-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
536
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
537
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
538
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
539
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
540
+
AMD_FMT_MOD_SET(PACKERS, pkrs) |
541
+
AMD_FMT_MOD_SET(DCC, 1) |
542
+
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
543
+
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
544
+
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
545
+
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
546
+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
550
547
551
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
552
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
553
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
554
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
555
-
AMD_FMT_MOD_SET(PACKERS, pkrs) |
556
-
AMD_FMT_MOD_SET(DCC, 1) |
557
-
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
558
-
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
559
-
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
560
-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
548
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
549
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
550
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
551
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
552
+
AMD_FMT_MOD_SET(PACKERS, pkrs) |
553
+
AMD_FMT_MOD_SET(DCC, 1) |
554
+
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
555
+
AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
556
+
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
557
+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
561
558
562
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
563
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
564
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
565
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
566
-
AMD_FMT_MOD_SET(PACKERS, pkrs));
559
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
560
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
561
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
562
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
563
+
AMD_FMT_MOD_SET(PACKERS, pkrs));
567
564
568
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
569
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
570
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
571
-
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
572
-
AMD_FMT_MOD_SET(PACKERS, pkrs));
565
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
566
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S_X) |
567
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
568
+
AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
569
+
AMD_FMT_MOD_SET(PACKERS, pkrs));
573
570
574
-
/* Only supported for 64bpp, will be filtered in dm_plane_format_mod_supported */
575
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
576
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
577
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
571
+
/* Only supported for 64bpp, will be filtered in amdgpu_dm_plane_format_mod_supported */
572
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
573
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D) |
574
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
578
575
579
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
580
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
581
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
576
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
577
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_S) |
578
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX9));
582
579
}
583
580
584
-
static void add_gfx11_modifiers(struct amdgpu_device *adev,
581
+
static void amdgpu_dm_plane_add_gfx11_modifiers(struct amdgpu_device *adev,
585
582
uint64_t **mods, uint64_t *size, uint64_t *capacity)
586
583
{
587
584
int num_pipes = 0;
···
633
628
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
634
629
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B);
635
630
636
-
add_modifier(mods, size, capacity, modifier_dcc_best);
637
-
add_modifier(mods, size, capacity, modifier_dcc_4k);
631
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_best);
632
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_4k);
638
633
639
-
add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1));
640
-
add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1));
634
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1));
635
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1));
641
636
642
-
add_modifier(mods, size, capacity, modifier_r_x);
637
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, modifier_r_x);
643
638
}
644
639
645
-
add_modifier(mods, size, capacity, AMD_FMT_MOD |
646
-
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
647
-
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D));
640
+
amdgpu_dm_plane_add_modifier(mods, size, capacity, AMD_FMT_MOD |
641
+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
642
+
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_D));
648
643
}
649
644
650
-
static int get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
645
+
static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsigned int plane_type, uint64_t **mods)
651
646
{
652
647
uint64_t size = 0, capacity = 128;
653
648
*mods = NULL;
···
659
654
*mods = kmalloc(capacity * sizeof(uint64_t), GFP_KERNEL);
660
655
661
656
if (plane_type == DRM_PLANE_TYPE_CURSOR) {
662
-
add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
663
-
add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
657
+
amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
658
+
amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
664
659
return *mods ? 0 : -ENOMEM;
665
660
}
666
661
667
662
switch (adev->family) {
668
663
case AMDGPU_FAMILY_AI:
669
664
case AMDGPU_FAMILY_RV:
670
-
add_gfx9_modifiers(adev, mods, &size, &capacity);
665
+
amdgpu_dm_plane_add_gfx9_modifiers(adev, mods, &size, &capacity);
671
666
break;
672
667
case AMDGPU_FAMILY_NV:
673
668
case AMDGPU_FAMILY_VGH:
···
675
670
case AMDGPU_FAMILY_GC_10_3_6:
676
671
case AMDGPU_FAMILY_GC_10_3_7:
677
672
if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
678
-
add_gfx10_3_modifiers(adev, mods, &size, &capacity);
673
+
amdgpu_dm_plane_add_gfx10_3_modifiers(adev, mods, &size, &capacity);
679
674
else
680
-
add_gfx10_1_modifiers(adev, mods, &size, &capacity);
675
+
amdgpu_dm_plane_add_gfx10_1_modifiers(adev, mods, &size, &capacity);
681
676
break;
682
677
case AMDGPU_FAMILY_GC_11_0_0:
683
678
case AMDGPU_FAMILY_GC_11_0_1:
684
679
case AMDGPU_FAMILY_GC_11_5_0:
685
-
add_gfx11_modifiers(adev, mods, &size, &capacity);
680
+
amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &size, &capacity);
686
681
break;
687
682
}
688
683
689
-
add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
684
+
amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_LINEAR);
690
685
691
686
/* INVALID marks the end of the list. */
692
-
add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
687
+
amdgpu_dm_plane_add_modifier(mods, &size, &capacity, DRM_FORMAT_MOD_INVALID);
693
688
694
689
if (!*mods)
695
690
return -ENOMEM;
···
697
692
return 0;
698
693
}
699
694
700
-
static int get_plane_formats(const struct drm_plane *plane,
701
-
const struct dc_plane_cap *plane_cap,
702
-
uint32_t *formats, int max_formats)
695
+
static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane,
696
+
const struct dc_plane_cap *plane_cap,
697
+
uint32_t *formats, int max_formats)
703
698
{
704
699
int i, num_formats = 0;
705
700
···
823
818
}
824
819
825
820
if (adev->family >= AMDGPU_FAMILY_AI) {
826
-
ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
827
-
rotation, plane_size,
828
-
tiling_info, dcc,
829
-
address,
830
-
force_disable_dcc);
821
+
ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
822
+
rotation, plane_size,
823
+
tiling_info, dcc,
824
+
address,
825
+
force_disable_dcc);
831
826
if (ret)
832
827
return ret;
833
828
} else {
834
-
fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
829
+
amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
835
830
}
836
831
837
832
return 0;
838
833
}
839
834
840
-
static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
841
-
struct drm_plane_state *new_state)
835
+
static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane,
836
+
struct drm_plane_state *new_state)
842
837
{
843
838
struct amdgpu_framebuffer *afb;
844
839
struct drm_gem_object *obj;
···
933
928
return r;
934
929
}
935
930
936
-
static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
937
-
struct drm_plane_state *old_state)
931
+
static void amdgpu_dm_plane_helper_cleanup_fb(struct drm_plane *plane,
932
+
struct drm_plane_state *old_state)
938
933
{
939
934
struct amdgpu_bo *rbo;
940
935
int r;
···
954
949
amdgpu_bo_unref(&rbo);
955
950
}
956
951
957
-
static void get_min_max_dc_plane_scaling(struct drm_device *dev,
952
+
static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev,
958
953
struct drm_framebuffer *fb,
959
954
int *min_downscale, int *max_upscale)
960
955
{
···
1035
1030
}
1036
1031
1037
1032
/* Get min/max allowed scaling factors from plane caps. */
1038
-
get_min_max_dc_plane_scaling(state->crtc->dev, fb,
1039
-
&min_downscale, &max_upscale);
1033
+
amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->crtc->dev, fb,
1034
+
&min_downscale, &max_upscale);
1040
1035
/*
1041
1036
* Convert to drm convention: 16.16 fixed point, instead of dc's
1042
1037
* 1.0 == 1000. Also drm scaling is src/dst instead of dc's
···
1106
1101
1107
1102
/* Validate scaling per-format with DC plane caps */
1108
1103
if (state->plane && state->plane->dev && state->fb) {
1109
-
get_min_max_dc_plane_scaling(state->plane->dev, state->fb,
1110
-
&min_downscale, &max_upscale);
1104
+
amdgpu_dm_plane_get_min_max_dc_plane_scaling(state->plane->dev, state->fb,
1105
+
&min_downscale, &max_upscale);
1111
1106
} else {
1112
1107
min_downscale = 250;
1113
1108
max_upscale = 16000;
···
1133
1128
return 0;
1134
1129
}
1135
1130
1136
-
static int dm_plane_atomic_check(struct drm_plane *plane,
1137
-
struct drm_atomic_state *state)
1131
+
static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane,
1132
+
struct drm_atomic_state *state)
1138
1133
{
1139
1134
struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1140
1135
plane);
···
1172
1167
return -EINVAL;
1173
1168
}
1174
1169
1175
-
static int dm_plane_atomic_async_check(struct drm_plane *plane,
1176
-
struct drm_atomic_state *state)
1170
+
static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane,
1171
+
struct drm_atomic_state *state)
1177
1172
{
1178
1173
/* Only support async updates on cursor planes. */
1179
1174
if (plane->type != DRM_PLANE_TYPE_CURSOR)
···
1182
1177
return 0;
1183
1178
}
1184
1179
1185
-
static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
1186
-
struct dc_cursor_position *position)
1180
+
static int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
1181
+
struct dc_cursor_position *position)
1187
1182
{
1188
1183
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1189
1184
int x, y;
···
1246
1241
amdgpu_crtc->crtc_id, plane->state->crtc_w,
1247
1242
plane->state->crtc_h);
1248
1243
1249
-
ret = get_cursor_position(plane, crtc, &position);
1244
+
ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position);
1250
1245
if (ret)
1251
1246
return;
1252
1247
···
1295
1290
}
1296
1291
}
1297
1292
1298
-
static void dm_plane_atomic_async_update(struct drm_plane *plane,
1299
-
struct drm_atomic_state *state)
1293
+
static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane,
1294
+
struct drm_atomic_state *state)
1300
1295
{
1301
1296
struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
1302
1297
plane);
···
1320
1315
}
1321
1316
1322
1317
static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
1323
-
.prepare_fb = dm_plane_helper_prepare_fb,
1324
-
.cleanup_fb = dm_plane_helper_cleanup_fb,
1325
-
.atomic_check = dm_plane_atomic_check,
1326
-
.atomic_async_check = dm_plane_atomic_async_check,
1327
-
.atomic_async_update = dm_plane_atomic_async_update
1318
+
.prepare_fb = amdgpu_dm_plane_helper_prepare_fb,
1319
+
.cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb,
1320
+
.atomic_check = amdgpu_dm_plane_atomic_check,
1321
+
.atomic_async_check = amdgpu_dm_plane_atomic_async_check,
1322
+
.atomic_async_update = amdgpu_dm_plane_atomic_async_update
1328
1323
};
1329
1324
1330
-
static void dm_drm_plane_reset(struct drm_plane *plane)
1325
+
static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane)
1331
1326
{
1332
1327
struct dm_plane_state *amdgpu_state = NULL;
1333
1328
···
1341
1336
__drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
1342
1337
}
1343
1338
1344
-
static struct drm_plane_state *
1345
-
dm_drm_plane_duplicate_state(struct drm_plane *plane)
1339
+
static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct drm_plane *plane)
1346
1340
{
1347
1341
struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
1348
1342
···
1360
1356
return &dm_plane_state->base;
1361
1357
}
1362
1358
1363
-
static bool dm_plane_format_mod_supported(struct drm_plane *plane,
1364
-
uint32_t format,
1365
-
uint64_t modifier)
1359
+
static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane,
1360
+
uint32_t format,
1361
+
uint64_t modifier)
1366
1362
{
1367
1363
struct amdgpu_device *adev = drm_to_adev(plane->dev);
1368
1364
const struct drm_format_info *info = drm_format_info(format);
1369
1365
int i;
1370
1366
1371
-
enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;
1367
+
enum dm_micro_swizzle microtile = amdgpu_dm_plane_modifier_gfx9_swizzle_mode(modifier) & 3;
1372
1368
1373
1369
if (!info)
1374
1370
return false;
···
1405
1401
info->cpp[0] < 8)
1406
1402
return false;
1407
1403
1408
-
if (modifier_has_dcc(modifier)) {
1404
+
if (amdgpu_dm_plane_modifier_has_dcc(modifier)) {
1409
1405
/* Per radeonsi comments 16/64 bpp are more complicated. */
1410
1406
if (info->cpp[0] != 4)
1411
1407
return false;
···
1419
1415
return true;
1420
1416
}
1421
1417
1422
-
static void dm_drm_plane_destroy_state(struct drm_plane *plane,
1423
-
struct drm_plane_state *state)
1418
+
static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane,
1419
+
struct drm_plane_state *state)
1424
1420
{
1425
1421
struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
1426
1422
···
1434
1430
.update_plane = drm_atomic_helper_update_plane,
1435
1431
.disable_plane = drm_atomic_helper_disable_plane,
1436
1432
.destroy = drm_plane_helper_destroy,
1437
-
.reset = dm_drm_plane_reset,
1438
-
.atomic_duplicate_state = dm_drm_plane_duplicate_state,
1439
-
.atomic_destroy_state = dm_drm_plane_destroy_state,
1440
-
.format_mod_supported = dm_plane_format_mod_supported,
1433
+
.reset = amdgpu_dm_plane_drm_plane_reset,
1434
+
.atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state,
1435
+
.atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state,
1436
+
.format_mod_supported = amdgpu_dm_plane_format_mod_supported,
1441
1437
};
1442
1438
1443
1439
int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
···
1451
1447
unsigned int supported_rotations;
1452
1448
uint64_t *modifiers = NULL;
1453
1449
1454
-
num_formats = get_plane_formats(plane, plane_cap, formats,
1455
-
ARRAY_SIZE(formats));
1450
+
num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats,
1451
+
ARRAY_SIZE(formats));
1456
1452
1457
-
res = get_plane_modifiers(dm->adev, plane->type, &modifiers);
1453
+
res = amdgpu_dm_plane_get_plane_modifiers(dm->adev, plane->type, &modifiers);
1458
1454
if (res)
1459
1455
return res;
1460
1456
···
1524
1520
return 0;
1525
1521
}
1526
1522
1527
-
bool is_video_format(uint32_t format)
1523
+
bool amdgpu_dm_plane_is_video_format(uint32_t format)
1528
1524
{
1529
1525
int i;
1530
1526