Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x
* 'sh-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-3.x:
sh: fix the compile error in setup-sh7757.c
serial: sh-sci: report CTS as active for get_mctrl
sh: Add unaligned memory access for PC relative intructions
sh: Fix unaligned memory access for branches without delay slots
sh: Fix up fallout from cpuidle changes.
serial: sh-sci: console Runtime PM support
sh: Fix conflicting definitions of ptrace_triggered
serial: sh-sci: fix DMA build by including dma-mapping.h
serial: sh-sci: Fix up default regtype probing.
sh: intc: enable both edges GPIO interrupts on sh7372
shwdt: fix usage of mod_timer
clocksource: sh_cmt: wait for CMCNT on init V2
+135
-15
+1
-1
arch/sh/include/asm/ptrace.h
+1
-1
arch/sh/include/asm/ptrace.h
···
123
123
struct perf_event;
124
124
struct perf_sample_data;
125
125
126
-
extern void ptrace_triggered(struct perf_event *bp, int nmi,
126
+
extern void ptrace_triggered(struct perf_event *bp,
127
127
struct perf_sample_data *data, struct pt_regs *regs);
128
128
129
129
#define task_pt_regs(task) \
+1
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+1
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+1
-1
arch/sh/kernel/idle.c
+1
-1
arch/sh/kernel/idle.c
+37
arch/sh/kernel/traps_32.c
+37
arch/sh/kernel/traps_32.c
···
316
316
break;
317
317
}
318
318
break;
319
+
320
+
case 9: /* mov.w @(disp,PC),Rn */
321
+
srcu = (unsigned char __user *)regs->pc;
322
+
srcu += 4;
323
+
srcu += (instruction & 0x00FF) << 1;
324
+
dst = (unsigned char *)rn;
325
+
*(unsigned long *)dst = 0;
326
+
327
+
#if !defined(__LITTLE_ENDIAN__)
328
+
dst += 2;
329
+
#endif
330
+
331
+
if (ma->from(dst, srcu, 2))
332
+
goto fetch_fault;
333
+
sign_extend(2, dst);
334
+
ret = 0;
335
+
break;
336
+
337
+
case 0xd: /* mov.l @(disp,PC),Rn */
338
+
srcu = (unsigned char __user *)(regs->pc & ~0x3);
339
+
srcu += 4;
340
+
srcu += (instruction & 0x00FF) << 2;
341
+
dst = (unsigned char *)rn;
342
+
*(unsigned long *)dst = 0;
343
+
344
+
if (ma->from(dst, srcu, 4))
345
+
goto fetch_fault;
346
+
ret = 0;
347
+
break;
319
348
}
320
349
return ret;
321
350
···
495
466
case 0x0500: /* mov.w @(disp,Rm),R0 */
496
467
goto simple;
497
468
case 0x0B00: /* bf lab - no delayslot*/
469
+
ret = 0;
498
470
break;
499
471
case 0x0F00: /* bf/s lab */
500
472
ret = handle_delayslot(regs, instruction, ma);
···
509
479
}
510
480
break;
511
481
case 0x0900: /* bt lab - no delayslot */
482
+
ret = 0;
512
483
break;
513
484
case 0x0D00: /* bt/s lab */
514
485
ret = handle_delayslot(regs, instruction, ma);
···
525
494
}
526
495
break;
527
496
497
+
case 0x9000: /* mov.w @(disp,Rm),Rn */
498
+
goto simple;
499
+
528
500
case 0xA000: /* bra label */
529
501
ret = handle_delayslot(regs, instruction, ma);
530
502
if (ret==0)
···
541
507
regs->pc += SH_PC_12BIT_OFFSET(instruction);
542
508
}
543
509
break;
510
+
511
+
case 0xD000: /* mov.l @(disp,Rm),Rn */
512
+
goto simple;
544
513
}
545
514
return ret;
546
515
+32
-2
drivers/clocksource/sh_cmt.c
+32
-2
drivers/clocksource/sh_cmt.c
···
26
26
#include <linux/clk.h>
27
27
#include <linux/irq.h>
28
28
#include <linux/err.h>
29
+
#include <linux/delay.h>
29
30
#include <linux/clocksource.h>
30
31
#include <linux/clockchips.h>
31
32
#include <linux/sh_timer.h>
···
151
150
152
151
static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
153
152
{
154
-
int ret;
153
+
int k, ret;
155
154
156
155
/* enable clock */
157
156
ret = clk_enable(p->clk);
158
157
if (ret) {
159
158
dev_err(&p->pdev->dev, "cannot enable clock\n");
160
-
return ret;
159
+
goto err0;
161
160
}
162
161
163
162
/* make sure channel is disabled */
···
175
174
sh_cmt_write(p, CMCOR, 0xffffffff);
176
175
sh_cmt_write(p, CMCNT, 0);
177
176
177
+
/*
178
+
* According to the sh73a0 user's manual, as CMCNT can be operated
179
+
* only by the RCLK (Pseudo 32 KHz), there's one restriction on
180
+
* modifying CMCNT register; two RCLK cycles are necessary before
181
+
* this register is either read or any modification of the value
182
+
* it holds is reflected in the LSI's actual operation.
183
+
*
184
+
* While at it, we're supposed to clear out the CMCNT as of this
185
+
* moment, so make sure it's processed properly here. This will
186
+
* take RCLKx2 at maximum.
187
+
*/
188
+
for (k = 0; k < 100; k++) {
189
+
if (!sh_cmt_read(p, CMCNT))
190
+
break;
191
+
udelay(1);
192
+
}
193
+
194
+
if (sh_cmt_read(p, CMCNT)) {
195
+
dev_err(&p->pdev->dev, "cannot clear CMCNT\n");
196
+
ret = -ETIMEDOUT;
197
+
goto err1;
198
+
}
199
+
178
200
/* enable channel */
179
201
sh_cmt_start_stop_ch(p, 1);
180
202
return 0;
203
+
err1:
204
+
/* stop clock */
205
+
clk_disable(p->clk);
206
+
207
+
err0:
208
+
return ret;
181
209
}
182
210
183
211
static void sh_cmt_disable(struct sh_cmt_priv *p)
+3
drivers/sh/intc/chip.c
+3
drivers/sh/intc/chip.c
+60
-11
drivers/tty/serial/sh-sci.c
+60
-11
drivers/tty/serial/sh-sci.c
···
47
47
#include <linux/ctype.h>
48
48
#include <linux/err.h>
49
49
#include <linux/dmaengine.h>
50
+
#include <linux/dma-mapping.h>
50
51
#include <linux/scatterlist.h>
51
52
#include <linux/slab.h>
52
53
···
96
95
#endif
97
96
98
97
struct notifier_block freq_transition;
98
+
99
+
#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
100
+
unsigned short saved_smr;
101
+
unsigned short saved_fcr;
102
+
unsigned char saved_brr;
103
+
#endif
99
104
};
100
105
101
106
/* Function prototypes */
···
1083
1076
/* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1084
1077
and CTS/RTS */
1085
1078
1086
-
return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
1079
+
return TIOCM_DTR | TIOCM_RTS | TIOCM_CTS | TIOCM_DSR;
1087
1080
}
1088
1081
1089
1082
#ifdef CONFIG_SERIAL_SH_SCI_DMA
···
1640
1633
return ((freq + 16 * bps) / (32 * bps) - 1);
1641
1634
}
1642
1635
1636
+
static void sci_reset(struct uart_port *port)
1637
+
{
1638
+
unsigned int status;
1639
+
1640
+
do {
1641
+
status = sci_in(port, SCxSR);
1642
+
} while (!(status & SCxSR_TEND(port)));
1643
+
1644
+
sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1645
+
1646
+
if (port->type != PORT_SCI)
1647
+
sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1648
+
}
1649
+
1643
1650
static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1644
1651
struct ktermios *old)
1645
1652
{
1646
1653
struct sci_port *s = to_sci_port(port);
1647
-
unsigned int status, baud, smr_val, max_baud;
1654
+
unsigned int baud, smr_val, max_baud;
1648
1655
int t = -1;
1649
1656
u16 scfcr = 0;
1650
1657
···
1678
1657
1679
1658
sci_port_enable(s);
1680
1659
1681
-
do {
1682
-
status = sci_in(port, SCxSR);
1683
-
} while (!(status & SCxSR_TEND(port)));
1684
-
1685
-
sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1686
-
1687
-
if (port->type != PORT_SCI)
1688
-
sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1660
+
sci_reset(port);
1689
1661
1690
1662
smr_val = sci_in(port, SCSMR) & 3;
1691
1663
···
2051
2037
if (options)
2052
2038
uart_parse_options(options, &baud, &parity, &bits, &flow);
2053
2039
2054
-
/* TODO: disable clock */
2040
+
sci_port_disable(sci_port);
2041
+
2055
2042
return uart_set_options(port, co, baud, parity, bits, flow);
2056
2043
}
2057
2044
···
2095
2080
return 0;
2096
2081
}
2097
2082
2083
+
#define uart_console(port) ((port)->cons->index == (port)->line)
2084
+
2085
+
static int sci_runtime_suspend(struct device *dev)
2086
+
{
2087
+
struct sci_port *sci_port = dev_get_drvdata(dev);
2088
+
struct uart_port *port = &sci_port->port;
2089
+
2090
+
if (uart_console(port)) {
2091
+
sci_port->saved_smr = sci_in(port, SCSMR);
2092
+
sci_port->saved_brr = sci_in(port, SCBRR);
2093
+
sci_port->saved_fcr = sci_in(port, SCFCR);
2094
+
}
2095
+
return 0;
2096
+
}
2097
+
2098
+
static int sci_runtime_resume(struct device *dev)
2099
+
{
2100
+
struct sci_port *sci_port = dev_get_drvdata(dev);
2101
+
struct uart_port *port = &sci_port->port;
2102
+
2103
+
if (uart_console(port)) {
2104
+
sci_reset(port);
2105
+
sci_out(port, SCSMR, sci_port->saved_smr);
2106
+
sci_out(port, SCBRR, sci_port->saved_brr);
2107
+
sci_out(port, SCFCR, sci_port->saved_fcr);
2108
+
sci_out(port, SCSCR, sci_port->cfg->scscr);
2109
+
}
2110
+
return 0;
2111
+
}
2112
+
2098
2113
#define SCI_CONSOLE (&serial_console)
2099
2114
2100
2115
#else
···
2134
2089
}
2135
2090
2136
2091
#define SCI_CONSOLE NULL
2092
+
#define sci_runtime_suspend NULL
2093
+
#define sci_runtime_resume NULL
2137
2094
2138
2095
#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2139
2096
···
2251
2204
}
2252
2205
2253
2206
static const struct dev_pm_ops sci_dev_pm_ops = {
2207
+
.runtime_suspend = sci_runtime_suspend,
2208
+
.runtime_resume = sci_runtime_resume,
2254
2209
.suspend = sci_suspend,
2255
2210
.resume = sci_resume,
2256
2211
};