Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (32 commits)
ARM: mmp: Change the way we use timer 0 as clockevent timer.
ARM: mmp: Switch to using timer 1 as clocksource timer.
ARM: mmp: Also start timer 1 on boot.
ARM: pxa168/gplugd: free correct GPIO
ARM: pxa168/gplugd: get rid of mfp-gplugd.h
ARM: pxa: fix logic error in PJ4 iWMMXt handling
mach-sa1100: fix PCI build problem
omap: timer: Set dmtimer used as clocksource in autoreload mode
OMAP3: am3517crane: remove NULL board_mux from board file
arm: mach-omap2: mux: use kstrdup()
arch:arm:plat-omap:iovmm: remove unused variable 'va'
Update Nook Color machine 3284 to common Encore name
am3505/3517: Various platform defines for UART4
OMAP: hwmod: fix build break on non-OMAP4 multi-OMAP2 builds
OMAP: Fix linking error in twl-common.c for OMAP2/3/4 only builds
iMX: Fix build for iMX53
ARM: mx5: board-cpuimx51.c fixup irq_to_gpio() usage
OMAP2+: PM: SmartReflex: use put_sync_suspend for IRQ-safe disabling
OMAP3: beagle: don't touch omap_device internals
OMAP1: enable GENERIC_IRQ_CHIP
...
+252
-186
+3
-3
arch/arm/kernel/iwmmxt.S
+3
-3
arch/arm/kernel/iwmmxt.S
···
195
195
196
196
@ enable access to CP0 and CP1
197
197
XSC(mrc p15, 0, r4, c15, c1, 0)
198
-
XSC(orr r4, r4, #0xf)
198
+
XSC(orr r4, r4, #0x3)
199
199
XSC(mcr p15, 0, r4, c15, c1, 0)
200
200
PJ4(mrc p15, 0, r4, c1, c0, 2)
201
-
PJ4(orr r4, r4, #0x3)
201
+
PJ4(orr r4, r4, #0xf)
202
202
PJ4(mcr p15, 0, r4, c1, c0, 2)
203
203
204
204
mov r0, #0 @ nothing to load
···
313
313
teq r2, r3 @ next task owns it?
314
314
movne pc, lr @ no: leave Concan disabled
315
315
316
-
1: @ flip Conan access
316
+
1: @ flip Concan access
317
317
XSC(eor r1, r1, #0x3)
318
318
XSC(mcr p15, 0, r1, c15, c1, 0)
319
319
PJ4(eor r1, r1, #0xf)
+3
arch/arm/mach-imx/clock-imx25.c
+3
arch/arm/mach-imx/clock-imx25.c
···
331
331
__raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
332
332
CRM_BASE + 0x64);
333
333
334
+
/* Clock source for gpt is ahb_div */
335
+
__raw_writel(__raw_readl(CRM_BASE+0x64) & ~(1 << 5), CRM_BASE + 0x64);
336
+
334
337
mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
335
338
336
339
return 0;
+13
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+13
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
···
30
30
#include <linux/input.h>
31
31
#include <linux/gpio.h>
32
32
#include <linux/delay.h>
33
+
#include <sound/tlv320aic32x4.h>
33
34
#include <asm/mach-types.h>
34
35
#include <asm/mach/arch.h>
35
36
#include <asm/mach/time.h>
···
197
196
.invert = 0,
198
197
};
199
198
199
+
static struct aic32x4_pdata visstrim_m10_aic32x4_pdata = {
200
+
.power_cfg = AIC32X4_PWR_MICBIAS_2075_LDOIN |
201
+
AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE |
202
+
AIC32X4_PWR_AIC32X4_LDO_ENABLE |
203
+
AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36 |
204
+
AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED,
205
+
.micpga_routing = AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K |
206
+
AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K,
207
+
.swapdacs = false,
208
+
};
209
+
200
210
static struct i2c_board_info visstrim_m10_i2c_devices[] = {
201
211
{
202
212
I2C_BOARD_INFO("pca9555", 0x20),
···
215
203
},
216
204
{
217
205
I2C_BOARD_INFO("tlv320aic32x4", 0x18),
206
+
.platform_data = &visstrim_m10_aic32x4_pdata,
218
207
}
219
208
};
220
209
+2
-2
arch/arm/mach-imx/mach-mx31ads.c
+2
-2
arch/arm/mach-imx/mach-mx31ads.c
···
468
468
#endif
469
469
};
470
470
471
-
static void mxc_init_i2c(void)
471
+
static void __init mxc_init_i2c(void)
472
472
{
473
473
i2c_register_board_info(1, mx31ads_i2c1_devices,
474
474
ARRAY_SIZE(mx31ads_i2c1_devices));
···
486
486
MX31_PIN_STXD5__STXD5,
487
487
};
488
488
489
-
static void mxc_init_audio(void)
489
+
static void __init mxc_init_audio(void)
490
490
{
491
491
imx31_add_imx_ssi(0, NULL);
492
492
mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
+1
-1
arch/arm/mach-imx/mach-mx31lilly.c
+1
-1
arch/arm/mach-imx/mach-mx31lilly.c
+15
-7
arch/arm/mach-mmp/gplugd.c
+15
-7
arch/arm/mach-mmp/gplugd.c
···
16
16
#include <mach/gpio.h>
17
17
#include <mach/pxa168.h>
18
18
#include <mach/mfp-pxa168.h>
19
-
#include <mach/mfp-gplugd.h>
20
19
21
20
#include "common.h"
22
21
23
22
static unsigned long gplugd_pin_config[] __initdata = {
24
23
/* UART3 */
25
-
GPIO8_UART3_SOUT,
26
-
GPIO9_UART3_SIN,
27
-
GPI1O_UART3_CTS,
28
-
GPI11_UART3_RTS,
24
+
GPIO8_UART3_TXD,
25
+
GPIO9_UART3_RXD,
26
+
GPIO1O_UART3_CTS,
27
+
GPIO11_UART3_RTS,
28
+
29
+
/* USB OTG PEN */
30
+
GPIO18_GPIO,
29
31
30
32
/* MMC2 */
31
33
GPIO28_MMC2_CMD,
···
111
109
GPIO105_CI2C_SDA,
112
110
GPIO106_CI2C_SCL,
113
111
112
+
/* SPI NOR Flash on SSP2 */
113
+
GPIO107_SSP2_RXD,
114
+
GPIO108_SSP2_TXD,
115
+
GPIO110_GPIO, /* SPI_CSn */
116
+
GPIO111_SSP2_CLK,
117
+
114
118
/* Select JTAG */
115
119
GPIO109_GPIO,
116
120
···
162
154
"frequency\n");
163
155
} else {
164
156
gpio_direction_output(35, 1);
165
-
gpio_free(104);
157
+
gpio_free(35);
166
158
}
167
159
168
160
if (unlikely(gpio_request(85, "DISP_FREQ_SEL_2"))) {
···
170
162
"frequency\n");
171
163
} else {
172
164
gpio_direction_output(85, 0);
173
-
gpio_free(104);
165
+
gpio_free(85);
174
166
}
175
167
}
176
168
-52
arch/arm/mach-mmp/include/mach/mfp-gplugd.h
-52
arch/arm/mach-mmp/include/mach/mfp-gplugd.h
···
1
-
/*
2
-
* linux/arch/arm/mach-mmp/include/mach/mfp-gplugd.h
3
-
*
4
-
* MFP definitions used in gplugD
5
-
*
6
-
* This program is free software; you can redistribute it and/or modify
7
-
* it under the terms of the GNU General Public License version 2 as
8
-
* published by the Free Software Foundation.
9
-
*/
10
-
11
-
#ifndef __MACH_MFP_GPLUGD_H
12
-
#define __MACH_MFP_GPLUGD_H
13
-
14
-
#include <plat/mfp.h>
15
-
#include <mach/mfp.h>
16
-
17
-
/* UART3 */
18
-
#define GPIO8_UART3_SOUT MFP_CFG(GPIO8, AF2)
19
-
#define GPIO9_UART3_SIN MFP_CFG(GPIO9, AF2)
20
-
#define GPI1O_UART3_CTS MFP_CFG(GPIO10, AF2)
21
-
#define GPI11_UART3_RTS MFP_CFG(GPIO11, AF2)
22
-
23
-
/* MMC2 */
24
-
#define GPIO28_MMC2_CMD MFP_CFG_DRV(GPIO28, AF6, FAST)
25
-
#define GPIO29_MMC2_CLK MFP_CFG_DRV(GPIO29, AF6, FAST)
26
-
#define GPIO30_MMC2_DAT0 MFP_CFG_DRV(GPIO30, AF6, FAST)
27
-
#define GPIO31_MMC2_DAT1 MFP_CFG_DRV(GPIO31, AF6, FAST)
28
-
#define GPIO32_MMC2_DAT2 MFP_CFG_DRV(GPIO32, AF6, FAST)
29
-
#define GPIO33_MMC2_DAT3 MFP_CFG_DRV(GPIO33, AF6, FAST)
30
-
31
-
/* I2S */
32
-
#undef GPIO114_I2S_FRM
33
-
#undef GPIO115_I2S_BCLK
34
-
35
-
#define GPIO114_I2S_FRM MFP_CFG_DRV(GPIO114, AF1, FAST)
36
-
#define GPIO115_I2S_BCLK MFP_CFG_DRV(GPIO115, AF1, FAST)
37
-
#define GPIO116_I2S_TXD MFP_CFG_DRV(GPIO116, AF1, FAST)
38
-
39
-
/* MMC4 */
40
-
#define GPIO125_MMC4_DAT3 MFP_CFG_DRV(GPIO125, AF7, FAST)
41
-
#define GPIO126_MMC4_DAT2 MFP_CFG_DRV(GPIO126, AF7, FAST)
42
-
#define GPIO127_MMC4_DAT1 MFP_CFG_DRV(GPIO127, AF7, FAST)
43
-
#define GPIO0_2_MMC4_DAT0 MFP_CFG_DRV(GPIO0_2, AF7, FAST)
44
-
#define GPIO1_2_MMC4_CMD MFP_CFG_DRV(GPIO1_2, AF7, FAST)
45
-
#define GPIO2_2_MMC4_CLK MFP_CFG_DRV(GPIO2_2, AF7, FAST)
46
-
47
-
/* OTG GPIO */
48
-
#define GPIO_USB_OTG_PEN 18
49
-
#define GPIO_USB_OIDIR 20
50
-
51
-
/* Other GPIOs are 35, 84, 85 */
52
-
#endif /* __MACH_MFP_GPLUGD_H */
+32
-5
arch/arm/mach-mmp/include/mach/mfp-pxa168.h
+32
-5
arch/arm/mach-mmp/include/mach/mfp-pxa168.h
···
203
203
#define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3)
204
204
205
205
/* UART */
206
+
#define GPIO8_UART3_TXD MFP_CFG(GPIO8, AF2)
207
+
#define GPIO9_UART3_RXD MFP_CFG(GPIO9, AF2)
208
+
#define GPIO1O_UART3_CTS MFP_CFG(GPIO10, AF2)
209
+
#define GPIO11_UART3_RTS MFP_CFG(GPIO11, AF2)
206
210
#define GPIO88_UART2_TXD MFP_CFG(GPIO88, AF2)
207
211
#define GPIO89_UART2_RXD MFP_CFG(GPIO89, AF2)
208
212
#define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST)
···
235
231
#define GPIO43_MMC1_CLK MFP_CFG(GPIO43, AF1)
236
232
#define GPIO53_MMC1_CD MFP_CFG(GPIO53, AF1)
237
233
#define GPIO46_MMC1_WP MFP_CFG(GPIO46, AF1)
234
+
235
+
/* MMC2 */
236
+
#define GPIO28_MMC2_CMD MFP_CFG_DRV(GPIO28, AF6, FAST)
237
+
#define GPIO29_MMC2_CLK MFP_CFG_DRV(GPIO29, AF6, FAST)
238
+
#define GPIO30_MMC2_DAT0 MFP_CFG_DRV(GPIO30, AF6, FAST)
239
+
#define GPIO31_MMC2_DAT1 MFP_CFG_DRV(GPIO31, AF6, FAST)
240
+
#define GPIO32_MMC2_DAT2 MFP_CFG_DRV(GPIO32, AF6, FAST)
241
+
#define GPIO33_MMC2_DAT3 MFP_CFG_DRV(GPIO33, AF6, FAST)
242
+
243
+
/* MMC4 */
244
+
#define GPIO125_MMC4_DAT3 MFP_CFG_DRV(GPIO125, AF7, FAST)
245
+
#define GPIO126_MMC4_DAT2 MFP_CFG_DRV(GPIO126, AF7, FAST)
246
+
#define GPIO127_MMC4_DAT1 MFP_CFG_DRV(GPIO127, AF7, FAST)
247
+
#define GPIO0_2_MMC4_DAT0 MFP_CFG_DRV(GPIO0_2, AF7, FAST)
248
+
#define GPIO1_2_MMC4_CMD MFP_CFG_DRV(GPIO1_2, AF7, FAST)
249
+
#define GPIO2_2_MMC4_CLK MFP_CFG_DRV(GPIO2_2, AF7, FAST)
238
250
239
251
/* LCD */
240
252
#define GPIO84_LCD_CS MFP_CFG(GPIO84, AF1)
···
289
269
#define GPIO106_CI2C_SCL MFP_CFG(GPIO106, AF1)
290
270
291
271
/* I2S */
292
-
#define GPIO113_I2S_MCLK MFP_CFG(GPIO113,AF6)
293
-
#define GPIO114_I2S_FRM MFP_CFG(GPIO114,AF1)
294
-
#define GPIO115_I2S_BCLK MFP_CFG(GPIO115,AF1)
295
-
#define GPIO116_I2S_RXD MFP_CFG(GPIO116,AF2)
296
-
#define GPIO117_I2S_TXD MFP_CFG(GPIO117,AF2)
272
+
#define GPIO113_I2S_MCLK MFP_CFG(GPIO113, AF6)
273
+
#define GPIO114_I2S_FRM MFP_CFG(GPIO114, AF1)
274
+
#define GPIO115_I2S_BCLK MFP_CFG(GPIO115, AF1)
275
+
#define GPIO116_I2S_RXD MFP_CFG(GPIO116, AF2)
276
+
#define GPIO116_I2S_TXD MFP_CFG(GPIO116, AF1)
277
+
#define GPIO117_I2S_TXD MFP_CFG(GPIO117, AF2)
297
278
298
279
/* PWM */
299
280
#define GPIO96_PWM3_OUT MFP_CFG(GPIO96, AF1)
···
344
323
#define GPIO100_MII_MDC MFP_CFG(GPIO100, AF5)
345
324
#define GPIO101_MII_MDIO MFP_CFG(GPIO101, AF5)
346
325
#define GPIO103_RX_DV MFP_CFG(GPIO103, AF5)
326
+
327
+
/* SSP2 */
328
+
#define GPIO107_SSP2_RXD MFP_CFG(GPIO107, AF4)
329
+
#define GPIO108_SSP2_TXD MFP_CFG(GPIO108, AF4)
330
+
#define GPIO111_SSP2_CLK MFP_CFG(GPIO111, AF4)
331
+
#define GPIO112_SSP2_FRM MFP_CFG(GPIO112, AF4)
347
332
348
333
#endif /* __ASM_MACH_MFP_PXA168_H */
+44
-18
arch/arm/mach-mmp/time.c
+44
-18
arch/arm/mach-mmp/time.c
···
51
51
{
52
52
int delay = 100;
53
53
54
-
__raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(0));
54
+
__raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1));
55
55
56
56
while (delay--)
57
57
cpu_relax();
58
58
59
-
return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0));
59
+
return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1));
60
60
}
61
61
62
62
unsigned long long notrace sched_clock(void)
···
75
75
{
76
76
struct clock_event_device *c = dev_id;
77
77
78
-
/* disable and clear pending interrupt status */
79
-
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
80
-
__raw_writel(0x1, TIMERS_VIRT_BASE + TMR_ICR(0));
78
+
/*
79
+
* Clear pending interrupt status.
80
+
*/
81
+
__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
82
+
83
+
/*
84
+
* Disable timer 0.
85
+
*/
86
+
__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
87
+
81
88
c->event_handler(c);
89
+
82
90
return IRQ_HANDLED;
83
91
}
84
92
85
93
static int timer_set_next_event(unsigned long delta,
86
94
struct clock_event_device *dev)
87
95
{
88
-
unsigned long flags, next;
96
+
unsigned long flags;
89
97
90
98
local_irq_save(flags);
91
99
92
-
/* clear pending interrupt status and enable */
100
+
/*
101
+
* Disable timer 0.
102
+
*/
103
+
__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
104
+
105
+
/*
106
+
* Clear and enable timer match 0 interrupt.
107
+
*/
93
108
__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
94
109
__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
95
110
96
-
next = timer_read() + delta;
97
-
__raw_writel(next, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
111
+
/*
112
+
* Setup new clockevent timer value.
113
+
*/
114
+
__raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
115
+
116
+
/*
117
+
* Enable timer 0.
118
+
*/
119
+
__raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER);
98
120
99
121
local_irq_restore(flags);
122
+
100
123
return 0;
101
124
}
102
125
···
168
145
static void __init timer_config(void)
169
146
{
170
147
uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
171
-
uint32_t cer = __raw_readl(TIMERS_VIRT_BASE + TMR_CER);
172
-
uint32_t cmr = __raw_readl(TIMERS_VIRT_BASE + TMR_CMR);
173
148
174
-
__raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */
149
+
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */
175
150
176
-
ccr &= (cpu_is_mmp2()) ? TMR_CCR_CS_0(0) : TMR_CCR_CS_0(3);
151
+
ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
152
+
(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
177
153
__raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
178
154
179
-
/* free-running mode */
180
-
__raw_writel(cmr | 0x01, TIMERS_VIRT_BASE + TMR_CMR);
155
+
/* set timer 0 to periodic mode, and timer 1 to free-running mode */
156
+
__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CMR);
181
157
182
-
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* free-running */
158
+
__raw_writel(0x1, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* periodic */
183
159
__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */
184
160
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
185
161
186
-
/* enable timer counter */
187
-
__raw_writel(cer | 0x01, TIMERS_VIRT_BASE + TMR_CER);
162
+
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */
163
+
__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1)); /* clear status */
164
+
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1));
165
+
166
+
/* enable timer 1 counter */
167
+
__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CER);
188
168
}
189
169
190
170
static struct irqaction timer_irq = {
+1
-1
arch/arm/mach-mx5/board-cpuimx51.c
+1
-1
arch/arm/mach-mx5/board-cpuimx51.c
···
81
81
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
82
82
}, {
83
83
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
84
-
.irq = irq_to_gpio(CPUIMX51_QUARTD_GPIO),
84
+
.irq = gpio_to_irq(CPUIMX51_QUARTD_GPIO),
85
85
.irqflags = IRQF_TRIGGER_HIGH,
86
86
.uartclk = CPUIMX51_QUART_XTAL,
87
87
.regshift = CPUIMX51_QUART_REGSHIFT,
+1
-1
arch/arm/mach-mx5/board-mx51_babbage.c
+1
-1
arch/arm/mach-mx5/board-mx51_babbage.c
+3
-3
arch/arm/mach-mx5/board-mx51_efikamx.c
+3
-3
arch/arm/mach-mx5/board-mx51_efikamx.c
···
108
108
gpio_request(EFIKAMX_PCBID2, "pcbid2");
109
109
gpio_direction_input(EFIKAMX_PCBID2);
110
110
111
-
id = gpio_get_value(EFIKAMX_PCBID0);
112
-
id |= gpio_get_value(EFIKAMX_PCBID1) << 1;
113
-
id |= gpio_get_value(EFIKAMX_PCBID2) << 2;
111
+
id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0;
112
+
id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1;
113
+
id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2;
114
114
115
115
switch (id) {
116
116
case 7:
+8
-7
arch/arm/mach-mx5/board-mx51_efikasb.c
+8
-7
arch/arm/mach-mx5/board-mx51_efikasb.c
···
156
156
{
157
157
.code = KEY_POWER,
158
158
.gpio = EFIKASB_PWRKEY,
159
-
.type = EV_PWR,
159
+
.type = EV_KEY,
160
160
.desc = "Power Button",
161
161
.wakeup = 1,
162
-
.debounce_interval = 10, /* ms */
162
+
.active_low = 1,
163
163
},
164
164
{
165
165
.code = SW_LID,
166
166
.gpio = EFIKASB_LID,
167
167
.type = EV_SW,
168
168
.desc = "Lid Switch",
169
+
.active_low = 1,
169
170
},
170
171
{
171
-
/* SW_RFKILLALL vs KEY_RFKILL ? */
172
-
.code = SW_RFKILL_ALL,
172
+
.code = KEY_RFKILL,
173
173
.gpio = EFIKASB_RFKILL,
174
-
.type = EV_SW,
174
+
.type = EV_KEY,
175
175
.desc = "rfkill",
176
+
.active_low = 1,
176
177
},
177
178
};
178
179
···
225
224
gpio_request(EFIKASB_PCBID1, "pcb id1");
226
225
gpio_direction_input(EFIKASB_PCBID1);
227
226
228
-
id = gpio_get_value(EFIKASB_PCBID0);
229
-
id |= gpio_get_value(EFIKASB_PCBID1) << 1;
227
+
id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0;
228
+
id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1;
230
229
231
230
switch (id) {
232
231
default:
+5
-1
arch/arm/mach-mx5/clock-mx51-mx53.c
+5
-1
arch/arm/mach-mx5/clock-mx51-mx53.c
···
271
271
int i = 0;
272
272
273
273
pllbase = _get_pll_base(clk);
274
-
reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
274
+
reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
275
+
if (reg & MXC_PLL_DP_CTL_UPEN)
276
+
return 0;
277
+
278
+
reg |= MXC_PLL_DP_CTL_UPEN;
275
279
__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
276
280
277
281
/* Wait for lock */
+1
-1
arch/arm/mach-mx5/mx51_efika.c
+1
-1
arch/arm/mach-mx5/mx51_efika.c
-1
arch/arm/mach-omap2/Kconfig
-1
arch/arm/mach-omap2/Kconfig
-2
arch/arm/mach-omap2/board-am3517crane.c
-2
arch/arm/mach-omap2/board-am3517crane.c
+10
-13
arch/arm/mach-omap2/board-omap3beagle.c
+10
-13
arch/arm/mach-omap2/board-omap3beagle.c
···
491
491
492
492
/* Custom OPP enabled for all xM versions */
493
493
if (cpu_is_omap3630()) {
494
-
struct omap_hwmod *mh = omap_hwmod_lookup("mpu");
495
-
struct omap_hwmod *dh = omap_hwmod_lookup("iva");
496
-
struct device *dev;
494
+
struct device *mpu_dev, *iva_dev;
497
495
498
-
if (!mh || !dh) {
496
+
mpu_dev = omap2_get_mpuss_device();
497
+
iva_dev = omap2_get_iva_device();
498
+
499
+
if (!mpu_dev || !iva_dev) {
499
500
pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
500
-
__func__, mh, dh);
501
+
__func__, mpu_dev, iva_dev);
501
502
return;
502
503
}
503
504
/* Enable MPU 1GHz and lower opps */
504
-
dev = &mh->od->pdev.dev;
505
-
r = opp_enable(dev, 800000000);
505
+
r = opp_enable(mpu_dev, 800000000);
506
506
/* TODO: MPU 1GHz needs SR and ABB */
507
507
508
508
/* Enable IVA 800MHz and lower opps */
509
-
dev = &dh->od->pdev.dev;
510
-
r |= opp_enable(dev, 660000000);
509
+
r |= opp_enable(iva_dev, 660000000);
511
510
/* TODO: DSP 800MHz needs SR and ABB */
512
511
if (r) {
513
512
pr_err("%s: failed to enable higher opp %d\n",
···
515
516
* Cleanup - disable the higher freqs - we dont care
516
517
* about the results
517
518
*/
518
-
dev = &mh->od->pdev.dev;
519
-
opp_disable(dev, 800000000);
520
-
dev = &dh->od->pdev.dev;
521
-
opp_disable(dev, 660000000);
519
+
opp_disable(mpu_dev, 800000000);
520
+
opp_disable(iva_dev, 660000000);
522
521
}
523
522
}
524
523
return;
+24
-1
arch/arm/mach-omap2/cminst44xx.h
+24
-1
arch/arm/mach-omap2/cminst44xx.h
···
18
18
extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
19
19
20
20
extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
21
-
extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
21
+
22
+
# ifdef CONFIG_ARCH_OMAP4
23
+
extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
24
+
u16 clkctrl_offs);
22
25
23
26
extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
24
27
u16 clkctrl_offs);
25
28
extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
26
29
u16 clkctrl_offs);
30
+
31
+
# else
32
+
33
+
static inline int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
34
+
u16 clkctrl_offs)
35
+
{
36
+
return 0;
37
+
}
38
+
39
+
static inline void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst,
40
+
s16 cdoffs, u16 clkctrl_offs)
41
+
{
42
+
}
43
+
44
+
static inline void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
45
+
u16 clkctrl_offs)
46
+
{
47
+
}
48
+
49
+
# endif
27
50
28
51
/*
29
52
* In an ideal world, we would not export these low-level functions,
+4
-10
arch/arm/mach-omap2/mux.c
+4
-10
arch/arm/mach-omap2/mux.c
···
821
821
if (!omap_mux_options)
822
822
return;
823
823
824
-
options = kmalloc(strlen(omap_mux_options) + 1, GFP_KERNEL);
824
+
options = kstrdup(omap_mux_options, GFP_KERNEL);
825
825
if (!options)
826
826
return;
827
827
828
-
strcpy(options, omap_mux_options);
829
828
next_opt = options;
830
829
831
830
while ((token = strsep(&next_opt, ",")) != NULL) {
···
854
855
855
856
for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
856
857
if (src->muxnames[i]) {
857
-
dst->muxnames[i] =
858
-
kmalloc(strlen(src->muxnames[i]) + 1,
859
-
GFP_KERNEL);
858
+
dst->muxnames[i] = kstrdup(src->muxnames[i],
859
+
GFP_KERNEL);
860
860
if (!dst->muxnames[i])
861
861
goto free;
862
-
strcpy(dst->muxnames[i], src->muxnames[i]);
863
862
}
864
863
}
865
864
866
865
#ifdef CONFIG_DEBUG_FS
867
866
for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
868
867
if (src->balls[i]) {
869
-
dst->balls[i] =
870
-
kmalloc(strlen(src->balls[i]) + 1,
871
-
GFP_KERNEL);
868
+
dst->balls[i] = kstrdup(src->balls[i], GFP_KERNEL);
872
869
if (!dst->balls[i])
873
870
goto free;
874
-
strcpy(dst->balls[i], src->balls[i]);
875
871
}
876
872
}
877
873
#endif
+2
-1
arch/arm/mach-omap2/smartreflex.c
+2
-1
arch/arm/mach-omap2/smartreflex.c
···
621
621
sr_v2_disable(sr);
622
622
}
623
623
624
-
pm_runtime_put_sync(&sr->pdev->dev);
624
+
pm_runtime_put_sync_suspend(&sr->pdev->dev);
625
625
}
626
626
627
627
/**
···
860
860
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
861
861
862
862
pm_runtime_enable(&pdev->dev);
863
+
pm_runtime_irq_safe(&pdev->dev);
863
864
864
865
sr_info->pdev = pdev;
865
866
sr_info->srid = pdev->id;
+2
-1
arch/arm/mach-omap2/timer.c
+2
-1
arch/arm/mach-omap2/timer.c
···
293
293
pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
294
294
gptimer_id, clksrc.rate);
295
295
296
-
__omap_dm_timer_load_start(clksrc.io_base, OMAP_TIMER_CTRL_ST, 0, 1);
296
+
__omap_dm_timer_load_start(clksrc.io_base,
297
+
OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
297
298
init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
298
299
299
300
if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
+41
-37
arch/arm/mach-omap2/twl-common.c
+41
-37
arch/arm/mach-omap2/twl-common.c
···
48
48
omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
49
49
}
50
50
51
-
static struct twl4030_usb_data omap4_usb_pdata = {
52
-
.phy_init = omap4430_phy_init,
53
-
.phy_exit = omap4430_phy_exit,
54
-
.phy_power = omap4430_phy_power,
55
-
.phy_set_clock = omap4430_phy_set_clk,
56
-
.phy_suspend = omap4430_phy_suspend,
57
-
};
58
-
51
+
#if defined(CONFIG_ARCH_OMAP3)
59
52
static struct twl4030_usb_data omap3_usb_pdata = {
60
53
.usb_mode = T2_USB_MODE_ULPI,
61
54
};
···
113
120
},
114
121
.num_consumer_supplies = ARRAY_SIZE(omap3_vpll2_supplies),
115
122
.consumer_supplies = omap3_vpll2_supplies,
123
+
};
124
+
125
+
void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
126
+
u32 pdata_flags, u32 regulators_flags)
127
+
{
128
+
if (!pmic_data->irq_base)
129
+
pmic_data->irq_base = TWL4030_IRQ_BASE;
130
+
if (!pmic_data->irq_end)
131
+
pmic_data->irq_end = TWL4030_IRQ_END;
132
+
133
+
/* Common platform data configurations */
134
+
if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
135
+
pmic_data->usb = &omap3_usb_pdata;
136
+
137
+
if (pdata_flags & TWL_COMMON_PDATA_BCI && !pmic_data->bci)
138
+
pmic_data->bci = &omap3_bci_pdata;
139
+
140
+
if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc)
141
+
pmic_data->madc = &omap3_madc_pdata;
142
+
143
+
if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->audio)
144
+
pmic_data->audio = &omap3_audio_pdata;
145
+
146
+
/* Common regulator configurations */
147
+
if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
148
+
pmic_data->vdac = &omap3_vdac_idata;
149
+
150
+
if (regulators_flags & TWL_COMMON_REGULATOR_VPLL2 && !pmic_data->vpll2)
151
+
pmic_data->vpll2 = &omap3_vpll2_idata;
152
+
}
153
+
#endif /* CONFIG_ARCH_OMAP3 */
154
+
155
+
#if defined(CONFIG_ARCH_OMAP4)
156
+
static struct twl4030_usb_data omap4_usb_pdata = {
157
+
.phy_init = omap4430_phy_init,
158
+
.phy_exit = omap4430_phy_exit,
159
+
.phy_power = omap4430_phy_power,
160
+
.phy_set_clock = omap4430_phy_set_clk,
161
+
.phy_suspend = omap4430_phy_suspend,
116
162
};
117
163
118
164
static struct regulator_init_data omap4_vdac_idata = {
···
305
273
!pmic_data->clk32kg)
306
274
pmic_data->clk32kg = &omap4_clk32kg_idata;
307
275
}
308
-
309
-
void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
310
-
u32 pdata_flags, u32 regulators_flags)
311
-
{
312
-
if (!pmic_data->irq_base)
313
-
pmic_data->irq_base = TWL4030_IRQ_BASE;
314
-
if (!pmic_data->irq_end)
315
-
pmic_data->irq_end = TWL4030_IRQ_END;
316
-
317
-
/* Common platform data configurations */
318
-
if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
319
-
pmic_data->usb = &omap3_usb_pdata;
320
-
321
-
if (pdata_flags & TWL_COMMON_PDATA_BCI && !pmic_data->bci)
322
-
pmic_data->bci = &omap3_bci_pdata;
323
-
324
-
if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc)
325
-
pmic_data->madc = &omap3_madc_pdata;
326
-
327
-
if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->audio)
328
-
pmic_data->audio = &omap3_audio_pdata;
329
-
330
-
/* Common regulator configurations */
331
-
if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
332
-
pmic_data->vdac = &omap3_vdac_idata;
333
-
334
-
if (regulators_flags & TWL_COMMON_REGULATOR_VPLL2 && !pmic_data->vpll2)
335
-
pmic_data->vpll2 = &omap3_vpll2_idata;
336
-
}
276
+
#endif /* CONFIG_ARCH_OMAP4 */
+1
arch/arm/mach-sa1100/pci-nanoengine.c
+1
arch/arm/mach-sa1100/pci-nanoengine.c
+8
arch/arm/plat-mxc/include/mach/debug-macro.S
+8
arch/arm/plat-mxc/include/mach/debug-macro.S
···
44
44
#define UART_PADDR MX51_UART1_BASE_ADDR
45
45
#endif
46
46
47
+
/* iMX50/53 have same addresses, but not iMX51 */
48
+
#if defined(CONFIG_SOC_IMX50) || defined(CONFIG_SOC_IMX53)
49
+
#ifdef UART_PADDR
50
+
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
51
+
#endif
52
+
#define UART_PADDR MX53_UART1_BASE_ADDR
53
+
#endif
54
+
47
55
#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
48
56
49
57
.macro addruart, rp, rv
+17
-14
arch/arm/plat-mxc/include/mach/iomux-mx53.h
+17
-14
arch/arm/plat-mxc/include/mach/iomux-mx53.h
···
30
30
#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
31
31
PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
32
32
PAD_CTL_SRE_FAST)
33
+
#define PAD_CTRL_I2C (PAD_CTL_SRE_FAST | PAD_CTL_ODE | PAD_CTL_PKE | \
34
+
PAD_CTL_PUE | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP \
35
+
| PAD_CTL_HYS)
33
36
34
37
#define _MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0)
35
38
#define _MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0)
···
1259
1256
#define MX53_PAD_KEY_COL3__GPIO4_12 (_MX53_PAD_KEY_COL3__GPIO4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1260
1257
#define MX53_PAD_KEY_COL3__USBOH3_H2_DP (_MX53_PAD_KEY_COL3__USBOH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
1261
1258
#define MX53_PAD_KEY_COL3__SPDIF_IN1 (_MX53_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1262
-
#define MX53_PAD_KEY_COL3__I2C2_SCL (_MX53_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1259
+
#define MX53_PAD_KEY_COL3__I2C2_SCL (_MX53_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
1263
1260
#define MX53_PAD_KEY_COL3__ECSPI1_SS3 (_MX53_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1264
1261
#define MX53_PAD_KEY_COL3__FEC_CRS (_MX53_PAD_KEY_COL3__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
1265
1262
#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK (_MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
···
1267
1264
#define MX53_PAD_KEY_ROW3__GPIO4_13 (_MX53_PAD_KEY_ROW3__GPIO4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1268
1265
#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM (_MX53_PAD_KEY_ROW3__USBOH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
1269
1266
#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK (_MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1270
-
#define MX53_PAD_KEY_ROW3__I2C2_SDA (_MX53_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1267
+
#define MX53_PAD_KEY_ROW3__I2C2_SDA (_MX53_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
1271
1268
#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT (_MX53_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
1272
1269
#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP (_MX53_PAD_KEY_ROW3__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
1273
1270
#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 (_MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
···
1539
1536
#define MX53_PAD_CSI0_DAT8__KPP_COL_7 (_MX53_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1540
1537
#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX53_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1541
1538
#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC (_MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
1542
-
#define MX53_PAD_CSI0_DAT8__I2C1_SDA (_MX53_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1539
+
#define MX53_PAD_CSI0_DAT8__I2C1_SDA (_MX53_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
1543
1540
#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 (_MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
1544
1541
#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 (_MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1545
1542
#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 (_MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
···
1547
1544
#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 (_MX53_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1548
1545
#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX53_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1549
1546
#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR (_MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1550
-
#define MX53_PAD_CSI0_DAT9__I2C1_SCL (_MX53_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1547
+
#define MX53_PAD_CSI0_DAT9__I2C1_SCL (_MX53_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
1551
1548
#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 (_MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
1552
1549
#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 (_MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1553
1550
#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 (_MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
···
1634
1631
#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1635
1632
#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS (_MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1636
1633
#define MX53_PAD_EIM_EB2__ECSPI1_SS0 (_MX53_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1637
-
#define MX53_PAD_EIM_EB2__I2C2_SCL (_MX53_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1634
+
#define MX53_PAD_EIM_EB2__I2C2_SCL (_MX53_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
1638
1635
#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 (_MX53_PAD_EIM_D16__EMI_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1639
1636
#define MX53_PAD_EIM_D16__GPIO3_16 (_MX53_PAD_EIM_D16__GPIO3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1640
1637
#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 (_MX53_PAD_EIM_D16__IPU_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1641
1638
#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK (_MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1642
1639
#define MX53_PAD_EIM_D16__ECSPI1_SCLK (_MX53_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1643
-
#define MX53_PAD_EIM_D16__I2C2_SDA (_MX53_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1640
+
#define MX53_PAD_EIM_D16__I2C2_SDA (_MX53_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
1644
1641
#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 (_MX53_PAD_EIM_D17__EMI_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1645
1642
#define MX53_PAD_EIM_D17__GPIO3_17 (_MX53_PAD_EIM_D17__GPIO3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1646
1643
#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 (_MX53_PAD_EIM_D17__IPU_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1647
1644
#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN (_MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
1648
1645
#define MX53_PAD_EIM_D17__ECSPI1_MISO (_MX53_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1649
-
#define MX53_PAD_EIM_D17__I2C3_SCL (_MX53_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1646
+
#define MX53_PAD_EIM_D17__I2C3_SCL (_MX53_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
1650
1647
#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 (_MX53_PAD_EIM_D18__EMI_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1651
1648
#define MX53_PAD_EIM_D18__GPIO3_18 (_MX53_PAD_EIM_D18__GPIO3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1652
1649
#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 (_MX53_PAD_EIM_D18__IPU_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1653
1650
#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO (_MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1654
1651
#define MX53_PAD_EIM_D18__ECSPI1_MOSI (_MX53_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1655
-
#define MX53_PAD_EIM_D18__I2C3_SDA (_MX53_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1652
+
#define MX53_PAD_EIM_D18__I2C3_SDA (_MX53_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
1656
1653
#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS (_MX53_PAD_EIM_D18__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1657
1654
#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 (_MX53_PAD_EIM_D19__EMI_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1658
1655
#define MX53_PAD_EIM_D19__GPIO3_19 (_MX53_PAD_EIM_D19__GPIO3_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
···
1675
1672
#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 (_MX53_PAD_EIM_D21__IPU_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1676
1673
#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK (_MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1677
1674
#define MX53_PAD_EIM_D21__CSPI_SCLK (_MX53_PAD_EIM_D21__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1678
-
#define MX53_PAD_EIM_D21__I2C1_SCL (_MX53_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1675
+
#define MX53_PAD_EIM_D21__I2C1_SCL (_MX53_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
1679
1676
#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX53_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
1680
1677
#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 (_MX53_PAD_EIM_D22__EMI_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1681
1678
#define MX53_PAD_EIM_D22__GPIO3_22 (_MX53_PAD_EIM_D22__GPIO3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
···
1735
1732
#define MX53_PAD_EIM_D28__UART2_CTS (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
1736
1733
#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO (_MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1737
1734
#define MX53_PAD_EIM_D28__CSPI_MOSI (_MX53_PAD_EIM_D28__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1738
-
#define MX53_PAD_EIM_D28__I2C1_SDA (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1735
+
#define MX53_PAD_EIM_D28__I2C1_SDA (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
1739
1736
#define MX53_PAD_EIM_D28__IPU_EXT_TRIG (_MX53_PAD_EIM_D28__IPU_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
1740
1737
#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 (_MX53_PAD_EIM_D28__IPU_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1741
1738
#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 (_MX53_PAD_EIM_D29__EMI_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
···
2300
2297
#define MX53_PAD_GPIO_9__SCC_FAIL_STATE (_MX53_PAD_GPIO_9__SCC_FAIL_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
2301
2298
#define MX53_PAD_GPIO_3__ESAI1_HCKR (_MX53_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
2302
2299
#define MX53_PAD_GPIO_3__GPIO1_3 (_MX53_PAD_GPIO_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2303
-
#define MX53_PAD_GPIO_3__I2C3_SCL (_MX53_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
2300
+
#define MX53_PAD_GPIO_3__I2C3_SCL (_MX53_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
2304
2301
#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN (_MX53_PAD_GPIO_3__DPLLIP1_TOG_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
2305
2302
#define MX53_PAD_GPIO_3__CCM_CLKO2 (_MX53_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2306
2303
#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
···
2308
2305
#define MX53_PAD_GPIO_3__MLB_MLBCLK (_MX53_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2309
2306
#define MX53_PAD_GPIO_6__ESAI1_SCKT (_MX53_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
2310
2307
#define MX53_PAD_GPIO_6__GPIO1_6 (_MX53_PAD_GPIO_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2311
-
#define MX53_PAD_GPIO_6__I2C3_SDA (_MX53_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
2308
+
#define MX53_PAD_GPIO_6__I2C3_SDA (_MX53_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
2312
2309
#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX53_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2313
2310
#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX53_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
2314
2311
#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
···
2336
2333
#define MX53_PAD_GPIO_5__CCM_CLKO (_MX53_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
2337
2334
#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2338
2335
#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 (_MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2339
-
#define MX53_PAD_GPIO_5__I2C3_SCL (_MX53_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
2336
+
#define MX53_PAD_GPIO_5__I2C3_SCL (_MX53_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(PAD_CTRL_I2C))
2340
2337
#define MX53_PAD_GPIO_5__CCM_PLL1_BYP (_MX53_PAD_GPIO_5__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2341
2338
#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX53_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2342
2339
#define MX53_PAD_GPIO_7__GPIO1_7 (_MX53_PAD_GPIO_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
···
2359
2356
#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT (_MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
2360
2357
#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 (_MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2361
2358
#define MX53_PAD_GPIO_16__SPDIF_IN1 (_MX53_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2362
-
#define MX53_PAD_GPIO_16__I2C3_SDA (_MX53_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
2359
+
#define MX53_PAD_GPIO_16__I2C3_SDA (_MX53_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(PAD_CTRL_I2C))
2363
2360
#define MX53_PAD_GPIO_16__SJC_DE_B (_MX53_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2364
2361
#define MX53_PAD_GPIO_17__ESAI1_TX0 (_MX53_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2365
2362
#define MX53_PAD_GPIO_17__GPIO7_12 (_MX53_PAD_GPIO_17__GPIO7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+1
arch/arm/plat-omap/Kconfig
+1
arch/arm/plat-omap/Kconfig
+5
arch/arm/plat-omap/include/plat/dma.h
+5
arch/arm/plat-omap/include/plat/dma.h
···
195
195
196
196
#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */
197
197
#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */
198
+
199
+
/* Only for AM35xx */
200
+
#define AM35XX_DMA_UART4_TX 54
201
+
#define AM35XX_DMA_UART4_RX 55
202
+
198
203
/*----------------------------------------------------------------------------*/
199
204
200
205
#define OMAP1_DMA_TOUT_IRQ (1 << 0)
+1
arch/arm/plat-omap/include/plat/irqs.h
+1
arch/arm/plat-omap/include/plat/irqs.h
+3
arch/arm/plat-omap/include/plat/serial.h
+3
arch/arm/plat-omap/include/plat/serial.h
···
56
56
#define TI816X_UART2_BASE 0x48022000
57
57
#define TI816X_UART3_BASE 0x48024000
58
58
59
+
/* AM3505/3517 UART4 */
60
+
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
61
+
59
62
/* External port on Zoom2/3 */
60
63
#define ZOOM_UART_BASE 0x10000000
61
64
#define ZOOM_UART_VIRT 0xfa400000
-3
arch/arm/plat-omap/iovmm.c
-3
arch/arm/plat-omap/iovmm.c
+1
-1
arch/arm/tools/mach-types
+1
-1
arch/arm/tools/mach-types
···
910
910
uemd MACH_UEMD UEMD 3281
911
911
ccwmx51mut MACH_CCWMX51MUT CCWMX51MUT 3282
912
912
rockhopper MACH_ROCKHOPPER ROCKHOPPER 3283
913
-
nookcolor MACH_NOOKCOLOR NOOKCOLOR 3284
913
+
encore MACH_ENCORE ENCORE 3284
914
914
hkdkc100 MACH_HKDKC100 HKDKC100 3285
915
915
ts42xx MACH_TS42XX TS42XX 3286
916
916
aebl MACH_AEBL AEBL 3287