tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2025-07-18-1' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"Seems like a quiet enough week, xe/amdgpu being the usual suspects,
then mediatek with a few fixes, and otherwise just misc other bits.

dp:
- aux dpcd address fix

xe:
- SR-IOV fixes for GT reset and TLB invalidation
- Fix memory copy direction during migration
- Fix alignment check on migration
- Fix MOCS and page fault init order to correctly account
for topology

amdgpu:
- Fix a DC memory leak
- DCN 4.0.1 degamma LUT fix
- Fix reset counter handling for soft recovery
- GC 8 fix

radeon:
- Drop console locks when suspending/resuming

nouveau:
- ioctl validation fix

panfrost:
- scheduler bug fix

mediatek:
- Add wait_event_timeout when disabling plane
- only announce AFBC if really supported
- mtk_dpi: Reorder output formats on MT8195/88"

* tag 'drm-fixes-2025-07-18-1' of https://gitlab.freedesktop.org/drm/kernel:
drm/mediatek: mtk_dpi: Reorder output formats on MT8195/88
drm/mediatek: only announce AFBC if really supported
drm/mediatek: Add wait_event_timeout when disabling plane
drm/xe/pf: Resend PF provisioning after GT reset
drm/xe/pf: Prepare to stop SR-IOV support prior GT reset
drm/xe/migrate: Fix alignment check
drm/xe: Move page fault init after topology init
drm/xe/mocs: Initialize MOCS index early
drm/xe/migrate: fix copy direction in access_memory
drm/xe: Dont skip TLB invalidations on VF
drm/amdgpu/gfx8: reset compute ring wptr on the GPU on resume
drm/amdgpu: Increase reset counter only on success
drm/radeon: Do not hold console lock during resume
drm/radeon: Do not hold console lock while suspending clients
drm/amd/display: Disable CRTC degamma LUT for DCN401
drm/amd/display: Free memory allocation
drm/dp: Change AUX DPCD probe address from LANE0_1_STATUS to TRAINING_PATTERN_SET
drm/panfrost: Fix scheduler workqueue bug
drm/nouveau: check ioctl command codes better

Linus Torvalds c460535a f0afb7bd

+174 -56
+7 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
··· 427 427 { 428 428 unsigned long flags; 429 429 ktime_t deadline; 430 + bool ret; 430 431 431 432 if (unlikely(ring->adev->debug_disable_soft_recovery)) 432 433 return false; ··· 442 441 dma_fence_set_error(fence, -ENODATA); 443 442 spin_unlock_irqrestore(fence->lock, flags); 444 443 445 - atomic_inc(&ring->adev->gpu_reset_counter); 446 444 while (!dma_fence_is_signaled(fence) && 447 445 ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0) 448 446 ring->funcs->soft_recovery(ring, vmid); 449 447 450 - return dma_fence_is_signaled(fence); 448 + ret = dma_fence_is_signaled(fence); 449 + /* increment the counter only if soft reset worked */ 450 + if (ret) 451 + atomic_inc(&ring->adev->gpu_reset_counter); 452 + 453 + return ret; 451 454 } 452 455 453 456 /*
+1
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
··· 4640 4640 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation)); 4641 4641 /* reset ring buffer */ 4642 4642 ring->wptr = 0; 4643 + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 4643 4644 amdgpu_ring_clear_ring(ring); 4644 4645 } 4645 4646 return 0;
+10 -1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
··· 728 728 * support programmable degamma anywhere. 729 729 */ 730 730 is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch; 731 - drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0, 731 + /* Dont't enable DRM CRTC degamma property for DCN401 since the 732 + * pre-blending degamma LUT doesn't apply to cursor, and therefore 733 + * can't work similar to a post-blending degamma LUT as in other hw 734 + * versions. 735 + * TODO: revisit it once KMS plane color API is merged. 736 + */ 737 + drm_crtc_enable_color_mgmt(&acrtc->base, 738 + (is_dcn && 739 + dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01) ? 740 + MAX_COLOR_LUT_ENTRIES : 0, 732 741 true, MAX_COLOR_LUT_ENTRIES); 733 742 734 743 drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
+2 -1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
··· 1565 1565 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL); 1566 1566 if (!clk_mgr->base.bw_params) { 1567 1567 BREAK_TO_DEBUGGER(); 1568 - kfree(clk_mgr); 1568 + kfree(clk_mgr401); 1569 1569 return NULL; 1570 1570 } 1571 1571 ··· 1576 1576 if (!clk_mgr->wm_range_table) { 1577 1577 BREAK_TO_DEBUGGER(); 1578 1578 kfree(clk_mgr->base.bw_params); 1579 + kfree(clk_mgr401); 1579 1580 return NULL; 1580 1581 } 1581 1582
+1 -1
drivers/gpu/drm/display/drm_dp_helper.c
··· 725 725 * monitor doesn't power down exactly after the throw away read. 726 726 */ 727 727 if (!aux->is_remote) { 728 - ret = drm_dp_dpcd_probe(aux, DP_LANE0_1_STATUS); 728 + ret = drm_dp_dpcd_probe(aux, DP_TRAINING_PATTERN_SET); 729 729 if (ret < 0) 730 730 return ret; 731 731 }
+35 -1
drivers/gpu/drm/mediatek/mtk_crtc.c
··· 719 719 return 0; 720 720 } 721 721 722 + void mtk_crtc_plane_disable(struct drm_crtc *crtc, struct drm_plane *plane) 723 + { 724 + #if IS_REACHABLE(CONFIG_MTK_CMDQ) 725 + struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); 726 + struct mtk_plane_state *plane_state = to_mtk_plane_state(plane->state); 727 + int i; 728 + 729 + /* no need to wait for disabling the plane by CPU */ 730 + if (!mtk_crtc->cmdq_client.chan) 731 + return; 732 + 733 + if (!mtk_crtc->enabled) 734 + return; 735 + 736 + /* set pending plane state to disabled */ 737 + for (i = 0; i < mtk_crtc->layer_nr; i++) { 738 + struct drm_plane *mtk_plane = &mtk_crtc->planes[i]; 739 + struct mtk_plane_state *mtk_plane_state = to_mtk_plane_state(mtk_plane->state); 740 + 741 + if (mtk_plane->index == plane->index) { 742 + memcpy(mtk_plane_state, plane_state, sizeof(*plane_state)); 743 + break; 744 + } 745 + } 746 + mtk_crtc_update_config(mtk_crtc, false); 747 + 748 + /* wait for planes to be disabled by CMDQ */ 749 + wait_event_timeout(mtk_crtc->cb_blocking_queue, 750 + mtk_crtc->cmdq_vblank_cnt == 0, 751 + msecs_to_jiffies(500)); 752 + #endif 753 + } 754 + 722 755 void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 723 756 struct drm_atomic_state *state) 724 757 { ··· 963 930 mtk_ddp_comp_supported_rotations(comp), 964 931 mtk_ddp_comp_get_blend_modes(comp), 965 932 mtk_ddp_comp_get_formats(comp), 966 - mtk_ddp_comp_get_num_formats(comp), i); 933 + mtk_ddp_comp_get_num_formats(comp), 934 + mtk_ddp_comp_is_afbc_supported(comp), i); 967 935 if (ret) 968 936 return ret; 969 937
+1
drivers/gpu/drm/mediatek/mtk_crtc.h
··· 21 21 unsigned int num_conn_routes); 22 22 int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 23 23 struct mtk_plane_state *state); 24 + void mtk_crtc_plane_disable(struct drm_crtc *crtc, struct drm_plane *plane); 24 25 void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 25 26 struct drm_atomic_state *plane_state); 26 27 struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc);
+1
drivers/gpu/drm/mediatek/mtk_ddp_comp.c
··· 366 366 .get_blend_modes = mtk_ovl_get_blend_modes, 367 367 .get_formats = mtk_ovl_get_formats, 368 368 .get_num_formats = mtk_ovl_get_num_formats, 369 + .is_afbc_supported = mtk_ovl_is_afbc_supported, 369 370 }; 370 371 371 372 static const struct mtk_ddp_comp_funcs ddp_postmask = {
+9
drivers/gpu/drm/mediatek/mtk_ddp_comp.h
··· 83 83 u32 (*get_blend_modes)(struct device *dev); 84 84 const u32 *(*get_formats)(struct device *dev); 85 85 size_t (*get_num_formats)(struct device *dev); 86 + bool (*is_afbc_supported)(struct device *dev); 86 87 void (*connect)(struct device *dev, struct device *mmsys_dev, unsigned int next); 87 88 void (*disconnect)(struct device *dev, struct device *mmsys_dev, unsigned int next); 88 89 void (*add)(struct device *dev, struct mtk_mutex *mutex); ··· 293 292 return comp->funcs->get_num_formats(comp->dev); 294 293 295 294 return 0; 295 + } 296 + 297 + static inline bool mtk_ddp_comp_is_afbc_supported(struct mtk_ddp_comp *comp) 298 + { 299 + if (comp->funcs && comp->funcs->is_afbc_supported) 300 + return comp->funcs->is_afbc_supported(comp->dev); 301 + 302 + return false; 296 303 } 297 304 298 305 static inline bool mtk_ddp_comp_add(struct mtk_ddp_comp *comp, struct mtk_mutex *mutex)
+1
drivers/gpu/drm/mediatek/mtk_disp_drv.h
··· 106 106 u32 mtk_ovl_get_blend_modes(struct device *dev); 107 107 const u32 *mtk_ovl_get_formats(struct device *dev); 108 108 size_t mtk_ovl_get_num_formats(struct device *dev); 109 + bool mtk_ovl_is_afbc_supported(struct device *dev); 109 110 110 111 void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex); 111 112 void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex);
+7
drivers/gpu/drm/mediatek/mtk_disp_ovl.c
··· 236 236 return ovl->data->num_formats; 237 237 } 238 238 239 + bool mtk_ovl_is_afbc_supported(struct device *dev) 240 + { 241 + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); 242 + 243 + return ovl->data->supports_afbc; 244 + } 245 + 239 246 int mtk_ovl_clk_enable(struct device *dev) 240 247 { 241 248 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+2 -2
drivers/gpu/drm/mediatek/mtk_dpi.c
··· 1095 1095 }; 1096 1096 1097 1097 static const u32 mt8195_dpi_output_fmts[] = { 1098 - MEDIA_BUS_FMT_BGR888_1X24, 1099 1098 MEDIA_BUS_FMT_RGB888_1X24, 1100 1099 MEDIA_BUS_FMT_RGB888_2X12_LE, 1101 1100 MEDIA_BUS_FMT_RGB888_2X12_BE, ··· 1102 1103 MEDIA_BUS_FMT_YUYV8_1X16, 1103 1104 MEDIA_BUS_FMT_YUYV10_1X20, 1104 1105 MEDIA_BUS_FMT_YUYV12_1X24, 1106 + MEDIA_BUS_FMT_BGR888_1X24, 1105 1107 MEDIA_BUS_FMT_YUV8_1X24, 1106 1108 MEDIA_BUS_FMT_YUV10_1X30, 1107 1109 }; 1108 1110 1109 1111 static const u32 mt8195_dp_intf_output_fmts[] = { 1110 - MEDIA_BUS_FMT_BGR888_1X24, 1111 1112 MEDIA_BUS_FMT_RGB888_1X24, 1112 1113 MEDIA_BUS_FMT_RGB888_2X12_LE, 1113 1114 MEDIA_BUS_FMT_RGB888_2X12_BE, 1114 1115 MEDIA_BUS_FMT_RGB101010_1X30, 1115 1116 MEDIA_BUS_FMT_YUYV8_1X16, 1116 1117 MEDIA_BUS_FMT_YUYV10_1X20, 1118 + MEDIA_BUS_FMT_BGR888_1X24, 1117 1119 MEDIA_BUS_FMT_YUV8_1X24, 1118 1120 MEDIA_BUS_FMT_YUV10_1X30, 1119 1121 };
+10 -2
drivers/gpu/drm/mediatek/mtk_plane.c
··· 285 285 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 286 286 plane); 287 287 struct mtk_plane_state *mtk_plane_state = to_mtk_plane_state(new_state); 288 + struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 289 + plane); 290 + 288 291 mtk_plane_state->pending.enable = false; 289 292 wmb(); /* Make sure the above parameter is set before update */ 290 293 mtk_plane_state->pending.dirty = true; 294 + 295 + mtk_crtc_plane_disable(old_state->crtc, plane); 291 296 } 292 297 293 298 static void mtk_plane_atomic_update(struct drm_plane *plane, ··· 326 321 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, 327 322 unsigned long possible_crtcs, enum drm_plane_type type, 328 323 unsigned int supported_rotations, const u32 blend_modes, 329 - const u32 *formats, size_t num_formats, unsigned int plane_idx) 324 + const u32 *formats, size_t num_formats, 325 + bool supports_afbc, unsigned int plane_idx) 330 326 { 331 327 int err; 332 328 ··· 338 332 339 333 err = drm_universal_plane_init(dev, plane, possible_crtcs, 340 334 &mtk_plane_funcs, formats, 341 - num_formats, modifiers, type, NULL); 335 + num_formats, 336 + supports_afbc ? modifiers : NULL, 337 + type, NULL); 342 338 if (err) { 343 339 DRM_ERROR("failed to initialize plane\n"); 344 340 return err;
+2 -1
drivers/gpu/drm/mediatek/mtk_plane.h
··· 49 49 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, 50 50 unsigned long possible_crtcs, enum drm_plane_type type, 51 51 unsigned int supported_rotations, const u32 blend_modes, 52 - const u32 *formats, size_t num_formats, unsigned int plane_idx); 52 + const u32 *formats, size_t num_formats, 53 + bool supports_afbc, unsigned int plane_idx); 53 54 #endif
+5 -6
drivers/gpu/drm/nouveau/nouveau_drm.c
··· 1284 1284 DRM_IOCTL_DEF_DRV(NOUVEAU_EXEC, nouveau_exec_ioctl_exec, DRM_RENDER_ALLOW), 1285 1285 }; 1286 1286 1287 + #define DRM_IOCTL_NOUVEAU_NVIF _IOC(_IOC_READ | _IOC_WRITE, DRM_IOCTL_BASE, \ 1288 + DRM_COMMAND_BASE + DRM_NOUVEAU_NVIF, 0) 1289 + 1287 1290 long 1288 1291 nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 1289 1292 { ··· 1300 1297 return ret; 1301 1298 } 1302 1299 1303 - switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) { 1304 - case DRM_NOUVEAU_NVIF: 1300 + if ((cmd & ~IOCSIZE_MASK) == DRM_IOCTL_NOUVEAU_NVIF) 1305 1301 ret = nouveau_abi16_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd)); 1306 - break; 1307 - default: 1302 + else 1308 1303 ret = drm_ioctl(file, cmd, arg); 1309 - break; 1310 - } 1311 1304 1312 1305 pm_runtime_mark_last_busy(dev->dev); 1313 1306 pm_runtime_put_autosuspend(dev->dev);
+1 -1
drivers/gpu/drm/panfrost/panfrost_job.c
··· 841 841 .num_rqs = DRM_SCHED_PRIORITY_COUNT, 842 842 .credit_limit = 2, 843 843 .timeout = msecs_to_jiffies(JOB_TIMEOUT_MS), 844 - .timeout_wq = pfdev->reset.wq, 845 844 .name = "pan_js", 846 845 .dev = pfdev->dev, 847 846 }; ··· 878 879 pfdev->reset.wq = alloc_ordered_workqueue("panfrost-reset", 0); 879 880 if (!pfdev->reset.wq) 880 881 return -ENOMEM; 882 + args.timeout_wq = pfdev->reset.wq; 881 883 882 884 for (j = 0; j < NUM_JOB_SLOTS; j++) { 883 885 js->queue[j].fence_context = dma_fence_context_alloc(1);
+6 -17
drivers/gpu/drm/radeon/radeon_device.c
··· 26 26 * Jerome Glisse 27 27 */ 28 28 29 - #include <linux/console.h> 30 29 #include <linux/efi.h> 31 30 #include <linux/pci.h> 32 31 #include <linux/pm_runtime.h> ··· 1634 1635 pci_set_power_state(pdev, PCI_D3hot); 1635 1636 } 1636 1637 1637 - if (notify_clients) { 1638 - console_lock(); 1639 - drm_client_dev_suspend(dev, true); 1640 - console_unlock(); 1641 - } 1638 + if (notify_clients) 1639 + drm_client_dev_suspend(dev, false); 1640 + 1642 1641 return 0; 1643 1642 } 1644 1643 ··· 1658 1661 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1659 1662 return 0; 1660 1663 1661 - if (notify_clients) { 1662 - console_lock(); 1663 - } 1664 1664 if (resume) { 1665 1665 pci_set_power_state(pdev, PCI_D0); 1666 1666 pci_restore_state(pdev); 1667 - if (pci_enable_device(pdev)) { 1668 - if (notify_clients) 1669 - console_unlock(); 1667 + if (pci_enable_device(pdev)) 1670 1668 return -1; 1671 - } 1672 1669 } 1673 1670 /* resume AGP if in use */ 1674 1671 radeon_agp_resume(rdev); ··· 1738 1747 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1739 1748 radeon_pm_compute_clocks(rdev); 1740 1749 1741 - if (notify_clients) { 1742 - drm_client_dev_resume(dev, true); 1743 - console_unlock(); 1744 - } 1750 + if (notify_clients) 1751 + drm_client_dev_resume(dev, false); 1745 1752 1746 1753 return 0; 1747 1754 }
+9 -6
drivers/gpu/drm/xe/xe_gt.c
··· 417 417 if (err) 418 418 return err; 419 419 420 + xe_mocs_init_early(gt); 421 + 420 422 return 0; 421 423 } 422 424 ··· 632 630 if (err) 633 631 return err; 634 632 635 - err = xe_gt_pagefault_init(gt); 636 - if (err) 637 - return err; 638 - 639 - xe_mocs_init_early(gt); 640 - 641 633 err = xe_gt_sysfs_init(gt); 642 634 if (err) 643 635 return err; 644 636 645 637 err = gt_fw_domain_init(gt); 638 + if (err) 639 + return err; 640 + 641 + err = xe_gt_pagefault_init(gt); 646 642 if (err) 647 643 return err; 648 644 ··· 838 838 err = -ETIMEDOUT; 839 839 goto err_out; 840 840 } 841 + 842 + if (IS_SRIOV_PF(gt_to_xe(gt))) 843 + xe_gt_sriov_pf_stop_prepare(gt); 841 844 842 845 xe_uc_gucrc_disable(&gt->uc); 843 846 xe_uc_stop_prepare(&gt->uc);
+19
drivers/gpu/drm/xe/xe_gt_sriov_pf.c
··· 172 172 pf_clear_vf_scratch_regs(gt, vfid); 173 173 } 174 174 175 + static void pf_cancel_restart(struct xe_gt *gt) 176 + { 177 + xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt))); 178 + 179 + if (cancel_work_sync(&gt->sriov.pf.workers.restart)) 180 + xe_gt_sriov_dbg_verbose(gt, "pending restart canceled!\n"); 181 + } 182 + 183 + /** 184 + * xe_gt_sriov_pf_stop_prepare() - Prepare to stop SR-IOV support. 185 + * @gt: the &xe_gt 186 + * 187 + * This function can only be called on the PF. 188 + */ 189 + void xe_gt_sriov_pf_stop_prepare(struct xe_gt *gt) 190 + { 191 + pf_cancel_restart(gt); 192 + } 193 + 175 194 static void pf_restart(struct xe_gt *gt) 176 195 { 177 196 struct xe_device *xe = gt_to_xe(gt);
+5
drivers/gpu/drm/xe/xe_gt_sriov_pf.h
··· 13 13 int xe_gt_sriov_pf_init(struct xe_gt *gt); 14 14 void xe_gt_sriov_pf_init_hw(struct xe_gt *gt); 15 15 void xe_gt_sriov_pf_sanitize_hw(struct xe_gt *gt, unsigned int vfid); 16 + void xe_gt_sriov_pf_stop_prepare(struct xe_gt *gt); 16 17 void xe_gt_sriov_pf_restart(struct xe_gt *gt); 17 18 #else 18 19 static inline int xe_gt_sriov_pf_init_early(struct xe_gt *gt) ··· 27 26 } 28 27 29 28 static inline void xe_gt_sriov_pf_init_hw(struct xe_gt *gt) 29 + { 30 + } 31 + 32 + static inline void xe_gt_sriov_pf_stop_prepare(struct xe_gt *gt) 30 33 { 31 34 } 32 35
+27
drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
··· 2364 2364 return err; 2365 2365 } 2366 2366 2367 + static int pf_push_self_config(struct xe_gt *gt) 2368 + { 2369 + int err; 2370 + 2371 + err = pf_push_full_vf_config(gt, PFID); 2372 + if (err) { 2373 + xe_gt_sriov_err(gt, "Failed to push self configuration (%pe)\n", 2374 + ERR_PTR(err)); 2375 + return err; 2376 + } 2377 + 2378 + xe_gt_sriov_dbg_verbose(gt, "self configuration completed\n"); 2379 + return 0; 2380 + } 2381 + 2367 2382 static void fini_config(void *arg) 2368 2383 { 2369 2384 struct xe_gt *gt = arg; ··· 2402 2387 int xe_gt_sriov_pf_config_init(struct xe_gt *gt) 2403 2388 { 2404 2389 struct xe_device *xe = gt_to_xe(gt); 2390 + int err; 2405 2391 2406 2392 xe_gt_assert(gt, IS_SRIOV_PF(xe)); 2393 + 2394 + mutex_lock(xe_gt_sriov_pf_master_mutex(gt)); 2395 + err = pf_push_self_config(gt); 2396 + mutex_unlock(xe_gt_sriov_pf_master_mutex(gt)); 2397 + 2398 + if (err) 2399 + return err; 2407 2400 2408 2401 return devm_add_action_or_reset(xe->drm.dev, fini_config, gt); 2409 2402 } ··· 2429 2406 { 2430 2407 unsigned int n, total_vfs = xe_sriov_pf_get_totalvfs(gt_to_xe(gt)); 2431 2408 unsigned int fail = 0, skip = 0; 2409 + 2410 + mutex_lock(xe_gt_sriov_pf_master_mutex(gt)); 2411 + pf_push_self_config(gt); 2412 + mutex_unlock(xe_gt_sriov_pf_master_mutex(gt)); 2432 2413 2433 2414 for (n = 1; n <= total_vfs; n++) { 2434 2415 if (xe_gt_sriov_pf_config_is_empty(gt, n))
+3 -3
drivers/gpu/drm/xe/xe_migrate.c
··· 1817 1817 xe_bo_assert_held(bo); 1818 1818 1819 1819 /* Use bounce buffer for small access and unaligned access */ 1820 - if (len & XE_CACHELINE_MASK || 1821 - ((uintptr_t)buf | offset) & XE_CACHELINE_MASK) { 1820 + if (!IS_ALIGNED(len, XE_CACHELINE_BYTES) || 1821 + !IS_ALIGNED((unsigned long)buf + offset, XE_CACHELINE_BYTES)) { 1822 1822 int buf_offset = 0; 1823 1823 1824 1824 /* ··· 1848 1848 err = xe_migrate_access_memory(m, bo, 1849 1849 offset & ~XE_CACHELINE_MASK, 1850 1850 (void *)ptr, 1851 - sizeof(bounce), 0); 1851 + sizeof(bounce), write); 1852 1852 if (err) 1853 1853 return err; 1854 1854 } else {
+10 -12
drivers/gpu/drm/xe/xe_ring_ops.c
··· 110 110 return i; 111 111 } 112 112 113 - static int emit_flush_invalidate(u32 *dw, int i) 113 + static int emit_flush_invalidate(u32 addr, u32 val, u32 *dw, int i) 114 114 { 115 115 dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW | 116 - MI_FLUSH_IMM_DW | MI_FLUSH_DW_STORE_INDEX; 117 - dw[i++] = LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR; 116 + MI_FLUSH_IMM_DW; 117 + 118 + dw[i++] = addr | MI_FLUSH_DW_USE_GTT; 118 119 dw[i++] = 0; 119 - dw[i++] = 0; 120 + dw[i++] = val; 120 121 121 122 return i; 122 123 } ··· 398 397 static void emit_migration_job_gen12(struct xe_sched_job *job, 399 398 struct xe_lrc *lrc, u32 seqno) 400 399 { 400 + u32 saddr = xe_lrc_start_seqno_ggtt_addr(lrc); 401 401 u32 dw[MAX_JOB_SIZE_DW], i = 0; 402 402 403 403 i = emit_copy_timestamp(lrc, dw, i); 404 404 405 - i = emit_store_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc), 406 - seqno, dw, i); 405 + i = emit_store_imm_ggtt(saddr, seqno, dw, i); 407 406 408 407 dw[i++] = MI_ARB_ON_OFF | MI_ARB_DISABLE; /* Enabled again below */ 409 408 410 409 i = emit_bb_start(job->ptrs[0].batch_addr, BIT(8), dw, i); 411 410 412 - if (!IS_SRIOV_VF(gt_to_xe(job->q->gt))) { 413 - /* XXX: Do we need this? Leaving for now. */ 414 - dw[i++] = preparser_disable(true); 415 - i = emit_flush_invalidate(dw, i); 416 - dw[i++] = preparser_disable(false); 417 - } 411 + dw[i++] = preparser_disable(true); 412 + i = emit_flush_invalidate(saddr, seqno, dw, i); 413 + dw[i++] = preparser_disable(false); 418 414 419 415 i = emit_bb_start(job->ptrs[1].batch_addr, BIT(8), dw, i); 420 416