tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Arnd Bergmann:
"Here are a couple last-minute fixes for ARM SoCs. Most of them are
for the OMAP platforms, the rest are all for different platforms.

OMAP:
All dts fixes, mostly affecting voltages and pinctrl for various
device drivers:

- Regulator minimum voltage fixes for omap5
- ISP syscon register offset fix for omap3
- Fix regulator initial modes for n900
- Fix omap5 pinctrl wkup instance size

Allwinner:
Remove incorrect constraints from a dcdc1 regulator

Alltera SoCFPGA:
Fix compilation in thumb2 mode

Samsung exynos:
Fix a potential oops in the pm-domain error handling

Davinci:
Avoid a link error if NVMEM is disabled

Renesas:
Do not mark an external uart clock as disabled, to allow probing
the uarts"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: davinci: only use NVMEM when available
ARM: SoCFPGA: Fix secondary CPU startup in thumb2 kernel
ARM: dts: omap5: fix range of permitted wakeup pinmux registers
ARM: dts: omap3-n900: Specify peripherals LDO regulators initial mode
ARM: dts: omap3: Fix ISP syscon register offset
ARM: dts: omap5-cm-t54: fix ldo1_reg and ldo4_reg ranges
ARM: dts: omap5-board-common: fix ldo1_reg and ldo4_reg ranges
arm64: dts: r8a7795: Don't disable referenced optional scif clock
ARM: EXYNOS: Properly skip unitialized parent clock in power domain on
ARM: dts: sun8i-q8-common: Do not set constraints on dc1sw regulator

Linus Torvalds c4781a8d 54176cc6

+27 -10
+9
arch/arm/boot/dts/omap3-n900.dts
··· 329 329 regulator-name = "V28"; 330 330 regulator-min-microvolt = <2800000>; 331 331 regulator-max-microvolt = <2800000>; 332 + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ 332 333 regulator-always-on; /* due to battery cover sensor */ 333 334 }; 334 335 ··· 337 336 regulator-name = "VCSI"; 338 337 regulator-min-microvolt = <1800000>; 339 338 regulator-max-microvolt = <1800000>; 339 + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ 340 340 }; 341 341 342 342 &vaux3 { 343 343 regulator-name = "VMMC2_30"; 344 344 regulator-min-microvolt = <2800000>; 345 345 regulator-max-microvolt = <3000000>; 346 + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ 346 347 }; 347 348 348 349 &vaux4 { 349 350 regulator-name = "VCAM_ANA_28"; 350 351 regulator-min-microvolt = <2800000>; 351 352 regulator-max-microvolt = <2800000>; 353 + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ 352 354 }; 353 355 354 356 &vmmc1 { 355 357 regulator-name = "VMMC1"; 356 358 regulator-min-microvolt = <1850000>; 357 359 regulator-max-microvolt = <3150000>; 360 + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ 358 361 }; 359 362 360 363 &vmmc2 { 361 364 regulator-name = "V28_A"; 362 365 regulator-min-microvolt = <2800000>; 363 366 regulator-max-microvolt = <3000000>; 367 + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ 364 368 regulator-always-on; /* due VIO leak to AIC34 VDDs */ 365 369 }; 366 370 ··· 373 367 regulator-name = "VPLL"; 374 368 regulator-min-microvolt = <1800000>; 375 369 regulator-max-microvolt = <1800000>; 370 + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ 376 371 regulator-always-on; 377 372 }; 378 373 ··· 381 374 regulator-name = "VSDI_CSI"; 382 375 regulator-min-microvolt = <1800000>; 383 376 regulator-max-microvolt = <1800000>; 377 + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ 384 378 regulator-always-on; 385 379 }; 386 380 ··· 389 381 regulator-name = "VMMC2_IO_18"; 390 382 regulator-min-microvolt = <1800000>; 391 383 regulator-max-microvolt = <1800000>; 384 + regulator-initial-mode = <0x0e>; /* RES_STATE_ACTIVE */ 392 385 }; 393 386 394 387 &vio {
+1 -1
arch/arm/boot/dts/omap34xx.dtsi
··· 46 46 0x480bd800 0x017c>; 47 47 interrupts = <24>; 48 48 iommus = <&mmu_isp>; 49 - syscon = <&scm_conf 0xdc>; 49 + syscon = <&scm_conf 0x6c>; 50 50 ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>; 51 51 #clock-cells = <1>; 52 52 ports {
+2 -2
arch/arm/boot/dts/omap5-board-common.dtsi
··· 472 472 ldo1_reg: ldo1 { 473 473 /* VDDAPHY_CAM: vdda_csiport */ 474 474 regulator-name = "ldo1"; 475 - regulator-min-microvolt = <1500000>; 475 + regulator-min-microvolt = <1800000>; 476 476 regulator-max-microvolt = <1800000>; 477 477 }; 478 478 ··· 498 498 ldo4_reg: ldo4 { 499 499 /* VDDAPHY_DISP: vdda_dsiport/hdmi */ 500 500 regulator-name = "ldo4"; 501 - regulator-min-microvolt = <1500000>; 501 + regulator-min-microvolt = <1800000>; 502 502 regulator-max-microvolt = <1800000>; 503 503 }; 504 504
+2 -2
arch/arm/boot/dts/omap5-cm-t54.dts
··· 513 513 ldo1_reg: ldo1 { 514 514 /* VDDAPHY_CAM: vdda_csiport */ 515 515 regulator-name = "ldo1"; 516 - regulator-min-microvolt = <1500000>; 516 + regulator-min-microvolt = <1800000>; 517 517 regulator-max-microvolt = <1800000>; 518 518 }; 519 519 ··· 537 537 ldo4_reg: ldo4 { 538 538 /* VDDAPHY_DISP: vdda_dsiport/hdmi */ 539 539 regulator-name = "ldo4"; 540 - regulator-min-microvolt = <1500000>; 540 + regulator-min-microvolt = <1800000>; 541 541 regulator-max-microvolt = <1800000>; 542 542 }; 543 543
+1 -1
arch/arm/boot/dts/omap5.dtsi
··· 269 269 omap5_pmx_wkup: pinmux@c840 { 270 270 compatible = "ti,omap5-padconf", 271 271 "pinctrl-single"; 272 - reg = <0xc840 0x0038>; 272 + reg = <0xc840 0x003c>; 273 273 #address-cells = <1>; 274 274 #size-cells = <0>; 275 275 #interrupt-cells = <1>;
-2
arch/arm/boot/dts/sun8i-q8-common.dtsi
··· 125 125 }; 126 126 127 127 &reg_dc1sw { 128 - regulator-min-microvolt = <3000000>; 129 - regulator-max-microvolt = <3000000>; 130 128 regulator-name = "vcc-lcd"; 131 129 }; 132 130
+5
arch/arm/mach-davinci/board-mityomapl138.c
··· 121 121 const char *partnum = NULL; 122 122 struct davinci_soc_info *soc_info = &davinci_soc_info; 123 123 124 + if (!IS_BUILTIN(CONFIG_NVMEM)) { 125 + pr_warn("Factory Config not available without CONFIG_NVMEM\n"); 126 + goto bad_config; 127 + } 128 + 124 129 ret = nvmem_device_read(nvmem, 0, sizeof(factory_config), 125 130 &factory_config); 126 131 if (ret != sizeof(struct factory_config)) {
+5
arch/arm/mach-davinci/common.c
··· 33 33 char *mac_addr = davinci_soc_info.emac_pdata->mac_addr; 34 34 off_t offset = (off_t)context; 35 35 36 + if (!IS_BUILTIN(CONFIG_NVMEM)) { 37 + pr_warn("Cannot read MAC addr from EEPROM without CONFIG_NVMEM\n"); 38 + return; 39 + } 40 + 36 41 /* Read MAC addr from EEPROM */ 37 42 if (nvmem_device_read(nvmem, offset, ETH_ALEN, mac_addr) == ETH_ALEN) 38 43 pr_info("Read MAC addr from EEPROM: %pM\n", mac_addr);
+1 -1
arch/arm/mach-exynos/pm_domains.c
··· 92 92 if (IS_ERR(pd->clk[i])) 93 93 break; 94 94 95 - if (IS_ERR(pd->clk[i])) 95 + if (IS_ERR(pd->pclk[i])) 96 96 continue; /* Skip on first power up */ 97 97 if (clk_set_parent(pd->clk[i], pd->pclk[i])) 98 98 pr_err("%s: error setting parent to clock%d\n",
+1
arch/arm/mach-socfpga/headsmp.S
··· 13 13 #include <asm/assembler.h> 14 14 15 15 .arch armv7-a 16 + .arm 16 17 17 18 ENTRY(secondary_trampoline) 18 19 /* CPU1 will always fetch from 0x0 when it is brought out of reset.
-1
arch/arm64/boot/dts/renesas/r8a7795.dtsi
··· 120 120 compatible = "fixed-clock"; 121 121 #clock-cells = <0>; 122 122 clock-frequency = <0>; 123 - status = "disabled"; 124 123 }; 125 124 126 125 soc {