tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
MIPS: Sibyte: Fix locking in set_irq_affinity
MIPS: Use force_sig when handling address errors.
MIPS: Cavium: Add struct clocksource * argument to octeon_cvmcount_read()
MIPS: Rewrite <asm/div64.h> to work with gcc 4.4.0.
MIPS: Fix highmem.
MIPS: Fix sign-extension bug in 32-bit kernel on 32-bit hardware.
MIPS: MSP71xx: Remove the RAMROOT functions
MIPS: Use -mno-check-zero-division
MIPS: Set compiler options only after the compiler prefix has ben set.
MIPS: IP27: Get rid of #ident. Gcc 4.4.0 doesn't like it.
MIPS: uaccess: Switch lock annotations to might_fault().
MIPS: MSP71xx: Resolve use of non-existent GPIO routines in msp71xx reset
MIPS: MSP71xx: Resolve multiple definition of plat_timer_setup
MIPS: Make uaccess.h slightly more sparse friendly.
MIPS: Make access_ok() sideeffect proof.
MIPS: IP27: Fix clash with NMI_OFFSET from hardirq.h
MIPS: Alchemy: Timer build fix
MIPS: Kconfig: Delete duplicate definition of RWSEM_GENERIC_SPINLOCK.
MIPS: Cavium: Add support for 8k and 32k page sizes.
MIPS: TXx9: Fix possible overflow in clock calculations
...

Linus Torvalds c48f2295 5732c468

+318 -338
+12 -8
arch/mips/Kconfig
··· 1411 1411 1412 1412 config PAGE_SIZE_8KB 1413 1413 bool "8kB" 1414 - depends on EXPERIMENTAL && CPU_R8000 1414 + depends on (EXPERIMENTAL && CPU_R8000) || CPU_CAVIUM_OCTEON 1415 1415 help 1416 1416 Using 8kB page size will result in higher performance kernel at 1417 1417 the price of higher memory consumption. This option is available 1418 - only on the R8000 processor. Not that at the time of this writing 1419 - this option is still high experimental; there are also issues with 1420 - compatibility of user applications. 1418 + only on R8000 and cnMIPS processors. Note that you will need a 1419 + suitable Linux distribution to support this. 1421 1420 1422 1421 config PAGE_SIZE_16KB 1423 1422 bool "16kB" ··· 1426 1427 the price of higher memory consumption. This option is available on 1427 1428 all non-R3000 family processors. Note that you will need a suitable 1428 1429 Linux distribution to support this. 1430 + 1431 + config PAGE_SIZE_32KB 1432 + bool "32kB" 1433 + depends on CPU_CAVIUM_OCTEON 1434 + help 1435 + Using 32kB page size will result in higher performance kernel at 1436 + the price of higher memory consumption. This option is available 1437 + only on cnMIPS cores. Note that you will need a suitable Linux 1438 + distribution to support this. 1429 1439 1430 1440 config PAGE_SIZE_64KB 1431 1441 bool "64kB" ··· 1965 1957 If unsure, say Y. Only embedded should say N here. 1966 1958 1967 1959 endmenu 1968 - 1969 - config RWSEM_GENERIC_SPINLOCK 1970 - bool 1971 - default y 1972 1960 1973 1961 config LOCKDEP_SUPPORT 1974 1962 bool
+3 -2
arch/mips/Makefile
··· 14 14 15 15 KBUILD_DEFCONFIG := ip22_defconfig 16 16 17 - cflags-y := -ffunction-sections 18 - 19 17 # 20 18 # Select the object file format to substitute into the linker script. 21 19 # ··· 47 49 CROSS_COMPILE := $(call cc-cross-prefix, $(tool-archpref)-linux- $(tool-archpref)-linux-gnu- $(tool-archpref)-unknown-linux-gnu-) 48 50 endif 49 51 endif 52 + 53 + cflags-y := -ffunction-sections 54 + cflags-y += $(call cc-option, -mno-check-zero-division) 50 55 51 56 ifdef CONFIG_32BIT 52 57 ld-emul = $(32bit-emul)
+1 -1
arch/mips/alchemy/common/time.c
··· 44 44 45 45 extern int allow_au1k_wait; /* default off for CP0 Counter */ 46 46 47 - static cycle_t au1x_counter1_read(void) 47 + static cycle_t au1x_counter1_read(struct clocksource *cs) 48 48 { 49 49 return au_readl(SYS_RTCREAD); 50 50 }
+1 -1
arch/mips/cavium-octeon/csrc-octeon.c
··· 38 38 local_irq_restore(flags); 39 39 } 40 40 41 - static cycle_t octeon_cvmcount_read(void) 41 + static cycle_t octeon_cvmcount_read(struct clocksource *cs) 42 42 { 43 43 return read_c0_cvmcount(); 44 44 }
+2 -2
arch/mips/include/asm/bitops.h
··· 567 567 int num; 568 568 569 569 if (BITS_PER_LONG == 32 && 570 - __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { 570 + __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { 571 571 __asm__( 572 572 " .set push \n" 573 573 " .set mips32 \n" ··· 644 644 { 645 645 int r; 646 646 647 - if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { 647 + if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) { 648 648 __asm__("clz %0, %1" : "=r" (x) : "r" (x)); 649 649 650 650 return 32 - x;
+2 -2
arch/mips/include/asm/checksum.h
··· 40 40 __wsum csum_partial_copy_from_user(const void __user *src, void *dst, int len, 41 41 __wsum sum, int *err_ptr) 42 42 { 43 - might_sleep(); 43 + might_fault(); 44 44 return __csum_partial_copy_user((__force void *)src, dst, 45 45 len, sum, err_ptr); 46 46 } ··· 53 53 __wsum csum_and_copy_to_user(const void *src, void __user *dst, int len, 54 54 __wsum sum, int *err_ptr) 55 55 { 56 - might_sleep(); 56 + might_fault(); 57 57 if (access_ok(VERIFY_WRITE, dst, len)) 58 58 return __csum_partial_copy_user(src, (__force void *)dst, 59 59 len, sum, err_ptr);
-1
arch/mips/include/asm/compat.h
··· 3 3 /* 4 4 * Architecture specific compatibility types 5 5 */ 6 - #include <linux/seccomp.h> 7 6 #include <linux/thread_info.h> 8 7 #include <linux/types.h> 9 8 #include <asm/page.h>
+9
arch/mips/include/asm/cpu-features.h
··· 147 147 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 148 148 cpu_has_mips64r1 | cpu_has_mips64r2) 149 149 150 + /* 151 + * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 152 + * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels 153 + * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 154 + */ 155 + # ifndef cpu_has_clo_clz 156 + # define cpu_has_clo_clz cpu_has_mips_r 157 + # endif 158 + 150 159 #ifndef cpu_has_dsp 151 160 #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 152 161 #endif
+51 -93
arch/mips/include/asm/div64.h
··· 6 6 * License. See the file "COPYING" in the main directory of this archive 7 7 * for more details. 8 8 */ 9 - #ifndef _ASM_DIV64_H 10 - #define _ASM_DIV64_H 9 + #ifndef __ASM_DIV64_H 10 + #define __ASM_DIV64_H 11 + 12 + #include <asm-generic/div64.h> 13 + 14 + #if BITS_PER_LONG == 64 11 15 12 16 #include <linux/types.h> 13 - 14 - #if (_MIPS_SZLONG == 32) 15 - 16 - #include <asm/compiler.h> 17 17 18 18 /* 19 19 * No traps on overflows for any of these... 20 20 */ 21 21 22 - #define do_div64_32(res, high, low, base) ({ \ 23 - unsigned long __quot32, __mod32; \ 24 - unsigned long __cf, __tmp, __tmp2, __i; \ 25 - \ 26 - __asm__(".set push\n\t" \ 27 - ".set noat\n\t" \ 28 - ".set noreorder\n\t" \ 29 - "move %2, $0\n\t" \ 30 - "move %3, $0\n\t" \ 31 - "b 1f\n\t" \ 32 - " li %4, 0x21\n" \ 33 - "0:\n\t" \ 34 - "sll $1, %0, 0x1\n\t" \ 35 - "srl %3, %0, 0x1f\n\t" \ 36 - "or %0, $1, %5\n\t" \ 37 - "sll %1, %1, 0x1\n\t" \ 38 - "sll %2, %2, 0x1\n" \ 39 - "1:\n\t" \ 40 - "bnez %3, 2f\n\t" \ 41 - " sltu %5, %0, %z6\n\t" \ 42 - "bnez %5, 3f\n" \ 43 - "2:\n\t" \ 44 - " addiu %4, %4, -1\n\t" \ 45 - "subu %0, %0, %z6\n\t" \ 46 - "addiu %2, %2, 1\n" \ 47 - "3:\n\t" \ 48 - "bnez %4, 0b\n\t" \ 49 - " srl %5, %1, 0x1f\n\t" \ 50 - ".set pop" \ 51 - : "=&r" (__mod32), "=&r" (__tmp), \ 52 - "=&r" (__quot32), "=&r" (__cf), \ 53 - "=&r" (__i), "=&r" (__tmp2) \ 54 - : "Jr" (base), "0" (high), "1" (low)); \ 55 - \ 56 - (res) = __quot32; \ 57 - __mod32; }) 22 + #define __div64_32(n, base) \ 23 + ({ \ 24 + unsigned long __cf, __tmp, __tmp2, __i; \ 25 + unsigned long __quot32, __mod32; \ 26 + unsigned long __high, __low; \ 27 + unsigned long long __n; \ 28 + \ 29 + __high = *__n >> 32; \ 30 + __low = __n; \ 31 + __asm__( \ 32 + " .set push \n" \ 33 + " .set noat \n" \ 34 + " .set noreorder \n" \ 35 + " move %2, $0 \n" \ 36 + " move %3, $0 \n" \ 37 + " b 1f \n" \ 38 + " li %4, 0x21 \n" \ 39 + "0: \n" \ 40 + " sll $1, %0, 0x1 \n" \ 41 + " srl %3, %0, 0x1f \n" \ 42 + " or %0, $1, %5 \n" \ 43 + " sll %1, %1, 0x1 \n" \ 44 + " sll %2, %2, 0x1 \n" \ 45 + "1: \n" \ 46 + " bnez %3, 2f \n" \ 47 + " sltu %5, %0, %z6 \n" \ 48 + " bnez %5, 3f \n" \ 49 + "2: \n" \ 50 + " addiu %4, %4, -1 \n" \ 51 + " subu %0, %0, %z6 \n" \ 52 + " addiu %2, %2, 1 \n" \ 53 + "3: \n" \ 54 + " bnez %4, 0b\n\t" \ 55 + " srl %5, %1, 0x1f\n\t" \ 56 + " .set pop" \ 57 + : "=&r" (__mod32), "=&r" (__tmp), \ 58 + "=&r" (__quot32), "=&r" (__cf), \ 59 + "=&r" (__i), "=&r" (__tmp2) \ 60 + : "Jr" (base), "0" (__high), "1" (__low)); \ 61 + \ 62 + (__n) = __quot32; \ 63 + __mod32; \ 64 + }) 58 65 59 - #define do_div(n, base) ({ \ 60 - unsigned long long __quot; \ 61 - unsigned long __mod; \ 62 - unsigned long long __div; \ 63 - unsigned long __upper, __low, __high, __base; \ 64 - \ 65 - __div = (n); \ 66 - __base = (base); \ 67 - \ 68 - __high = __div >> 32; \ 69 - __low = __div; \ 70 - __upper = __high; \ 71 - \ 72 - if (__high) \ 73 - __asm__("divu $0, %z2, %z3" \ 74 - : "=h" (__upper), "=l" (__high) \ 75 - : "Jr" (__high), "Jr" (__base) \ 76 - : GCC_REG_ACCUM); \ 77 - \ 78 - __mod = do_div64_32(__low, __upper, __low, __base); \ 79 - \ 80 - __quot = __high; \ 81 - __quot = __quot << 32 | __low; \ 82 - (n) = __quot; \ 83 - __mod; }) 66 + #endif /* BITS_PER_LONG == 64 */ 84 67 85 - #endif /* (_MIPS_SZLONG == 32) */ 86 - 87 - #if (_MIPS_SZLONG == 64) 88 - 89 - /* 90 - * Hey, we're already 64-bit, no 91 - * need to play games.. 92 - */ 93 - #define do_div(n, base) ({ \ 94 - unsigned long __quot; \ 95 - unsigned int __mod; \ 96 - unsigned long __div; \ 97 - unsigned int __base; \ 98 - \ 99 - __div = (n); \ 100 - __base = (base); \ 101 - \ 102 - __mod = __div % __base; \ 103 - __quot = __div / __base; \ 104 - \ 105 - (n) = __quot; \ 106 - __mod; }) 107 - 108 - #endif /* (_MIPS_SZLONG == 64) */ 109 - 110 - #endif /* _ASM_DIV64_H */ 68 + #endif /* __ASM_DIV64_H */
+7 -2
arch/mips/include/asm/dma-mapping.h
··· 24 24 enum dma_data_direction direction); 25 25 extern dma_addr_t dma_map_page(struct device *dev, struct page *page, 26 26 unsigned long offset, size_t size, enum dma_data_direction direction); 27 - extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address, 28 - size_t size, enum dma_data_direction direction); 27 + 28 + static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, 29 + size_t size, enum dma_data_direction direction) 30 + { 31 + dma_unmap_single(dev, dma_address, size, direction); 32 + } 33 + 29 34 extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, 30 35 int nhwentries, enum dma_data_direction direction); 31 36 extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
+3
arch/mips/include/asm/fixmap.h
··· 108 108 return __virt_to_fix(vaddr); 109 109 } 110 110 111 + #define kmap_get_fixmap_pte(vaddr) \ 112 + pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) 113 + 111 114 /* 112 115 * Called from pgtable_init() 113 116 */
+3 -2
arch/mips/include/asm/hazards.h
··· 138 138 __instruction_hazard(); \ 139 139 } while (0) 140 140 141 - #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ 142 - defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY) 141 + #elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ 142 + defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ 143 + defined(CONFIG_CPU_R5500) 143 144 144 145 /* 145 146 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
+4 -2
arch/mips/include/asm/highmem.h
··· 30 30 /* declarations for highmem.c */ 31 31 extern unsigned long highstart_pfn, highend_pfn; 32 32 33 - extern pte_t *kmap_pte; 34 - extern pgprot_t kmap_prot; 35 33 extern pte_t *pkmap_page_table; 36 34 37 35 /* ··· 59 61 #define kmap_atomic_to_page __kmap_atomic_to_page 60 62 61 63 #define flush_cache_kmaps() flush_cache_all() 64 + 65 + extern void kmap_init(void); 66 + 67 + #define kmap_prot PAGE_KERNEL 62 68 63 69 #endif /* __KERNEL__ */ 64 70
+3 -3
arch/mips/include/asm/mach-au1x00/au1000.h
··· 715 715 #ifdef CONFIG_SOC_AU1100 716 716 enum soc_au1100_ints { 717 717 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 718 - AU1100_UART0_INT, 718 + AU1100_UART0_INT = AU1100_FIRST_INT, 719 719 AU1100_UART1_INT, 720 720 AU1100_SD_INT, 721 721 AU1100_UART3_INT, ··· 902 902 AU1000_RTC_MATCH0_INT, 903 903 AU1000_RTC_MATCH1_INT, 904 904 AU1000_RTC_MATCH2_INT, 905 - 906 - AU1200_NAND_INT = AU1200_FIRST_INT + 23, 905 + AU1200_GPIO_203, 906 + AU1200_NAND_INT, 907 907 AU1200_GPIO_204, 908 908 AU1200_GPIO_205, 909 909 AU1200_GPIO_206,
-17
arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
··· 46 46 #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0 47 47 #endif 48 48 49 - #ifdef CONFIG_PM 50 - /* 51 - * This will enable the device to be powered up when write() or read() 52 - * is called. If this is not defined, the driver will return -EBUSY. 53 - */ 54 - #define WAKE_ON_ACCESS 1 55 - 56 - typedef struct { 57 - spinlock_t lock; /* Used to block on state transitions */ 58 - au1xxx_power_dev_t *dev; /* Power Managers device structure */ 59 - unsigned stopped; /* Used to signal device is stopped */ 60 - } pm_state; 61 - #endif 62 - 63 49 typedef struct { 64 50 u32 tx_dev_id, rx_dev_id, target_dev_id; 65 51 u32 tx_chan, rx_chan; ··· 58 72 #endif 59 73 int irq; 60 74 u32 regbase; 61 - #ifdef CONFIG_PM 62 - pm_state pm; 63 - #endif 64 75 } _auide_hwif; 65 76 66 77 /******************************************************************************/
+59
arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h
··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2009 Wu Zhangjin <wuzj@lemote.com> 7 + * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca> 8 + * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org> 9 + * 10 + * reference: /proc/cpuinfo, 11 + * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy), 12 + * arch/mips/kernel/proc.c(show_cpuinfo), 13 + * loongson2f user manual. 14 + */ 15 + 16 + #ifndef __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H 17 + #define __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H 18 + 19 + #define cpu_dcache_line_size() 32 20 + #define cpu_icache_line_size() 32 21 + #define cpu_scache_line_size() 32 22 + 23 + 24 + #define cpu_has_32fpr 1 25 + #define cpu_has_3k_cache 0 26 + #define cpu_has_4k_cache 1 27 + #define cpu_has_4kex 1 28 + #define cpu_has_64bits 1 29 + #define cpu_has_cache_cdex_p 0 30 + #define cpu_has_cache_cdex_s 0 31 + #define cpu_has_counter 1 32 + #define cpu_has_dc_aliases 1 33 + #define cpu_has_divec 0 34 + #define cpu_has_dsp 0 35 + #define cpu_has_ejtag 0 36 + #define cpu_has_fpu 1 37 + #define cpu_has_ic_fills_f_dc 0 38 + #define cpu_has_inclusive_pcaches 1 39 + #define cpu_has_llsc 1 40 + #define cpu_has_mcheck 0 41 + #define cpu_has_mdmx 0 42 + #define cpu_has_mips16 0 43 + #define cpu_has_mips32r1 0 44 + #define cpu_has_mips32r2 0 45 + #define cpu_has_mips3d 0 46 + #define cpu_has_mips64r1 0 47 + #define cpu_has_mips64r2 0 48 + #define cpu_has_mipsmt 0 49 + #define cpu_has_prefetch 0 50 + #define cpu_has_smartmips 0 51 + #define cpu_has_tlb 1 52 + #define cpu_has_tx39_cache 0 53 + #define cpu_has_userlocal 0 54 + #define cpu_has_vce 0 55 + #define cpu_has_vtag_icache 0 56 + #define cpu_has_watch 1 57 + #define cpu_icache_snoops_remote_store 1 58 + 59 + #endif /* __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H */
+26 -12
arch/mips/include/asm/mipsregs.h
··· 184 184 #else 185 185 186 186 #define PM_4K 0x00000000 187 + #define PM_8K 0x00002000 187 188 #define PM_16K 0x00006000 189 + #define PM_32K 0x0000e000 188 190 #define PM_64K 0x0001e000 191 + #define PM_128K 0x0003e000 189 192 #define PM_256K 0x0007e000 193 + #define PM_512K 0x000fe000 190 194 #define PM_1M 0x001fe000 195 + #define PM_2M 0x003fe000 191 196 #define PM_4M 0x007fe000 197 + #define PM_8M 0x00ffe000 192 198 #define PM_16M 0x01ffe000 199 + #define PM_32M 0x03ffe000 193 200 #define PM_64M 0x07ffe000 194 201 #define PM_256M 0x1fffe000 195 202 #define PM_1G 0x7fffe000 ··· 208 201 */ 209 202 #ifdef CONFIG_PAGE_SIZE_4KB 210 203 #define PM_DEFAULT_MASK PM_4K 204 + #elif defined(CONFIG_PAGE_SIZE_8KB) 205 + #define PM_DEFAULT_MASK PM_8K 211 206 #elif defined(CONFIG_PAGE_SIZE_16KB) 212 207 #define PM_DEFAULT_MASK PM_16K 208 + #elif defined(CONFIG_PAGE_SIZE_32KB) 209 + #define PM_DEFAULT_MASK PM_32K 213 210 #elif defined(CONFIG_PAGE_SIZE_64KB) 214 211 #define PM_DEFAULT_MASK PM_64K 215 212 #else ··· 728 717 ".set\tmips64\n\t" \ 729 718 "dmfc0\t%M0, " #source "\n\t" \ 730 719 "dsll\t%L0, %M0, 32\n\t" \ 731 - "dsrl\t%M0, %M0, 32\n\t" \ 732 - "dsrl\t%L0, %L0, 32\n\t" \ 720 + "dsra\t%M0, %M0, 32\n\t" \ 721 + "dsra\t%L0, %L0, 32\n\t" \ 733 722 ".set\tmips0" \ 734 723 : "=r" (__val)); \ 735 724 else \ ··· 737 726 ".set\tmips64\n\t" \ 738 727 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 739 728 "dsll\t%L0, %M0, 32\n\t" \ 740 - "dsrl\t%M0, %M0, 32\n\t" \ 741 - "dsrl\t%L0, %L0, 32\n\t" \ 729 + "dsra\t%M0, %M0, 32\n\t" \ 730 + "dsra\t%L0, %L0, 32\n\t" \ 742 731 ".set\tmips0" \ 743 732 : "=r" (__val)); \ 744 733 local_irq_restore(__flags); \ ··· 1495 1484 set_c0_##name(unsigned int set) \ 1496 1485 { \ 1497 1486 unsigned int res; \ 1487 + unsigned int new; \ 1498 1488 unsigned int omt; \ 1499 1489 unsigned long flags; \ 1500 1490 \ 1501 1491 local_irq_save(flags); \ 1502 1492 omt = __dmt(); \ 1503 1493 res = read_c0_##name(); \ 1504 - res |= set; \ 1505 - write_c0_##name(res); \ 1494 + new = res | set; \ 1495 + write_c0_##name(new); \ 1506 1496 __emt(omt); \ 1507 1497 local_irq_restore(flags); \ 1508 1498 \ ··· 1514 1502 clear_c0_##name(unsigned int clear) \ 1515 1503 { \ 1516 1504 unsigned int res; \ 1505 + unsigned int new; \ 1517 1506 unsigned int omt; \ 1518 1507 unsigned long flags; \ 1519 1508 \ 1520 1509 local_irq_save(flags); \ 1521 1510 omt = __dmt(); \ 1522 1511 res = read_c0_##name(); \ 1523 - res &= ~clear; \ 1524 - write_c0_##name(res); \ 1512 + new = res & ~clear; \ 1513 + write_c0_##name(new); \ 1525 1514 __emt(omt); \ 1526 1515 local_irq_restore(flags); \ 1527 1516 \ ··· 1530 1517 } \ 1531 1518 \ 1532 1519 static inline unsigned int \ 1533 - change_c0_##name(unsigned int change, unsigned int new) \ 1520 + change_c0_##name(unsigned int change, unsigned int newbits) \ 1534 1521 { \ 1535 1522 unsigned int res; \ 1523 + unsigned int new; \ 1536 1524 unsigned int omt; \ 1537 1525 unsigned long flags; \ 1538 1526 \ ··· 1541 1527 \ 1542 1528 omt = __dmt(); \ 1543 1529 res = read_c0_##name(); \ 1544 - res &= ~change; \ 1545 - res |= (new & change); \ 1546 - write_c0_##name(res); \ 1530 + new = res & ~change; \ 1531 + new |= (newbits & change); \ 1532 + write_c0_##name(new); \ 1547 1533 __emt(omt); \ 1548 1534 local_irq_restore(flags); \ 1549 1535 \
+3
arch/mips/include/asm/page.h
··· 23 23 #ifdef CONFIG_PAGE_SIZE_16KB 24 24 #define PAGE_SHIFT 14 25 25 #endif 26 + #ifdef CONFIG_PAGE_SIZE_32KB 27 + #define PAGE_SHIFT 15 28 + #endif 26 29 #ifdef CONFIG_PAGE_SIZE_64KB 27 30 #define PAGE_SHIFT 16 28 31 #endif
+6
arch/mips/include/asm/pgtable-64.h
··· 83 83 #define PMD_ORDER 0 84 84 #define PTE_ORDER 0 85 85 #endif 86 + #ifdef CONFIG_PAGE_SIZE_32KB 87 + #define PGD_ORDER 0 88 + #define PUD_ORDER aieeee_attempt_to_allocate_pud 89 + #define PMD_ORDER 0 90 + #define PTE_ORDER 0 91 + #endif 86 92 #ifdef CONFIG_PAGE_SIZE_64KB 87 93 #define PGD_ORDER 0 88 94 #define PUD_ORDER aieeee_attempt_to_allocate_pud
+2 -2
arch/mips/include/asm/sn/addrs.h
··· 359 359 TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice)) 360 360 #define LAUNCH_SIZE(nasid) KLD_LAUNCH(nasid)->size 361 361 362 - #define NMI_OFFSET(nasid, slice) \ 362 + #define SN_NMI_OFFSET(nasid, slice) \ 363 363 (KLD_NMI(nasid)->offset + \ 364 364 KLD_NMI(nasid)->stride * (slice)) 365 365 #define NMI_ADDR(nasid, slice) \ 366 - TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice)) 366 + TO_NODE_UNCAC((nasid), SN_NMI_OFFSET(nasid, slice)) 367 367 #define NMI_SIZE(nasid) KLD_NMI(nasid)->size 368 368 369 369 #define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset
+2 -2
arch/mips/include/asm/sn/nmi.h
··· 3 3 * License. See the file "COPYING" in the main directory of this archive 4 4 * for more details. 5 5 * 6 + * Derived from IRIX <sys/SN/nmi.h>, Revision 1.5. 7 + * 6 8 * Copyright (C) 1992 - 1997 Silicon Graphics, Inc. 7 9 */ 8 10 #ifndef __ASM_SN_NMI_H 9 11 #define __ASM_SN_NMI_H 10 - 11 - #ident "$Revision: 1.5 $" 12 12 13 13 #include <asm/sn/addrs.h> 14 14
+3
arch/mips/include/asm/thread_info.h
··· 75 75 #ifdef CONFIG_PAGE_SIZE_16KB 76 76 #define THREAD_SIZE_ORDER (0) 77 77 #endif 78 + #ifdef CONFIG_PAGE_SIZE_32KB 79 + #define THREAD_SIZE_ORDER (0) 80 + #endif 78 81 #ifdef CONFIG_PAGE_SIZE_64KB 79 82 #define THREAD_SIZE_ORDER (0) 80 83 #endif
+5 -1
arch/mips/include/asm/time.h
··· 57 57 58 58 static inline int mips_clockevent_init(void) 59 59 { 60 - #ifdef CONFIG_CEVT_R4K 60 + #ifdef CONFIG_MIPS_MT_SMTC 61 + extern int smtc_clockevent_init(void); 62 + 63 + return smtc_clockevent_init(); 64 + #elif defined(CONFIG_CEVT_R4K) 61 65 return r4k_clockevent_init(); 62 66 #else 63 67 return -ENXIO;
+48 -18
arch/mips/include/asm/uaccess.h
··· 105 105 #define __access_mask get_fs().seg 106 106 107 107 #define __access_ok(addr, size, mask) \ 108 - (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) 108 + ({ \ 109 + unsigned long __addr = (unsigned long) (addr); \ 110 + unsigned long __size = size; \ 111 + unsigned long __mask = mask; \ 112 + unsigned long __ok; \ 113 + \ 114 + __chk_user_ptr(addr); \ 115 + __ok = (signed long)(__mask & (__addr | (__addr + __size) | \ 116 + __ua_size(__size))); \ 117 + __ok == 0; \ 118 + }) 109 119 110 120 #define access_ok(type, addr, size) \ 111 - likely(__access_ok((unsigned long)(addr), (size), __access_mask)) 121 + likely(__access_ok((addr), (size), __access_mask)) 112 122 113 123 /* 114 124 * put_user: - Write a simple value into user space. ··· 235 225 ({ \ 236 226 int __gu_err; \ 237 227 \ 228 + __chk_user_ptr(ptr); \ 238 229 __get_user_common((x), size, ptr); \ 239 230 __gu_err; \ 240 231 }) ··· 245 234 int __gu_err = -EFAULT; \ 246 235 const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \ 247 236 \ 237 + might_fault(); \ 248 238 if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \ 249 239 __get_user_common((x), size, __gu_ptr); \ 250 240 \ ··· 317 305 __typeof__(*(ptr)) __pu_val; \ 318 306 int __pu_err = 0; \ 319 307 \ 308 + __chk_user_ptr(ptr); \ 320 309 __pu_val = (x); \ 321 310 switch (size) { \ 322 311 case 1: __put_user_asm("sb", ptr); break; \ ··· 335 322 __typeof__(*(ptr)) __pu_val = (x); \ 336 323 int __pu_err = -EFAULT; \ 337 324 \ 325 + might_fault(); \ 338 326 if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \ 339 327 switch (size) { \ 340 328 case 1: __put_user_asm("sb", __pu_addr); break; \ ··· 710 696 const void *__cu_from; \ 711 697 long __cu_len; \ 712 698 \ 713 - might_sleep(); \ 714 699 __cu_to = (to); \ 715 700 __cu_from = (from); \ 716 701 __cu_len = (n); \ 702 + might_fault(); \ 717 703 __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \ 718 704 __cu_len; \ 719 705 }) ··· 766 752 const void *__cu_from; \ 767 753 long __cu_len; \ 768 754 \ 769 - might_sleep(); \ 770 755 __cu_to = (to); \ 771 756 __cu_from = (from); \ 772 757 __cu_len = (n); \ 773 - if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) \ 758 + if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) { \ 759 + might_fault(); \ 774 760 __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, \ 775 761 __cu_len); \ 762 + } \ 776 763 __cu_len; \ 777 764 }) 778 765 ··· 846 831 const void __user *__cu_from; \ 847 832 long __cu_len; \ 848 833 \ 849 - might_sleep(); \ 850 834 __cu_to = (to); \ 851 835 __cu_from = (from); \ 852 836 __cu_len = (n); \ 837 + might_fault(); \ 853 838 __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ 854 839 __cu_len); \ 855 840 __cu_len; \ ··· 877 862 const void __user *__cu_from; \ 878 863 long __cu_len; \ 879 864 \ 880 - might_sleep(); \ 881 865 __cu_to = (to); \ 882 866 __cu_from = (from); \ 883 867 __cu_len = (n); \ 884 - if (access_ok(VERIFY_READ, __cu_from, __cu_len)) \ 868 + if (access_ok(VERIFY_READ, __cu_from, __cu_len)) { \ 869 + might_fault(); \ 885 870 __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ 886 871 __cu_len); \ 872 + } \ 887 873 __cu_len; \ 888 874 }) 889 875 890 - #define __copy_in_user(to, from, n) __copy_from_user(to, from, n) 876 + #define __copy_in_user(to, from, n) \ 877 + ({ \ 878 + void __user *__cu_to; \ 879 + const void __user *__cu_from; \ 880 + long __cu_len; \ 881 + \ 882 + __cu_to = (to); \ 883 + __cu_from = (from); \ 884 + __cu_len = (n); \ 885 + might_fault(); \ 886 + __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ 887 + __cu_len); \ 888 + __cu_len; \ 889 + }) 891 890 892 891 #define copy_in_user(to, from, n) \ 893 892 ({ \ ··· 909 880 const void __user *__cu_from; \ 910 881 long __cu_len; \ 911 882 \ 912 - might_sleep(); \ 913 883 __cu_to = (to); \ 914 884 __cu_from = (from); \ 915 885 __cu_len = (n); \ 916 886 if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) && \ 917 - access_ok(VERIFY_WRITE, __cu_to, __cu_len))) \ 887 + access_ok(VERIFY_WRITE, __cu_to, __cu_len))) { \ 888 + might_fault(); \ 918 889 __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ 919 890 __cu_len); \ 891 + } \ 920 892 __cu_len; \ 921 893 }) 922 894 ··· 937 907 { 938 908 __kernel_size_t res; 939 909 940 - might_sleep(); 910 + might_fault(); 941 911 __asm__ __volatile__( 942 912 "move\t$4, %1\n\t" 943 913 "move\t$5, $0\n\t" ··· 986 956 { 987 957 long res; 988 958 989 - might_sleep(); 959 + might_fault(); 990 960 __asm__ __volatile__( 991 961 "move\t$4, %1\n\t" 992 962 "move\t$5, %2\n\t" ··· 1023 993 { 1024 994 long res; 1025 995 1026 - might_sleep(); 996 + might_fault(); 1027 997 __asm__ __volatile__( 1028 998 "move\t$4, %1\n\t" 1029 999 "move\t$5, %2\n\t" ··· 1042 1012 { 1043 1013 long res; 1044 1014 1045 - might_sleep(); 1015 + might_fault(); 1046 1016 __asm__ __volatile__( 1047 1017 "move\t$4, %1\n\t" 1048 1018 __MODULE_JAL(__strlen_user_nocheck_asm) ··· 1072 1042 { 1073 1043 long res; 1074 1044 1075 - might_sleep(); 1045 + might_fault(); 1076 1046 __asm__ __volatile__( 1077 1047 "move\t$4, %1\n\t" 1078 1048 __MODULE_JAL(__strlen_user_asm) ··· 1089 1059 { 1090 1060 long res; 1091 1061 1092 - might_sleep(); 1062 + might_fault(); 1093 1063 __asm__ __volatile__( 1094 1064 "move\t$4, %1\n\t" 1095 1065 "move\t$5, %2\n\t" ··· 1120 1090 { 1121 1091 long res; 1122 1092 1123 - might_sleep(); 1093 + might_fault(); 1124 1094 __asm__ __volatile__( 1125 1095 "move\t$4, %1\n\t" 1126 1096 "move\t$5, %2\n\t"
+1 -1
arch/mips/kernel/cevt-smtc.c
··· 245 245 } 246 246 247 247 248 - int __cpuinit mips_clockevent_init(void) 248 + int __cpuinit smtc_clockevent_init(void) 249 249 { 250 250 uint64_t mips_freq = mips_hpt_frequency; 251 251 unsigned int cpu = smp_processor_id();
+2 -2
arch/mips/kernel/scall64-n32.S
··· 405 405 PTR sys_eventfd 406 406 PTR sys_fallocate 407 407 PTR sys_timerfd_create 408 - PTR sys_timerfd_gettime /* 5285 */ 409 - PTR sys_timerfd_settime 408 + PTR compat_sys_timerfd_gettime /* 5285 */ 409 + PTR compat_sys_timerfd_settime 410 410 PTR sys_signalfd4 411 411 PTR sys_eventfd2 412 412 PTR sys_epoll_create1
+2 -2
arch/mips/kernel/scall64-o32.S
··· 525 525 PTR sys_eventfd 526 526 PTR sys32_fallocate /* 4320 */ 527 527 PTR sys_timerfd_create 528 - PTR sys_timerfd_gettime 529 - PTR sys_timerfd_settime 528 + PTR compat_sys_timerfd_gettime 529 + PTR compat_sys_timerfd_settime 530 530 PTR compat_sys_signalfd4 531 531 PTR sys_eventfd2 /* 4325 */ 532 532 PTR sys_epoll_create1
+3 -3
arch/mips/kernel/unaligned.c
··· 482 482 return; 483 483 484 484 die_if_kernel("Unhandled kernel unaligned access", regs); 485 - send_sig(SIGSEGV, current, 1); 485 + force_sig(SIGSEGV, current); 486 486 487 487 return; 488 488 489 489 sigbus: 490 490 die_if_kernel("Unhandled kernel unaligned access", regs); 491 - send_sig(SIGBUS, current, 1); 491 + force_sig(SIGBUS, current); 492 492 493 493 return; 494 494 495 495 sigill: 496 496 die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); 497 - send_sig(SIGILL, current, 1); 497 + force_sig(SIGILL, current); 498 498 } 499 499 500 500 asmlinkage void do_ade(struct pt_regs *regs)
+9
arch/mips/lib/dump_tlb.c
··· 19 19 case PM_16K: return "16kb"; 20 20 case PM_64K: return "64kb"; 21 21 case PM_256K: return "256kb"; 22 + #ifdef CONFIG_CPU_CAVIUM_OCTEON 23 + case PM_8K: return "8kb"; 24 + case PM_32K: return "32kb"; 25 + case PM_128K: return "128kb"; 26 + case PM_512K: return "512kb"; 27 + case PM_2M: return "2Mb"; 28 + case PM_8M: return "8Mb"; 29 + case PM_32M: return "32Mb"; 30 + #endif 22 31 #ifndef CONFIG_CPU_VR41XX 23 32 case PM_1M: return "1Mb"; 24 33 case PM_4M: return "4Mb";
+1 -1
arch/mips/mm/c-r4k.c
··· 1041 1041 1042 1042 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", 1043 1043 icache_size >> 10, 1044 - cpu_has_vtag_icache ? "VIVT" : "VIPT", 1044 + c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", 1045 1045 way_string[c->icache.ways], c->icache.linesz); 1046 1046 1047 1047 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
+1 -18
arch/mips/mm/dma-default.c
··· 209 209 unsigned long addr; 210 210 211 211 addr = (unsigned long) page_address(page) + offset; 212 - dma_cache_wback_inv(addr, size); 212 + __dma_sync(addr, size, direction); 213 213 } 214 214 215 215 return plat_map_dma_mem_page(dev, page) + offset; 216 216 } 217 217 218 218 EXPORT_SYMBOL(dma_map_page); 219 - 220 - void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, 221 - enum dma_data_direction direction) 222 - { 223 - BUG_ON(direction == DMA_NONE); 224 - 225 - if (!plat_device_is_coherent(dev) && direction != DMA_TO_DEVICE) { 226 - unsigned long addr; 227 - 228 - addr = dma_addr_to_virt(dma_address); 229 - dma_cache_wback_inv(addr, size); 230 - } 231 - 232 - plat_unmap_dma_mem(dev, dma_address); 233 - } 234 - 235 - EXPORT_SYMBOL(dma_unmap_page); 236 219 237 220 void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, 238 221 enum dma_data_direction direction)
+19 -6
arch/mips/mm/highmem.c
··· 1 1 #include <linux/module.h> 2 2 #include <linux/highmem.h> 3 + #include <asm/fixmap.h> 3 4 #include <asm/tlbflush.h> 5 + 6 + static pte_t *kmap_pte; 7 + 8 + unsigned long highstart_pfn, highend_pfn; 4 9 5 10 void *__kmap(struct page *page) 6 11 { ··· 19 14 20 15 return addr; 21 16 } 17 + EXPORT_SYMBOL(__kmap); 22 18 23 19 void __kunmap(struct page *page) 24 20 { ··· 28 22 return; 29 23 kunmap_high(page); 30 24 } 25 + EXPORT_SYMBOL(__kunmap); 31 26 32 27 /* 33 28 * kmap_atomic/kunmap_atomic is significantly faster than kmap/kunmap because ··· 55 48 #ifdef CONFIG_DEBUG_HIGHMEM 56 49 BUG_ON(!pte_none(*(kmap_pte - idx))); 57 50 #endif 58 - set_pte(kmap_pte-idx, mk_pte(page, kmap_prot)); 51 + set_pte(kmap_pte-idx, mk_pte(page, PAGE_KERNEL)); 59 52 local_flush_tlb_one((unsigned long)vaddr); 60 53 61 54 return (void*) vaddr; 62 55 } 56 + EXPORT_SYMBOL(__kmap_atomic); 63 57 64 58 void __kunmap_atomic(void *kvaddr, enum km_type type) 65 59 { ··· 85 77 86 78 pagefault_enable(); 87 79 } 80 + EXPORT_SYMBOL(__kunmap_atomic); 88 81 89 82 /* 90 83 * This is the same as kmap_atomic() but can map memory that doesn't ··· 101 92 debug_kmap_atomic(type); 102 93 idx = type + KM_TYPE_NR*smp_processor_id(); 103 94 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); 104 - set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot)); 95 + set_pte(kmap_pte-idx, pfn_pte(pfn, PAGE_KERNEL)); 105 96 flush_tlb_one(vaddr); 106 97 107 98 return (void*) vaddr; ··· 120 111 return pte_page(*pte); 121 112 } 122 113 123 - EXPORT_SYMBOL(__kmap); 124 - EXPORT_SYMBOL(__kunmap); 125 - EXPORT_SYMBOL(__kmap_atomic); 126 - EXPORT_SYMBOL(__kunmap_atomic); 114 + void __init kmap_init(void) 115 + { 116 + unsigned long kmap_vstart; 117 + 118 + /* cache the first kmap pte */ 119 + kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN); 120 + kmap_pte = kmap_get_fixmap_pte(kmap_vstart); 121 + }
-26
arch/mips/mm/init.c
··· 104 104 return 1UL << order; 105 105 } 106 106 107 - /* 108 - * These are almost like kmap_atomic / kunmap_atmic except they take an 109 - * additional address argument as the hint. 110 - */ 111 - 112 - #define kmap_get_fixmap_pte(vaddr) \ 113 - pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) 114 - 115 107 #ifdef CONFIG_MIPS_MT_SMTC 116 108 static pte_t *kmap_coherent_pte; 117 109 static void __init kmap_coherent_init(void) ··· 255 263 SetPageDcacheDirty(page); 256 264 } 257 265 } 258 - 259 - #ifdef CONFIG_HIGHMEM 260 - unsigned long highstart_pfn, highend_pfn; 261 - 262 - pte_t *kmap_pte; 263 - pgprot_t kmap_prot; 264 - 265 - static void __init kmap_init(void) 266 - { 267 - unsigned long kmap_vstart; 268 - 269 - /* cache the first kmap pte */ 270 - kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN); 271 - kmap_pte = kmap_get_fixmap_pte(kmap_vstart); 272 - 273 - kmap_prot = PAGE_KERNEL; 274 - } 275 - #endif /* CONFIG_HIGHMEM */ 276 266 277 267 void __init fixrange_init(unsigned long start, unsigned long end, 278 268 pgd_t *pgd_base)
+2 -2
arch/mips/mm/sc-rm7k.c
··· 29 29 30 30 #include <asm/r4kcache.h> 31 31 32 - int rm7k_tcache_enabled; 32 + static int rm7k_tcache_enabled; 33 33 34 34 /* 35 35 * Writeback and invalidate the primary cache dcache before DMA. ··· 121 121 clear_c0_config(RM7K_CONF_SE); 122 122 } 123 123 124 - struct bcache_ops rm7k_sc_ops = { 124 + static struct bcache_ops rm7k_sc_ops = { 125 125 .bc_enable = rm7k_sc_enable, 126 126 .bc_disable = rm7k_sc_disable, 127 127 .bc_wback_inv = rm7k_sc_wback_inv,
-12
arch/mips/pmc-sierra/Kconfig
··· 36 36 37 37 endchoice 38 38 39 - menu "Options for PMC-Sierra MSP chipsets" 40 - depends on PMC_MSP 41 - 42 - config PMC_MSP_EMBEDDED_ROOTFS 43 - bool "Root filesystem embedded in kernel image" 44 - select MTD 45 - select MTD_BLOCK 46 - select MTD_PMC_MSP_RAMROOT 47 - select MTD_RAM 48 - 49 - endmenu 50 - 51 39 config HYPERTRANSPORT 52 40 bool "Hypertransport Support for PMC-Sierra Yosemite" 53 41 depends on PMC_YOSEMITE
+1 -59
arch/mips/pmc-sierra/msp71xx/msp_prom.c
··· 40 40 #include <linux/string.h> 41 41 #include <linux/interrupt.h> 42 42 #include <linux/mm.h> 43 - #ifdef CONFIG_CRAMFS 44 - #include <linux/cramfs_fs.h> 45 - #endif 46 - #ifdef CONFIG_SQUASHFS 47 - #include <linux/squashfs_fs.h> 48 - #endif 49 43 50 44 #include <asm/addrspace.h> 51 45 #include <asm/bootinfo.h> ··· 429 435 char *str; 430 436 unsigned int memsize; 431 437 unsigned int heaptop; 432 - #ifdef CONFIG_MTD_PMC_MSP_RAMROOT 433 - void *ramroot_start; 434 - unsigned long ramroot_size; 435 - #endif 436 438 int i; 437 439 438 440 str = prom_getenv(memsz_env); ··· 496 506 i++; /* 3 */ 497 507 mdesc[i].type = BOOT_MEM_RESERVED; 498 508 mdesc[i].base = CPHYSADDR((u32)_text); 499 - #ifdef CONFIG_MTD_PMC_MSP_RAMROOT 500 - if (get_ramroot(&ramroot_start, &ramroot_size)) { 501 - /* 502 - * Rootfs in RAM -- follows kernel 503 - * Combine rootfs image with kernel block so a 504 - * page (4k) isn't wasted between memory blocks 505 - */ 506 - mdesc[i].size = CPHYSADDR(PAGE_ALIGN( 507 - (u32)ramroot_start + ramroot_size)) - mdesc[i].base; 508 - } else 509 - #endif 510 - mdesc[i].size = CPHYSADDR(PAGE_ALIGN( 511 - (u32)_end)) - mdesc[i].base; 509 + mdesc[i].size = CPHYSADDR(PAGE_ALIGN((u32)_end)) - mdesc[i].base; 512 510 513 511 /* Remainder of RAM -- under memsize */ 514 512 i++; /* 5 */ ··· 506 528 507 529 return &mdesc[0]; 508 530 } 509 - 510 - /* rootfs functions */ 511 - #ifdef CONFIG_MTD_PMC_MSP_RAMROOT 512 - bool get_ramroot(void **start, unsigned long *size) 513 - { 514 - extern char _end[]; 515 - 516 - /* Check for start following the end of the kernel */ 517 - void *check_start = (void *)_end; 518 - 519 - /* Check for supported rootfs types */ 520 - #ifdef CONFIG_CRAMFS 521 - if (*(__u32 *)check_start == CRAMFS_MAGIC) { 522 - /* Get CRAMFS size */ 523 - *start = check_start; 524 - *size = PAGE_ALIGN(((struct cramfs_super *) 525 - check_start)->size); 526 - 527 - return true; 528 - } 529 - #endif 530 - #ifdef CONFIG_SQUASHFS 531 - if (*((unsigned int *)check_start) == SQUASHFS_MAGIC) { 532 - /* Get SQUASHFS size */ 533 - *start = check_start; 534 - *size = PAGE_ALIGN(((struct squashfs_super_block *) 535 - check_start)->bytes_used); 536 - 537 - return true; 538 - } 539 - #endif 540 - 541 - return false; 542 - } 543 - EXPORT_SYMBOL(get_ramroot); 544 - #endif
+2 -6
arch/mips/pmc-sierra/msp71xx/msp_setup.c
··· 21 21 22 22 #if defined(CONFIG_PMC_MSP7120_GW) 23 23 #include <msp_regops.h> 24 - #include <msp_gpio.h> 25 24 #define MSP_BOARD_RESET_GPIO 9 26 25 #endif 27 26 ··· 87 88 * as GPIO char driver may not be enabled and it would look up 88 89 * data inRAM! 89 90 */ 90 - set_value_reg32(GPIO_CFG3_REG, 91 - basic_mode_mask(MSP_BOARD_RESET_GPIO), 92 - basic_mode(MSP_GPIO_OUTPUT, MSP_BOARD_RESET_GPIO)); 93 - set_reg32(GPIO_DATA3_REG, 94 - basic_data_mask(MSP_BOARD_RESET_GPIO)); 91 + set_value_reg32(GPIO_CFG3_REG, 0xf000, 0x8000); 92 + set_reg32(GPIO_DATA3_REG, 8); 95 93 96 94 /* 97 95 * In case GPIO9 doesn't reset the board (jumper configurable!)
+2 -5
arch/mips/pmc-sierra/msp71xx/msp_time.c
··· 81 81 mips_hpt_frequency = cpu_rate/2; 82 82 } 83 83 84 - void __init plat_timer_setup(struct irqaction *irq) 84 + unsigned int __init get_c0_compare_int(void) 85 85 { 86 - #ifdef CONFIG_IRQ_MSP_CIC 87 - /* we are using the vpe0 counter for timer interrupts */ 88 - setup_irq(MSP_INT_VPE0_TIMER, irq); 89 - #endif 86 + return MSP_INT_VPE0_TIMER; 90 87 }
+1 -1
arch/mips/sgi-ip32/ip32-berr.c
··· 16 16 #include <asm/ptrace.h> 17 17 #include <asm/tlbdebug.h> 18 18 19 - int ip32_be_handler(struct pt_regs *regs, int is_fixup) 19 + static int ip32_be_handler(struct pt_regs *regs, int is_fixup) 20 20 { 21 21 int data = regs->cp0_cause & 4; 22 22
+2 -2
arch/mips/sgi-ip32/ip32-irq.c
··· 112 112 extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); 113 113 extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); 114 114 115 - struct irqaction memerr_irq = { 115 + static struct irqaction memerr_irq = { 116 116 .handler = crime_memerr_intr, 117 117 .flags = IRQF_DISABLED, 118 118 .name = "CRIME memory error", 119 119 }; 120 120 121 - struct irqaction cpuerr_irq = { 121 + static struct irqaction cpuerr_irq = { 122 122 .handler = crime_cpuerr_intr, 123 123 .flags = IRQF_DISABLED, 124 124 .name = "CRIME CPU error",
+2 -5
arch/mips/sibyte/bcm1480/irq.c
··· 113 113 { 114 114 int i = 0, old_cpu, cpu, int_on, k; 115 115 u64 cur_ints; 116 - struct irq_desc *desc = irq_desc + irq; 117 116 unsigned long flags; 118 117 unsigned int irq_dirty; 119 118 ··· 126 127 cpu = cpu_logical_map(i); 127 128 128 129 /* Protect against other affinity changers and IMR manipulation */ 129 - spin_lock_irqsave(&desc->lock, flags); 130 - spin_lock(&bcm1480_imr_lock); 130 + spin_lock_irqsave(&bcm1480_imr_lock, flags); 131 131 132 132 /* Swizzle each CPU's IMR (but leave the IP selection alone) */ 133 133 old_cpu = bcm1480_irq_owner[irq]; ··· 151 153 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 152 154 } 153 155 } 154 - spin_unlock(&bcm1480_imr_lock); 155 - spin_unlock_irqrestore(&desc->lock, flags); 156 + spin_unlock_irqrestore(&bcm1480_imr_lock, flags); 156 157 } 157 158 #endif 158 159
+2 -5
arch/mips/sibyte/sb1250/irq.c
··· 107 107 { 108 108 int i = 0, old_cpu, cpu, int_on; 109 109 u64 cur_ints; 110 - struct irq_desc *desc = irq_desc + irq; 111 110 unsigned long flags; 112 111 113 112 i = cpumask_first(mask); ··· 120 121 cpu = cpu_logical_map(i); 121 122 122 123 /* Protect against other affinity changers and IMR manipulation */ 123 - spin_lock_irqsave(&desc->lock, flags); 124 - spin_lock(&sb1250_imr_lock); 124 + spin_lock_irqsave(&sb1250_imr_lock, flags); 125 125 126 126 /* Swizzle each CPU's IMR (but leave the IP selection alone) */ 127 127 old_cpu = sb1250_irq_owner[irq]; ··· 142 144 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + 143 145 R_IMR_INTERRUPT_MASK)); 144 146 } 145 - spin_unlock(&sb1250_imr_lock); 146 - spin_unlock_irqrestore(&desc->lock, flags); 147 + spin_unlock_irqrestore(&sb1250_imr_lock, flags); 147 148 } 148 149 #endif 149 150
+1 -1
arch/mips/txx9/generic/setup_tx4927.c
··· 88 88 { 89 89 int i; 90 90 __u32 divmode; 91 - int cpuclk = 0; 91 + unsigned int cpuclk = 0; 92 92 u64 ccfg; 93 93 94 94 txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
+1 -1
arch/mips/txx9/generic/setup_tx4938.c
··· 93 93 { 94 94 int i; 95 95 __u32 divmode; 96 - int cpuclk = 0; 96 + unsigned int cpuclk = 0; 97 97 u64 ccfg; 98 98 99 99 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
+1 -1
arch/mips/txx9/generic/setup_tx4939.c
··· 114 114 int i; 115 115 __u32 divmode; 116 116 __u64 pcfg; 117 - int cpuclk = 0; 117 + unsigned int cpuclk = 0; 118 118 119 119 txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE, 120 120 TX4939_REG_SIZE);
+1 -1
arch/mips/txx9/rbtx4939/setup.c
··· 536 536 } 537 537 538 538 struct txx9_board_vec rbtx4939_vec __initdata = { 539 - .system = "Tothiba RBTX4939", 539 + .system = "Toshiba RBTX4939", 540 540 .prom_init = rbtx4939_prom_init, 541 541 .mem_setup = rbtx4939_setup, 542 542 .irq_setup = rbtx4939_irq_setup,
+7 -7
drivers/video/gbefb.c
··· 75 75 static unsigned int gbe_mem_size = CONFIG_FB_GBE_MEM * 1024*1024; 76 76 static void *gbe_mem; 77 77 static dma_addr_t gbe_dma_addr; 78 - unsigned long gbe_mem_phys; 78 + static unsigned long gbe_mem_phys; 79 79 80 80 static struct { 81 81 uint16_t *cpu; ··· 185 185 .vmode = FB_VMODE_NONINTERLACED, 186 186 }; 187 187 188 - struct fb_videomode *default_mode __initdata = &default_mode_CRT; 189 - struct fb_var_screeninfo *default_var __initdata = &default_var_CRT; 188 + static struct fb_videomode *default_mode __initdata = &default_mode_CRT; 189 + static struct fb_var_screeninfo *default_var __initdata = &default_var_CRT; 190 190 191 191 static int flat_panel_enabled = 0; 192 192 ··· 205 205 * console. 206 206 */ 207 207 208 - void gbe_turn_off(void) 208 + static void gbe_turn_off(void) 209 209 { 210 210 int i; 211 211 unsigned int val, x, y, vpixen_off; ··· 1097 1097 * Initialization 1098 1098 */ 1099 1099 1100 - int __init gbefb_setup(char *options) 1100 + static int __init gbefb_setup(char *options) 1101 1101 { 1102 1102 char *this_opt; 1103 1103 ··· 1283 1283 1284 1284 static struct platform_device *gbefb_device; 1285 1285 1286 - int __init gbefb_init(void) 1286 + static int __init gbefb_init(void) 1287 1287 { 1288 1288 int ret = platform_driver_register(&gbefb_driver); 1289 1289 if (!ret) { ··· 1301 1301 return ret; 1302 1302 } 1303 1303 1304 - void __exit gbefb_exit(void) 1304 + static void __exit gbefb_exit(void) 1305 1305 { 1306 1306 platform_device_unregister(gbefb_device); 1307 1307 platform_driver_unregister(&gbefb_driver);