perf/x86/intel: Use cache cpu-type for hybrid PMU selection

get_this_hybrid_cpu_type() misses a case when cpu-type is populated
regardless of X86_FEATURE_HYBRID_CPU. This is particularly true for hybrid
variants that have P or E cores fused off.

Instead use the cpu-type cached in struct x86_topology, as it does not rely
on hybrid feature to enumerate cpu-type. This can also help avoid the
model-specific fixup get_hybrid_cpu_type(). Also replace the
get_this_hybrid_cpu_native_id() with its cached value in struct
x86_topology.

While at it, remove enum hybrid_cpu_type as it serves no purpose when we
have the exact cpu-types defined in enum intel_cpu_type. Also rename
atom_native_id to intel_native_id and move it to intel-family.h where
intel_cpu_type lives.

Suggested-by: Dave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/r/20241211-add-cpu-type-v5-3-2ae010f50370@linux.intel.com

authored by

Pawan Gupta and committed by

Ingo Molnar 1 year ago c4a8b711 b52aaeea

+25 -28

3 changed files

expand all

arch

x86

events

intel

core.c

perf_event.h

include

asm

intel-family.h

+10 -9

arch/x86/events/intel/core.c

··· 4606 4606 return -EOPNOTSUPP; 4607 4607 } 4608 4608 4609 - static enum hybrid_cpu_type adl_get_hybrid_cpu_type(void) 4609 + static enum intel_cpu_type adl_get_hybrid_cpu_type(void) 4610 4610 { 4611 - return HYBRID_INTEL_CORE; 4611 + return INTEL_CPU_TYPE_CORE; 4612 4612 } 4613 4613 4614 4614 static inline bool erratum_hsw11(struct perf_event *event) ··· 4953 4953 4954 4954 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void) 4955 4955 { 4956 - u8 cpu_type = get_this_hybrid_cpu_type(); 4956 + struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 4957 + enum intel_cpu_type cpu_type = c->topo.intel_type; 4957 4958 int i; 4958 4959 4959 4960 /* ··· 4963 4962 * on it. There should be a fixup function provided for these 4964 4963 * troublesome CPUs (->get_hybrid_cpu_type). 4965 4964 */ 4966 - if (cpu_type == HYBRID_INTEL_NONE) { 4965 + if (cpu_type == INTEL_CPU_TYPE_UNKNOWN) { 4967 4966 if (x86_pmu.get_hybrid_cpu_type) 4968 4967 cpu_type = x86_pmu.get_hybrid_cpu_type(); 4969 4968 else ··· 4980 4979 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type; 4981 4980 u32 native_id; 4982 4981 4983 - if (cpu_type == HYBRID_INTEL_CORE && pmu_type == hybrid_big) 4982 + if (cpu_type == INTEL_CPU_TYPE_CORE && pmu_type == hybrid_big) 4984 4983 return &x86_pmu.hybrid_pmu[i]; 4985 - if (cpu_type == HYBRID_INTEL_ATOM) { 4984 + if (cpu_type == INTEL_CPU_TYPE_ATOM) { 4986 4985 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small) 4987 4986 return &x86_pmu.hybrid_pmu[i]; 4988 4987 4989 - native_id = get_this_hybrid_cpu_native_id(); 4990 - if (native_id == skt_native_id && pmu_type == hybrid_small) 4988 + native_id = c->topo.intel_native_model_id; 4989 + if (native_id == INTEL_ATOM_SKT_NATIVE_ID && pmu_type == hybrid_small) 4991 4990 return &x86_pmu.hybrid_pmu[i]; 4992 - if (native_id == cmt_native_id && pmu_type == hybrid_tiny) 4991 + if (native_id == INTEL_ATOM_CMT_NATIVE_ID && pmu_type == hybrid_tiny) 4993 4992 return &x86_pmu.hybrid_pmu[i]; 4994 4993 } 4995 4994 }

+1 -18

arch/x86/events/perf_event.h

··· 669 669 #define PERF_PEBS_DATA_SOURCE_GRT_MAX 0x10 670 670 #define PERF_PEBS_DATA_SOURCE_GRT_MASK (PERF_PEBS_DATA_SOURCE_GRT_MAX - 1) 671 671 672 - /* 673 - * CPUID.1AH.EAX[31:0] uniquely identifies the microarchitecture 674 - * of the core. Bits 31-24 indicates its core type (Core or Atom) 675 - * and Bits [23:0] indicates the native model ID of the core. 676 - * Core type and native model ID are defined in below enumerations. 677 - */ 678 - enum hybrid_cpu_type { 679 - HYBRID_INTEL_NONE, 680 - HYBRID_INTEL_ATOM = 0x20, 681 - HYBRID_INTEL_CORE = 0x40, 682 - }; 683 - 684 672 #define X86_HYBRID_PMU_ATOM_IDX 0 685 673 #define X86_HYBRID_PMU_CORE_IDX 1 686 674 #define X86_HYBRID_PMU_TINY_IDX 2 ··· 683 695 hybrid_big_small = hybrid_big | hybrid_small, 684 696 hybrid_small_tiny = hybrid_small | hybrid_tiny, 685 697 hybrid_big_small_tiny = hybrid_big | hybrid_small_tiny, 686 - }; 687 - 688 - enum atom_native_id { 689 - cmt_native_id = 0x2, /* Crestmont */ 690 - skt_native_id = 0x3, /* Skymont */ 691 698 }; 692 699 693 700 struct x86_hybrid_pmu { ··· 977 994 */ 978 995 int num_hybrid_pmus; 979 996 struct x86_hybrid_pmu *hybrid_pmu; 980 - enum hybrid_cpu_type (*get_hybrid_cpu_type) (void); 997 + enum intel_cpu_type (*get_hybrid_cpu_type) (void); 981 998 }; 982 999 983 1000 struct x86_perf_task_context_opt {

+14 -1

arch/x86/include/asm/intel-family.h

··· 182 182 /* Family 19 */ 183 183 #define INTEL_PANTHERCOVE_X IFM(19, 0x01) /* Diamond Rapids */ 184 184 185 - /* CPU core types */ 185 + /* 186 + * Intel CPU core types 187 + * 188 + * CPUID.1AH.EAX[31:0] uniquely identifies the microarchitecture 189 + * of the core. Bits 31-24 indicates its core type (Core or Atom) 190 + * and Bits [23:0] indicates the native model ID of the core. 191 + * Core type and native model ID are defined in below enumerations. 192 + */ 186 193 enum intel_cpu_type { 194 + INTEL_CPU_TYPE_UNKNOWN, 187 195 INTEL_CPU_TYPE_ATOM = 0x20, 188 196 INTEL_CPU_TYPE_CORE = 0x40, 197 + }; 198 + 199 + enum intel_native_id { 200 + INTEL_ATOM_CMT_NATIVE_ID = 0x2, /* Crestmont */ 201 + INTEL_ATOM_SKT_NATIVE_ID = 0x3, /* Skymont */ 189 202 }; 190 203 191 204 #endif /* _ASM_X86_INTEL_FAMILY_H */

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