Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann:
"Small fixes on multiple ARM platforms
- A build regression from a previous fix on dove and mv78xx0
- Two fixes for recently (3.5-rc1) changed mmp/pxa code
- multiple omap2+ bug fixes
- two trivial fixes for i.MX
- one v3.5 regression for mxs"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: apx4devkit: fix FEC enabling PHY clock
ARM: OMAP2+: hwmod data: Fix wrong McBSP clock alias on OMAP4
ARM: OMAP4: hwmod data: temporarily comment out data for the usb_host_fs and aess IP blocks
ARM: Orion: Fix WDT compile for Dove and MV78xx0
ARM: mmp: remove mach/gpio-pxa.h
ARM: imx: assert SCC gate stays enabled
ARM: OMAP4: TWL6030: ensure sys_nirq1 is mux'd and wakeup enabled
ARM: OMAP2: Overo: init I2C before MMC to fix MMC suspend/resume failure
ARM: imx27_visstrim_m10: Do not include <asm/system.h>
ARM: pxa: hx4700: Fix basic suspend/resume
+56
-47
+1
arch/arm/mach-dove/include/mach/bridge-regs.h
+1
arch/arm/mach-dove/include/mach/bridge-regs.h
+1
arch/arm/mach-dove/include/mach/dove.h
+1
arch/arm/mach-dove/include/mach/dove.h
+8
-1
arch/arm/mach-imx/clk-imx35.c
+8
-1
arch/arm/mach-imx/clk-imx35.c
···
201
201
pr_err("i.MX35 clk %d: register failed with %ld\n",
202
202
i, PTR_ERR(clk[i]));
203
203
204
-
205
204
clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
206
205
clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
207
206
clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
···
262
263
clk_prepare_enable(clk[gpio3_gate]);
263
264
clk_prepare_enable(clk[iim_gate]);
264
265
clk_prepare_enable(clk[emi_gate]);
266
+
267
+
/*
268
+
* SCC is needed to boot via mmc after a watchdog reset. The clock code
269
+
* before conversion to common clk also enabled UART1 (which isn't
270
+
* handled here and not needed for mmc) and IIM (which is enabled
271
+
* unconditionally above).
272
+
*/
273
+
clk_prepare_enable(clk[scc_gate]);
265
274
266
275
imx_print_silicon_rev("i.MX35", mx35_revision());
267
276
+1
-1
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+1
-1
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
-29
arch/arm/mach-mmp/include/mach/gpio-pxa.h
-29
arch/arm/mach-mmp/include/mach/gpio-pxa.h
···
1
-
#ifndef __ASM_MACH_GPIO_PXA_H
2
-
#define __ASM_MACH_GPIO_PXA_H
3
-
4
-
#include <mach/addr-map.h>
5
-
#include <mach/cputype.h>
6
-
#include <mach/irqs.h>
7
-
8
-
#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000)
9
-
10
-
#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
11
-
#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
12
-
13
-
#define gpio_to_bank(gpio) ((gpio) >> 5)
14
-
15
-
/* NOTE: these macros are defined here to make optimization of
16
-
* gpio_{get,set}_value() to work when 'gpio' is a constant.
17
-
* Usage of these macros otherwise is no longer recommended,
18
-
* use generic GPIO API whenever possible.
19
-
*/
20
-
#define GPIO_bit(gpio) (1 << ((gpio) & 0x1f))
21
-
22
-
#define GPLR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x00)
23
-
#define GPDR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x0c)
24
-
#define GPSR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x18)
25
-
#define GPCR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x24)
26
-
27
-
#include <plat/gpio-pxa.h>
28
-
29
-
#endif /* __ASM_MACH_GPIO_PXA_H */
+1
arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+1
arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+2
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+2
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
···
42
42
#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43
43
#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44
44
#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000
45
+
#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45
46
#define MV78XX0_CORE_REGS_SIZE SZ_16K
46
47
47
48
#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
···
60
59
* Core-specific peripheral registers.
61
60
*/
62
61
#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
62
+
#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE)
63
63
64
64
/*
65
65
* Register Map
+11
arch/arm/mach-mxs/mach-apx4devkit.c
+11
arch/arm/mach-mxs/mach-apx4devkit.c
···
205
205
return 0;
206
206
}
207
207
208
+
static void __init apx4devkit_fec_phy_clk_enable(void)
209
+
{
210
+
struct clk *clk;
211
+
212
+
/* Enable fec phy clock */
213
+
clk = clk_get_sys("enet_out", NULL);
214
+
if (!IS_ERR(clk))
215
+
clk_prepare_enable(clk);
216
+
}
217
+
208
218
static void __init apx4devkit_init(void)
209
219
{
210
220
mx28_soc_init();
···
235
225
phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK,
236
226
apx4devkit_phy_fixup);
237
227
228
+
apx4devkit_fec_phy_clk_enable();
238
229
mx28_add_fec(0, &mx28_fec_pdata);
239
230
240
231
mx28_add_mxs_mmc(0, &apx4devkit_mmc_pdata);
+1
-1
arch/arm/mach-omap2/board-overo.c
+1
-1
arch/arm/mach-omap2/board-overo.c
···
494
494
495
495
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
496
496
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
497
-
omap_hsmmc_init(mmc);
498
497
overo_i2c_init();
498
+
omap_hsmmc_init(mmc);
499
499
omap_display_init(&overo_dss_data);
500
500
omap_serial_init();
501
501
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
+14
-14
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+14
-14
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
···
1928
1928
1929
1929
static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1930
1930
{ .role = "pad_fck", .clk = "pad_clks_ck" },
1931
-
{ .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
1931
+
{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1932
1932
};
1933
1933
1934
1934
static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
···
1963
1963
1964
1964
static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1965
1965
{ .role = "pad_fck", .clk = "pad_clks_ck" },
1966
-
{ .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
1966
+
{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1967
1967
};
1968
1968
1969
1969
static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
···
1998
1998
1999
1999
static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2000
2000
{ .role = "pad_fck", .clk = "pad_clks_ck" },
2001
-
{ .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
2001
+
{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2002
2002
};
2003
2003
2004
2004
static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
···
2033
2033
2034
2034
static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2035
2035
{ .role = "pad_fck", .clk = "pad_clks_ck" },
2036
-
{ .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
2036
+
{ .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2037
2037
};
2038
2038
2039
2039
static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
···
3864
3864
};
3865
3865
3866
3866
/* usb_host_fs -> l3_main_2 */
3867
-
static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
3867
+
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3868
3868
.master = &omap44xx_usb_host_fs_hwmod,
3869
3869
.slave = &omap44xx_l3_main_2_hwmod,
3870
3870
.clk = "l3_div_ck",
···
3922
3922
};
3923
3923
3924
3924
/* aess -> l4_abe */
3925
-
static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
3925
+
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3926
3926
.master = &omap44xx_aess_hwmod,
3927
3927
.slave = &omap44xx_l4_abe_hwmod,
3928
3928
.clk = "ocp_abe_iclk",
···
4013
4013
};
4014
4014
4015
4015
/* l4_abe -> aess */
4016
-
static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
4016
+
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4017
4017
.master = &omap44xx_l4_abe_hwmod,
4018
4018
.slave = &omap44xx_aess_hwmod,
4019
4019
.clk = "ocp_abe_iclk",
···
4031
4031
};
4032
4032
4033
4033
/* l4_abe -> aess (dma) */
4034
-
static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
4034
+
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4035
4035
.master = &omap44xx_l4_abe_hwmod,
4036
4036
.slave = &omap44xx_aess_hwmod,
4037
4037
.clk = "ocp_abe_iclk",
···
5857
5857
};
5858
5858
5859
5859
/* l4_cfg -> usb_host_fs */
5860
-
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
5860
+
static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
5861
5861
.master = &omap44xx_l4_cfg_hwmod,
5862
5862
.slave = &omap44xx_usb_host_fs_hwmod,
5863
5863
.clk = "l4_div_ck",
···
6014
6014
&omap44xx_iva__l3_main_2,
6015
6015
&omap44xx_l3_main_1__l3_main_2,
6016
6016
&omap44xx_l4_cfg__l3_main_2,
6017
-
&omap44xx_usb_host_fs__l3_main_2,
6017
+
/* &omap44xx_usb_host_fs__l3_main_2, */
6018
6018
&omap44xx_usb_host_hs__l3_main_2,
6019
6019
&omap44xx_usb_otg_hs__l3_main_2,
6020
6020
&omap44xx_l3_main_1__l3_main_3,
6021
6021
&omap44xx_l3_main_2__l3_main_3,
6022
6022
&omap44xx_l4_cfg__l3_main_3,
6023
-
&omap44xx_aess__l4_abe,
6023
+
/* &omap44xx_aess__l4_abe, */
6024
6024
&omap44xx_dsp__l4_abe,
6025
6025
&omap44xx_l3_main_1__l4_abe,
6026
6026
&omap44xx_mpu__l4_abe,
···
6029
6029
&omap44xx_l4_cfg__l4_wkup,
6030
6030
&omap44xx_mpu__mpu_private,
6031
6031
&omap44xx_l4_cfg__ocp_wp_noc,
6032
-
&omap44xx_l4_abe__aess,
6033
-
&omap44xx_l4_abe__aess_dma,
6032
+
/* &omap44xx_l4_abe__aess, */
6033
+
/* &omap44xx_l4_abe__aess_dma, */
6034
6034
&omap44xx_l3_main_2__c2c,
6035
6035
&omap44xx_l4_wkup__counter_32k,
6036
6036
&omap44xx_l4_cfg__ctrl_module_core,
···
6136
6136
&omap44xx_l4_per__uart2,
6137
6137
&omap44xx_l4_per__uart3,
6138
6138
&omap44xx_l4_per__uart4,
6139
-
&omap44xx_l4_cfg__usb_host_fs,
6139
+
/* &omap44xx_l4_cfg__usb_host_fs, */
6140
6140
&omap44xx_l4_cfg__usb_host_hs,
6141
6141
&omap44xx_l4_cfg__usb_otg_hs,
6142
6142
&omap44xx_l4_cfg__usb_tll_hs,
+2
arch/arm/mach-omap2/twl-common.c
+2
arch/arm/mach-omap2/twl-common.c
···
32
32
#include "twl-common.h"
33
33
#include "pm.h"
34
34
#include "voltage.h"
35
+
#include "mux.h"
35
36
36
37
static struct i2c_board_info __initdata pmic_i2c_board_info = {
37
38
.addr = 0x48,
···
78
77
struct twl6040_platform_data *twl6040_data, int twl6040_irq)
79
78
{
80
79
/* PMIC part*/
80
+
omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
81
81
strncpy(omap4_i2c1_board_info[0].type, pmic_type,
82
82
sizeof(omap4_i2c1_board_info[0].type));
83
83
omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
+14
-1
arch/arm/mach-pxa/hx4700.c
+14
-1
arch/arm/mach-pxa/hx4700.c
···
127
127
GPIO19_SSP2_SCLK,
128
128
GPIO86_SSP2_RXD,
129
129
GPIO87_SSP2_TXD,
130
-
GPIO88_GPIO,
130
+
GPIO88_GPIO | MFP_LPM_DRIVE_HIGH, /* TSC2046_CS */
131
+
132
+
/* BQ24022 Regulator */
133
+
GPIO72_GPIO | MFP_LPM_KEEP_OUTPUT, /* BQ24022_nCHARGE_EN */
134
+
GPIO96_GPIO | MFP_LPM_KEEP_OUTPUT, /* BQ24022_ISET2 */
131
135
132
136
/* HX4700 specific input GPIOs */
133
137
GPIO12_GPIO | WAKEUP_ON_EDGE_RISE, /* ASIC3_IRQ */
···
139
135
GPIO14_GPIO, /* nWLAN_IRQ */
140
136
141
137
/* HX4700 specific output GPIOs */
138
+
GPIO61_GPIO | MFP_LPM_DRIVE_HIGH, /* W3220_nRESET */
139
+
GPIO71_GPIO | MFP_LPM_DRIVE_HIGH, /* ASIC3_nRESET */
140
+
GPIO81_GPIO | MFP_LPM_DRIVE_HIGH, /* CPU_GP_nRESET */
141
+
GPIO116_GPIO | MFP_LPM_DRIVE_HIGH, /* CPU_HW_nRESET */
142
142
GPIO102_GPIO | MFP_LPM_DRIVE_LOW, /* SYNAPTICS_POWER_ON */
143
143
144
144
GPIO10_GPIO, /* GSM_IRQ */
···
880
872
{ GPIO110_HX4700_LCD_LVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_LVDD" },
881
873
{ GPIO111_HX4700_LCD_AVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_AVDD" },
882
874
{ GPIO32_HX4700_RS232_ON, GPIOF_OUT_INIT_HIGH, "RS232_ON" },
875
+
{ GPIO61_HX4700_W3220_nRESET, GPIOF_OUT_INIT_HIGH, "W3220_nRESET" },
883
876
{ GPIO71_HX4700_ASIC3_nRESET, GPIOF_OUT_INIT_HIGH, "ASIC3_nRESET" },
877
+
{ GPIO81_HX4700_CPU_GP_nRESET, GPIOF_OUT_INIT_HIGH, "CPU_GP_nRESET" },
884
878
{ GPIO82_HX4700_EUART_RESET, GPIOF_OUT_INIT_HIGH, "EUART_RESET" },
879
+
{ GPIO116_HX4700_CPU_HW_nRESET, GPIOF_OUT_INIT_HIGH, "CPU_HW_nRESET" },
885
880
};
886
881
887
882
static void __init hx4700_init(void)
888
883
{
889
884
int ret;
885
+
886
+
PCFR = PCFR_GPR_EN | PCFR_OPDE;
890
887
891
888
pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config));
892
889
gpio_set_wake(GPIO12_HX4700_ASIC3_IRQ, 1);