Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: phy-rockchip-samsung-hdptx: Add clock provider support
The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC
CRU. It provides more accurate clock rates required by VOP2 to improve
existing support for display modes handling, which is known to be
problematic when dealing with non-integer refresh rates, among others.
It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be
used to support HDMI 2.1 4K@120Hz mode.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20240620-rk3588-hdmiphy-clkprov-v2-4-6a2d2164e508@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Cristian Ciocaltea
and committed by
Vinod Koul
c4b09c56
a652f221
+173
-22
+173
-22
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+173
-22
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
···
8
8
*/
9
9
#include <linux/bitfield.h>
10
10
#include <linux/clk.h>
11
+
#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
···
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#define LN3_TX_SER_RATE_SEL_HBR2 BIT(3)
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#define LN3_TX_SER_RATE_SEL_HBR3 BIT(2)
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+
#define HDMI20_MAX_RATE 600000000
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+
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struct lcpll_config {
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u32 bit_rate;
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u8 lcvco_mode_en;
···
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struct clk_bulk_data *clks;
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int nr_clks;
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struct reset_control_bulk_data rsts[RST_MAX];
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/* clk provider */
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struct clk_hw hw;
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unsigned long rate;
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atomic_t usage_count;
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};
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static const struct ropll_config ropll_tmds_cfg[] = {
···
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struct ropll_config rc = {0};
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int i;
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hdptx->rate = rate * 100;
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772
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for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
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if (rate == ropll_tmds_cfg[i].bit_rate) {
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cfg = &ropll_tmds_cfg[i];
···
834
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static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
835
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unsigned int rate)
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{
837
-
u32 val;
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int ret;
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ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
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if (ret)
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return ret;
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-
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if (!(val & HDPTX_O_PLL_LOCK_DONE)) {
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ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
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if (ret)
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return ret;
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-
}
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rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
851
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regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
···
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return rk_hdptx_post_enable_lane(hdptx);
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}
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static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
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unsigned int rate)
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{
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u32 status;
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int ret;
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if (atomic_inc_return(&hdptx->usage_count) > 1)
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return 0;
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ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
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if (ret)
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goto dec_usage;
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if (status & HDPTX_O_PLL_LOCK_DONE)
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dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n");
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if (rate) {
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ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
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if (ret)
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goto dec_usage;
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}
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return 0;
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dec_usage:
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atomic_dec(&hdptx->usage_count);
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return ret;
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}
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static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force)
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{
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u32 status;
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int ret;
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ret = atomic_dec_return(&hdptx->usage_count);
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if (ret > 0)
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return 0;
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if (ret < 0) {
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dev_warn(hdptx->dev, "Usage count underflow!\n");
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ret = -EINVAL;
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} else {
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ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
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if (!ret) {
904
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if (status & HDPTX_O_PLL_LOCK_DONE)
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rk_hdptx_phy_disable(hdptx);
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return 0;
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} else if (force) {
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return 0;
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}
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}
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atomic_inc(&hdptx->usage_count);
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return ret;
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}
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static int rk_hdptx_phy_power_on(struct phy *phy)
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{
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struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
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int bus_width = phy_get_bus_width(hdptx->phy);
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int ret;
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/*
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* FIXME: Temporary workaround to pass pixel_clk_rate
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* from the HDMI bridge driver until phy_configure_opts_hdmi
···
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dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
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__func__, bus_width, rate);
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return rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
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ret = rk_hdptx_phy_consumer_get(hdptx, rate);
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if (ret)
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return ret;
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ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
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if (ret)
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rk_hdptx_phy_consumer_put(hdptx, true);
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return ret;
931
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}
932
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static int rk_hdptx_phy_power_off(struct phy *phy)
934
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{
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struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
936
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u32 val;
937
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int ret;
938
888
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ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val);
940
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if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE))
941
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rk_hdptx_phy_disable(hdptx);
942
-
943
-
return ret;
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return rk_hdptx_phy_consumer_put(hdptx, false);
944
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}
945
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static const struct phy_ops rk_hdptx_phy_ops = {
···
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.power_off = rk_hdptx_phy_power_off,
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.owner = THIS_MODULE,
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};
895
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static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw)
897
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{
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return container_of(hw, struct rk_hdptx_phy, hw);
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}
900
+
901
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static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw)
902
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{
903
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struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
904
+
905
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return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100);
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}
907
+
908
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static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
909
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{
910
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struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
911
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rk_hdptx_phy_consumer_put(hdptx, true);
913
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}
914
+
915
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static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
916
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unsigned long parent_rate)
917
+
{
918
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struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
919
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920
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return hdptx->rate;
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}
922
+
923
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static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
925
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{
926
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u32 bit_rate = rate / 100;
927
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int i;
928
+
929
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if (rate > HDMI20_MAX_RATE)
930
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return rate;
931
+
932
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for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
933
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if (bit_rate == ropll_tmds_cfg[i].bit_rate)
934
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break;
935
+
936
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if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
937
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!rk_hdptx_phy_clk_pll_calc(bit_rate, NULL))
938
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return -EINVAL;
939
+
940
+
return rate;
941
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}
942
+
943
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static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
944
+
unsigned long parent_rate)
945
+
{
946
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struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
947
+
948
+
return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100);
949
+
}
950
+
951
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static const struct clk_ops hdptx_phy_clk_ops = {
952
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.prepare = rk_hdptx_phy_clk_prepare,
953
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.unprepare = rk_hdptx_phy_clk_unprepare,
954
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.recalc_rate = rk_hdptx_phy_clk_recalc_rate,
955
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.round_rate = rk_hdptx_phy_clk_round_rate,
956
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.set_rate = rk_hdptx_phy_clk_set_rate,
957
+
};
958
+
959
+
static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx)
960
+
{
961
+
struct device *dev = hdptx->dev;
962
+
const char *name, *pname;
963
+
struct clk *refclk;
964
+
int ret, id;
965
+
966
+
refclk = devm_clk_get(dev, "ref");
967
+
if (IS_ERR(refclk))
968
+
return dev_err_probe(dev, PTR_ERR(refclk),
969
+
"Failed to get ref clock\n");
970
+
971
+
id = of_alias_get_id(dev->of_node, "hdptxphy");
972
+
name = id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0";
973
+
pname = __clk_get_name(refclk);
974
+
975
+
hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops,
976
+
CLK_GET_RATE_NOCACHE);
977
+
978
+
ret = devm_clk_hw_register(dev, &hdptx->hw);
979
+
if (ret)
980
+
return dev_err_probe(dev, ret, "Failed to register clock\n");
981
+
982
+
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw);
983
+
if (ret)
984
+
return dev_err_probe(dev, ret,
985
+
"Failed to register clk provider\n");
986
+
return 0;
987
+
}
953
988
954
989
static int rk_hdptx_phy_runtime_suspend(struct device *dev)
955
990
{
···
1138
987
reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
1139
988
reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
1140
989
1141
-
return 0;
990
+
return rk_hdptx_phy_clk_register(hdptx);
1142
991
}
1143
992
1144
993
static const struct dev_pm_ops rk_hdptx_phy_pm_ops = {