Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull more kvm updates from Paolo Bonzini:
- ARM fixes
- RISC-V Svade and Svadu (accessed and dirty bit) extension support for
host and guest
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test
RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM
dt-bindings: riscv: Add Svade and Svadu Entries
RISC-V: Add Svade and Svadu Extensions Support
KVM: arm64: Use MDCR_EL2.HPME to evaluate overflow of hyp counters
KVM: arm64: Ignore PMCNTENSET_EL0 while checking for overflow status
KVM: arm64: Mark set_sysreg_masks() as inline to avoid build failure
KVM: arm64: vgic-its: Add stronger type-checking to the ITS entry sizes
KVM: arm64: vgic: Kill VGIC_MAX_PRIVATE definition
KVM: arm64: vgic: Make vgic_get_irq() more robust
KVM: arm64: vgic-v3: Sanitise guest writes to GICR_INVLPIR
+257
-119
+28
Documentation/devicetree/bindings/riscv/extensions.yaml
+28
Documentation/devicetree/bindings/riscv/extensions.yaml
···
171
171
ratified at commit 3f9ed34 ("Add ability to manually trigger
172
172
workflow. (#2)") of riscv-time-compare.
173
173
174
+
- const: svade
175
+
description: |
176
+
The standard Svade supervisor-level extension for SW-managed PTE A/D
177
+
bit updates as ratified in the 20240213 version of the privileged
178
+
ISA specification.
179
+
180
+
Both Svade and Svadu extensions control the hardware behavior when
181
+
the PTE A/D bits need to be set. The default behavior for the four
182
+
possible combinations of these extensions in the device tree are:
183
+
1) Neither Svade nor Svadu present in DT => It is technically
184
+
unknown whether the platform uses Svade or Svadu. Supervisor
185
+
software should be prepared to handle either hardware updating
186
+
of the PTE A/D bits or page faults when they need updated.
187
+
2) Only Svade present in DT => Supervisor must assume Svade to be
188
+
always enabled.
189
+
3) Only Svadu present in DT => Supervisor must assume Svadu to be
190
+
always enabled.
191
+
4) Both Svade and Svadu present in DT => Supervisor must assume
192
+
Svadu turned-off at boot time. To use Svadu, supervisor must
193
+
explicitly enable it using the SBI FWFT extension.
194
+
195
+
- const: svadu
196
+
description: |
197
+
The standard Svadu supervisor-level extension for hardware updating
198
+
of PTE A/D bits as ratified in the 20240528 version of the
199
+
privileged ISA specification. Please refer to Svade dt-binding
200
+
description for more details.
201
+
174
202
- const: svinval
175
203
description:
176
204
The standard Svinval supervisor-level extension for fine-grained
+1
-1
arch/arm64/kvm/nested.c
+1
-1
arch/arm64/kvm/nested.c
+45
-17
arch/arm64/kvm/pmu-emul.c
+45
-17
arch/arm64/kvm/pmu-emul.c
···
274
274
irq_work_sync(&vcpu->arch.pmu.overflow_work);
275
275
}
276
276
277
-
bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu, unsigned int idx)
277
+
static u64 kvm_pmu_hyp_counter_mask(struct kvm_vcpu *vcpu)
278
278
{
279
-
unsigned int hpmn;
279
+
unsigned int hpmn, n;
280
280
281
-
if (!vcpu_has_nv(vcpu) || idx == ARMV8_PMU_CYCLE_IDX)
282
-
return false;
281
+
if (!vcpu_has_nv(vcpu))
282
+
return 0;
283
+
284
+
hpmn = SYS_FIELD_GET(MDCR_EL2, HPMN, __vcpu_sys_reg(vcpu, MDCR_EL2));
285
+
n = vcpu->kvm->arch.pmcr_n;
286
+
287
+
/*
288
+
* Programming HPMN to a value greater than PMCR_EL0.N is
289
+
* CONSTRAINED UNPREDICTABLE. Make the implementation choice that an
290
+
* UNKNOWN number of counters (in our case, zero) are reserved for EL2.
291
+
*/
292
+
if (hpmn >= n)
293
+
return 0;
283
294
284
295
/*
285
296
* Programming HPMN=0 is CONSTRAINED UNPREDICTABLE if FEAT_HPMN0 isn't
···
299
288
* implementation choice that all counters are included in the second
300
289
* range reserved for EL2/EL3.
301
290
*/
302
-
hpmn = SYS_FIELD_GET(MDCR_EL2, HPMN, __vcpu_sys_reg(vcpu, MDCR_EL2));
303
-
return idx >= hpmn;
291
+
return GENMASK(n - 1, hpmn);
292
+
}
293
+
294
+
bool kvm_pmu_counter_is_hyp(struct kvm_vcpu *vcpu, unsigned int idx)
295
+
{
296
+
return kvm_pmu_hyp_counter_mask(vcpu) & BIT(idx);
304
297
}
305
298
306
299
u64 kvm_pmu_accessible_counter_mask(struct kvm_vcpu *vcpu)
307
300
{
308
301
u64 mask = kvm_pmu_implemented_counter_mask(vcpu);
309
-
u64 hpmn;
310
302
311
303
if (!vcpu_has_nv(vcpu) || vcpu_is_el2(vcpu))
312
304
return mask;
313
305
314
-
hpmn = SYS_FIELD_GET(MDCR_EL2, HPMN, __vcpu_sys_reg(vcpu, MDCR_EL2));
315
-
return mask & ~GENMASK(vcpu->kvm->arch.pmcr_n - 1, hpmn);
306
+
return mask & ~kvm_pmu_hyp_counter_mask(vcpu);
316
307
}
317
308
318
309
u64 kvm_pmu_implemented_counter_mask(struct kvm_vcpu *vcpu)
···
388
375
}
389
376
}
390
377
391
-
static u64 kvm_pmu_overflow_status(struct kvm_vcpu *vcpu)
378
+
/*
379
+
* Returns the PMU overflow state, which is true if there exists an event
380
+
* counter where the values of the global enable control, PMOVSSET_EL0[n], and
381
+
* PMINTENSET_EL1[n] are all 1.
382
+
*/
383
+
static bool kvm_pmu_overflow_status(struct kvm_vcpu *vcpu)
392
384
{
393
-
u64 reg = 0;
385
+
u64 reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
394
386
395
-
if ((kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E)) {
396
-
reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
397
-
reg &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
398
-
reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
399
-
}
387
+
reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
388
+
389
+
/*
390
+
* PMCR_EL0.E is the global enable control for event counters available
391
+
* to EL0 and EL1.
392
+
*/
393
+
if (!(kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E))
394
+
reg &= kvm_pmu_hyp_counter_mask(vcpu);
395
+
396
+
/*
397
+
* Otherwise, MDCR_EL2.HPME is the global enable control for event
398
+
* counters reserved for EL2.
399
+
*/
400
+
if (!(vcpu_read_sys_reg(vcpu, MDCR_EL2) & MDCR_EL2_HPME))
401
+
reg &= ~kvm_pmu_hyp_counter_mask(vcpu);
400
402
401
403
return reg;
402
404
}
···
424
396
if (!kvm_vcpu_has_pmu(vcpu))
425
397
return;
426
398
427
-
overflow = !!kvm_pmu_overflow_status(vcpu);
399
+
overflow = kvm_pmu_overflow_status(vcpu);
428
400
if (pmu->irq_level == overflow)
429
401
return;
430
402
+4
-1
arch/arm64/kvm/vgic/vgic-debug.c
+4
-1
arch/arm64/kvm/vgic/vgic-debug.c
···
287
287
* Expect this to succeed, as iter_mark_lpis() takes a reference on
288
288
* every LPI to be visited.
289
289
*/
290
-
irq = vgic_get_irq(kvm, vcpu, iter->intid);
290
+
if (iter->intid < VGIC_NR_PRIVATE_IRQS)
291
+
irq = vgic_get_vcpu_irq(vcpu, iter->intid);
292
+
else
293
+
irq = vgic_get_irq(kvm, iter->intid);
291
294
if (WARN_ON_ONCE(!irq))
292
295
return -EINVAL;
293
296
+1
-1
arch/arm64/kvm/vgic/vgic-init.c
+1
-1
arch/arm64/kvm/vgic/vgic-init.c
+54
-23
arch/arm64/kvm/vgic/vgic-its.c
+54
-23
arch/arm64/kvm/vgic/vgic-its.c
···
31
31
static int update_lpi_config(struct kvm *kvm, struct vgic_irq *irq,
32
32
struct kvm_vcpu *filter_vcpu, bool needs_inv);
33
33
34
+
#define vgic_its_read_entry_lock(i, g, valp, t) \
35
+
({ \
36
+
int __sz = vgic_its_get_abi(i)->t##_esz; \
37
+
struct kvm *__k = (i)->dev->kvm; \
38
+
int __ret; \
39
+
\
40
+
BUILD_BUG_ON(NR_ITS_ABIS == 1 && \
41
+
sizeof(*(valp)) != ABI_0_ESZ); \
42
+
if (NR_ITS_ABIS > 1 && \
43
+
KVM_BUG_ON(__sz != sizeof(*(valp)), __k)) \
44
+
__ret = -EINVAL; \
45
+
else \
46
+
__ret = kvm_read_guest_lock(__k, (g), \
47
+
valp, __sz); \
48
+
__ret; \
49
+
})
50
+
51
+
#define vgic_its_write_entry_lock(i, g, val, t) \
52
+
({ \
53
+
int __sz = vgic_its_get_abi(i)->t##_esz; \
54
+
struct kvm *__k = (i)->dev->kvm; \
55
+
typeof(val) __v = (val); \
56
+
int __ret; \
57
+
\
58
+
BUILD_BUG_ON(NR_ITS_ABIS == 1 && \
59
+
sizeof(__v) != ABI_0_ESZ); \
60
+
if (NR_ITS_ABIS > 1 && \
61
+
KVM_BUG_ON(__sz != sizeof(__v), __k)) \
62
+
__ret = -EINVAL; \
63
+
else \
64
+
__ret = vgic_write_guest_lock(__k, (g), \
65
+
&__v, __sz); \
66
+
__ret; \
67
+
})
68
+
34
69
/*
35
70
* Creates a new (reference to a) struct vgic_irq for a given LPI.
36
71
* If this LPI is already mapped on another ITS, we increase its refcount
···
77
42
struct kvm_vcpu *vcpu)
78
43
{
79
44
struct vgic_dist *dist = &kvm->arch.vgic;
80
-
struct vgic_irq *irq = vgic_get_irq(kvm, NULL, intid), *oldirq;
45
+
struct vgic_irq *irq = vgic_get_irq(kvm, intid), *oldirq;
81
46
unsigned long flags;
82
47
int ret;
83
48
···
454
419
last_byte_offset = byte_offset;
455
420
}
456
421
457
-
irq = vgic_get_irq(vcpu->kvm, NULL, intid);
422
+
irq = vgic_get_irq(vcpu->kvm, intid);
458
423
if (!irq)
459
424
continue;
460
425
···
829
794
830
795
its_free_ite(kvm, ite);
831
796
832
-
return vgic_its_write_entry_lock(its, gpa, 0, ite_esz);
797
+
return vgic_its_write_entry_lock(its, gpa, 0ULL, ite);
833
798
}
834
799
835
800
return E_ITS_DISCARD_UNMAPPED_INTERRUPT;
···
1178
1143
bool valid = its_cmd_get_validbit(its_cmd);
1179
1144
u8 num_eventid_bits = its_cmd_get_size(its_cmd);
1180
1145
gpa_t itt_addr = its_cmd_get_ittaddr(its_cmd);
1181
-
int dte_esz = vgic_its_get_abi(its)->dte_esz;
1182
1146
struct its_device *device;
1183
1147
gpa_t gpa;
1184
1148
···
1202
1168
* is an error, so we are done in any case.
1203
1169
*/
1204
1170
if (!valid)
1205
-
return vgic_its_write_entry_lock(its, gpa, 0, dte_esz);
1171
+
return vgic_its_write_entry_lock(its, gpa, 0ULL, dte);
1206
1172
1207
1173
device = vgic_its_alloc_device(its, device_id, itt_addr,
1208
1174
num_eventid_bits);
···
1322
1288
unsigned long intid;
1323
1289
1324
1290
xa_for_each(&dist->lpi_xa, intid, irq) {
1325
-
irq = vgic_get_irq(kvm, NULL, intid);
1291
+
irq = vgic_get_irq(kvm, intid);
1326
1292
if (!irq)
1327
1293
continue;
1328
1294
···
1388
1354
return 0;
1389
1355
1390
1356
xa_for_each(&dist->lpi_xa, intid, irq) {
1391
-
irq = vgic_get_irq(kvm, NULL, intid);
1357
+
irq = vgic_get_irq(kvm, intid);
1392
1358
if (!irq)
1393
1359
continue;
1394
1360
···
2124
2090
* vgic_its_save_ite - Save an interrupt translation entry at @gpa
2125
2091
*/
2126
2092
static int vgic_its_save_ite(struct vgic_its *its, struct its_device *dev,
2127
-
struct its_ite *ite, gpa_t gpa, int ite_esz)
2093
+
struct its_ite *ite, gpa_t gpa)
2128
2094
{
2129
2095
u32 next_offset;
2130
2096
u64 val;
···
2135
2101
ite->collection->collection_id;
2136
2102
val = cpu_to_le64(val);
2137
2103
2138
-
return vgic_its_write_entry_lock(its, gpa, val, ite_esz);
2104
+
return vgic_its_write_entry_lock(its, gpa, val, ite);
2139
2105
}
2140
2106
2141
2107
/**
···
2235
2201
if (ite->irq->hw && !kvm_vgic_global_state.has_gicv4_1)
2236
2202
return -EACCES;
2237
2203
2238
-
ret = vgic_its_save_ite(its, device, ite, gpa, ite_esz);
2204
+
ret = vgic_its_save_ite(its, device, ite, gpa);
2239
2205
if (ret)
2240
2206
return ret;
2241
2207
}
···
2274
2240
* @its: ITS handle
2275
2241
* @dev: ITS device
2276
2242
* @ptr: GPA
2277
-
* @dte_esz: device table entry size
2278
2243
*/
2279
2244
static int vgic_its_save_dte(struct vgic_its *its, struct its_device *dev,
2280
-
gpa_t ptr, int dte_esz)
2245
+
gpa_t ptr)
2281
2246
{
2282
2247
u64 val, itt_addr_field;
2283
2248
u32 next_offset;
···
2289
2256
(dev->num_eventid_bits - 1));
2290
2257
val = cpu_to_le64(val);
2291
2258
2292
-
return vgic_its_write_entry_lock(its, ptr, val, dte_esz);
2259
+
return vgic_its_write_entry_lock(its, ptr, val, dte);
2293
2260
}
2294
2261
2295
2262
/**
···
2365
2332
*/
2366
2333
static int vgic_its_save_device_tables(struct vgic_its *its)
2367
2334
{
2368
-
const struct vgic_its_abi *abi = vgic_its_get_abi(its);
2369
2335
u64 baser = its->baser_device_table;
2370
2336
struct its_device *dev;
2371
-
int dte_esz = abi->dte_esz;
2372
2337
2373
2338
if (!(baser & GITS_BASER_VALID))
2374
2339
return 0;
···
2385
2354
if (ret)
2386
2355
return ret;
2387
2356
2388
-
ret = vgic_its_save_dte(its, dev, eaddr, dte_esz);
2357
+
ret = vgic_its_save_dte(its, dev, eaddr);
2389
2358
if (ret)
2390
2359
return ret;
2391
2360
}
···
2466
2435
2467
2436
static int vgic_its_save_cte(struct vgic_its *its,
2468
2437
struct its_collection *collection,
2469
-
gpa_t gpa, int esz)
2438
+
gpa_t gpa)
2470
2439
{
2471
2440
u64 val;
2472
2441
···
2475
2444
collection->collection_id);
2476
2445
val = cpu_to_le64(val);
2477
2446
2478
-
return vgic_its_write_entry_lock(its, gpa, val, esz);
2447
+
return vgic_its_write_entry_lock(its, gpa, val, cte);
2479
2448
}
2480
2449
2481
2450
/*
···
2483
2452
* Return +1 on success, 0 if the entry was invalid (which should be
2484
2453
* interpreted as end-of-table), and a negative error value for generic errors.
2485
2454
*/
2486
-
static int vgic_its_restore_cte(struct vgic_its *its, gpa_t gpa, int esz)
2455
+
static int vgic_its_restore_cte(struct vgic_its *its, gpa_t gpa)
2487
2456
{
2488
2457
struct its_collection *collection;
2489
2458
struct kvm *kvm = its->dev->kvm;
···
2491
2460
u64 val;
2492
2461
int ret;
2493
2462
2494
-
ret = vgic_its_read_entry_lock(its, gpa, &val, esz);
2463
+
ret = vgic_its_read_entry_lock(its, gpa, &val, cte);
2495
2464
if (ret)
2496
2465
return ret;
2497
2466
val = le64_to_cpu(val);
···
2538
2507
max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2539
2508
2540
2509
list_for_each_entry(collection, &its->collection_list, coll_list) {
2541
-
ret = vgic_its_save_cte(its, collection, gpa, cte_esz);
2510
+
ret = vgic_its_save_cte(its, collection, gpa);
2542
2511
if (ret)
2543
2512
return ret;
2544
2513
gpa += cte_esz;
···
2552
2521
* table is not fully filled, add a last dummy element
2553
2522
* with valid bit unset
2554
2523
*/
2555
-
return vgic_its_write_entry_lock(its, gpa, 0, cte_esz);
2524
+
return vgic_its_write_entry_lock(its, gpa, 0ULL, cte);
2556
2525
}
2557
2526
2558
2527
/*
···
2577
2546
max_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
2578
2547
2579
2548
while (read < max_size) {
2580
-
ret = vgic_its_restore_cte(its, gpa, cte_esz);
2549
+
ret = vgic_its_restore_cte(its, gpa);
2581
2550
if (ret <= 0)
2582
2551
break;
2583
2552
gpa += cte_esz;
+6
-6
arch/arm64/kvm/vgic/vgic-mmio-v2.c
+6
-6
arch/arm64/kvm/vgic/vgic-mmio-v2.c
···
148
148
if (!(targets & (1U << c)))
149
149
continue;
150
150
151
-
irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
151
+
irq = vgic_get_vcpu_irq(vcpu, intid);
152
152
153
153
raw_spin_lock_irqsave(&irq->irq_lock, flags);
154
154
irq->pending_latch = true;
···
167
167
u64 val = 0;
168
168
169
169
for (i = 0; i < len; i++) {
170
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
170
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
171
171
172
172
val |= (u64)irq->targets << (i * 8);
173
173
···
191
191
return;
192
192
193
193
for (i = 0; i < len; i++) {
194
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
194
+
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, intid + i);
195
195
int target;
196
196
197
197
raw_spin_lock_irqsave(&irq->irq_lock, flags);
···
213
213
u64 val = 0;
214
214
215
215
for (i = 0; i < len; i++) {
216
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
216
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
217
217
218
218
val |= (u64)irq->source << (i * 8);
219
219
···
231
231
unsigned long flags;
232
232
233
233
for (i = 0; i < len; i++) {
234
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
234
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
235
235
236
236
raw_spin_lock_irqsave(&irq->irq_lock, flags);
237
237
···
253
253
unsigned long flags;
254
254
255
255
for (i = 0; i < len; i++) {
256
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
256
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
257
257
258
258
raw_spin_lock_irqsave(&irq->irq_lock, flags);
259
259
+9
-4
arch/arm64/kvm/vgic/vgic-mmio-v3.c
+9
-4
arch/arm64/kvm/vgic/vgic-mmio-v3.c
···
194
194
gpa_t addr, unsigned int len)
195
195
{
196
196
int intid = VGIC_ADDR_TO_INTID(addr, 64);
197
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
197
+
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, intid);
198
198
unsigned long ret = 0;
199
199
200
200
if (!irq)
···
220
220
if (addr & 4)
221
221
return;
222
222
223
-
irq = vgic_get_irq(vcpu->kvm, NULL, intid);
223
+
irq = vgic_get_irq(vcpu->kvm, intid);
224
224
225
225
if (!irq)
226
226
return;
···
530
530
unsigned long val)
531
531
{
532
532
struct vgic_irq *irq;
533
+
u32 intid;
533
534
534
535
/*
535
536
* If the guest wrote only to the upper 32bit part of the
···
542
541
if ((addr & 4) || !vgic_lpis_enabled(vcpu))
543
542
return;
544
543
544
+
intid = lower_32_bits(val);
545
+
if (intid < VGIC_MIN_LPI)
546
+
return;
547
+
545
548
vgic_set_rdist_busy(vcpu, true);
546
549
547
-
irq = vgic_get_irq(vcpu->kvm, NULL, lower_32_bits(val));
550
+
irq = vgic_get_irq(vcpu->kvm, intid);
548
551
if (irq) {
549
552
vgic_its_inv_lpi(vcpu->kvm, irq);
550
553
vgic_put_irq(vcpu->kvm, irq);
···
1025
1020
1026
1021
static void vgic_v3_queue_sgi(struct kvm_vcpu *vcpu, u32 sgi, bool allow_group1)
1027
1022
{
1028
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, sgi);
1023
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, sgi);
1029
1024
unsigned long flags;
1030
1025
1031
1026
raw_spin_lock_irqsave(&irq->irq_lock, flags);
+19
-19
arch/arm64/kvm/vgic/vgic-mmio.c
+19
-19
arch/arm64/kvm/vgic/vgic-mmio.c
···
50
50
51
51
/* Loop over all IRQs affected by this read */
52
52
for (i = 0; i < len * 8; i++) {
53
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
53
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
54
54
55
55
if (irq->group)
56
56
value |= BIT(i);
···
74
74
unsigned long flags;
75
75
76
76
for (i = 0; i < len * 8; i++) {
77
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
77
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
78
78
79
79
raw_spin_lock_irqsave(&irq->irq_lock, flags);
80
80
irq->group = !!(val & BIT(i));
···
102
102
103
103
/* Loop over all IRQs affected by this read */
104
104
for (i = 0; i < len * 8; i++) {
105
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
105
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
106
106
107
107
if (irq->enabled)
108
108
value |= (1U << i);
···
122
122
unsigned long flags;
123
123
124
124
for_each_set_bit(i, &val, len * 8) {
125
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
125
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
126
126
127
127
raw_spin_lock_irqsave(&irq->irq_lock, flags);
128
128
if (irq->hw && vgic_irq_is_sgi(irq->intid)) {
···
171
171
unsigned long flags;
172
172
173
173
for_each_set_bit(i, &val, len * 8) {
174
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
174
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
175
175
176
176
raw_spin_lock_irqsave(&irq->irq_lock, flags);
177
177
if (irq->hw && vgic_irq_is_sgi(irq->intid) && irq->enabled)
···
193
193
unsigned long flags;
194
194
195
195
for_each_set_bit(i, &val, len * 8) {
196
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
196
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
197
197
198
198
raw_spin_lock_irqsave(&irq->irq_lock, flags);
199
199
irq->enabled = true;
···
214
214
unsigned long flags;
215
215
216
216
for_each_set_bit(i, &val, len * 8) {
217
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
217
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
218
218
219
219
raw_spin_lock_irqsave(&irq->irq_lock, flags);
220
220
irq->enabled = false;
···
236
236
237
237
/* Loop over all IRQs affected by this read */
238
238
for (i = 0; i < len * 8; i++) {
239
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
239
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
240
240
unsigned long flags;
241
241
bool val;
242
242
···
309
309
unsigned long flags;
310
310
311
311
for_each_set_bit(i, &val, len * 8) {
312
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
312
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
313
313
314
314
/* GICD_ISPENDR0 SGI bits are WI when written from the guest. */
315
315
if (is_vgic_v2_sgi(vcpu, irq) && !is_user) {
···
395
395
unsigned long flags;
396
396
397
397
for_each_set_bit(i, &val, len * 8) {
398
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
398
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
399
399
400
400
/* GICD_ICPENDR0 SGI bits are WI when written from the guest. */
401
401
if (is_vgic_v2_sgi(vcpu, irq) && !is_user) {
···
494
494
495
495
/* Loop over all IRQs affected by this read */
496
496
for (i = 0; i < len * 8; i++) {
497
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
497
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
498
498
499
499
/*
500
500
* Even for HW interrupts, don't evaluate the HW state as
···
598
598
int i;
599
599
600
600
for_each_set_bit(i, &val, len * 8) {
601
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
601
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
602
602
vgic_mmio_change_active(vcpu, irq, false);
603
603
vgic_put_irq(vcpu->kvm, irq);
604
604
}
···
635
635
int i;
636
636
637
637
for_each_set_bit(i, &val, len * 8) {
638
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
638
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
639
639
vgic_mmio_change_active(vcpu, irq, true);
640
640
vgic_put_irq(vcpu->kvm, irq);
641
641
}
···
672
672
u64 val = 0;
673
673
674
674
for (i = 0; i < len; i++) {
675
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
675
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
676
676
677
677
val |= (u64)irq->priority << (i * 8);
678
678
···
698
698
unsigned long flags;
699
699
700
700
for (i = 0; i < len; i++) {
701
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
701
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
702
702
703
703
raw_spin_lock_irqsave(&irq->irq_lock, flags);
704
704
/* Narrow the priority range to what we actually support */
···
719
719
int i;
720
720
721
721
for (i = 0; i < len * 4; i++) {
722
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
722
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, intid + i);
723
723
724
724
if (irq->config == VGIC_CONFIG_EDGE)
725
725
value |= (2U << (i * 2));
···
750
750
if (intid + i < VGIC_NR_PRIVATE_IRQS)
751
751
continue;
752
752
753
-
irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
753
+
irq = vgic_get_irq(vcpu->kvm, intid + i);
754
754
raw_spin_lock_irqsave(&irq->irq_lock, flags);
755
755
756
756
if (test_bit(i * 2 + 1, &val))
···
775
775
if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
776
776
continue;
777
777
778
-
irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
778
+
irq = vgic_get_vcpu_irq(vcpu, intid + i);
779
779
if (irq->config == VGIC_CONFIG_LEVEL && irq->line_level)
780
780
val |= (1U << i);
781
781
···
799
799
if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
800
800
continue;
801
801
802
-
irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
802
+
irq = vgic_get_vcpu_irq(vcpu, intid + i);
803
803
804
804
/*
805
805
* Line level is set irrespective of irq type
+1
-1
arch/arm64/kvm/vgic/vgic-v2.c
+1
-1
arch/arm64/kvm/vgic/vgic-v2.c
+1
-1
arch/arm64/kvm/vgic/vgic-v3.c
+1
-1
arch/arm64/kvm/vgic/vgic-v3.c
+2
-2
arch/arm64/kvm/vgic/vgic-v4.c
+2
-2
arch/arm64/kvm/vgic/vgic-v4.c
···
123
123
* IRQ. The SGI code will do its magic.
124
124
*/
125
125
for (i = 0; i < VGIC_NR_SGIS; i++) {
126
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, i);
126
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, i);
127
127
struct irq_desc *desc;
128
128
unsigned long flags;
129
129
int ret;
···
160
160
int i;
161
161
162
162
for (i = 0; i < VGIC_NR_SGIS; i++) {
163
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, i);
163
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, i);
164
164
struct irq_desc *desc;
165
165
unsigned long flags;
166
166
int ret;
+27
-16
arch/arm64/kvm/vgic/vgic.c
+27
-16
arch/arm64/kvm/vgic/vgic.c
···
84
84
* struct vgic_irq. It also increases the refcount, so any caller is expected
85
85
* to call vgic_put_irq() once it's finished with this IRQ.
86
86
*/
87
-
struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
88
-
u32 intid)
87
+
struct vgic_irq *vgic_get_irq(struct kvm *kvm, u32 intid)
89
88
{
90
-
/* SGIs and PPIs */
91
-
if (intid <= VGIC_MAX_PRIVATE) {
92
-
intid = array_index_nospec(intid, VGIC_MAX_PRIVATE + 1);
93
-
return &vcpu->arch.vgic_cpu.private_irqs[intid];
94
-
}
95
-
96
89
/* SPIs */
97
-
if (intid < (kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) {
90
+
if (intid >= VGIC_NR_PRIVATE_IRQS &&
91
+
intid < (kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) {
98
92
intid = array_index_nospec(intid, kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS);
99
93
return &kvm->arch.vgic.spis[intid - VGIC_NR_PRIVATE_IRQS];
100
94
}
···
98
104
return vgic_get_lpi(kvm, intid);
99
105
100
106
return NULL;
107
+
}
108
+
109
+
struct vgic_irq *vgic_get_vcpu_irq(struct kvm_vcpu *vcpu, u32 intid)
110
+
{
111
+
if (WARN_ON(!vcpu))
112
+
return NULL;
113
+
114
+
/* SGIs and PPIs */
115
+
if (intid < VGIC_NR_PRIVATE_IRQS) {
116
+
intid = array_index_nospec(intid, VGIC_NR_PRIVATE_IRQS);
117
+
return &vcpu->arch.vgic_cpu.private_irqs[intid];
118
+
}
119
+
120
+
return vgic_get_irq(vcpu->kvm, intid);
101
121
}
102
122
103
123
/*
···
445
437
446
438
trace_vgic_update_irq_pending(vcpu ? vcpu->vcpu_idx : 0, intid, level);
447
439
448
-
irq = vgic_get_irq(kvm, vcpu, intid);
440
+
if (intid < VGIC_NR_PRIVATE_IRQS)
441
+
irq = vgic_get_vcpu_irq(vcpu, intid);
442
+
else
443
+
irq = vgic_get_irq(kvm, intid);
449
444
if (!irq)
450
445
return -EINVAL;
451
446
···
510
499
int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq,
511
500
u32 vintid, struct irq_ops *ops)
512
501
{
513
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, vintid);
502
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, vintid);
514
503
unsigned long flags;
515
504
int ret;
516
505
···
535
524
*/
536
525
void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid)
537
526
{
538
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, vintid);
527
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, vintid);
539
528
unsigned long flags;
540
529
541
530
if (!irq->hw)
···
558
547
if (!vgic_initialized(vcpu->kvm))
559
548
return -EAGAIN;
560
549
561
-
irq = vgic_get_irq(vcpu->kvm, vcpu, vintid);
550
+
irq = vgic_get_vcpu_irq(vcpu, vintid);
562
551
BUG_ON(!irq);
563
552
564
553
raw_spin_lock_irqsave(&irq->irq_lock, flags);
···
571
560
572
561
int kvm_vgic_get_map(struct kvm_vcpu *vcpu, unsigned int vintid)
573
562
{
574
-
struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, vintid);
563
+
struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, vintid);
575
564
unsigned long flags;
576
565
int ret = -1;
577
566
···
607
596
if (!irq_is_ppi(intid) && !vgic_valid_spi(vcpu->kvm, intid))
608
597
return -EINVAL;
609
598
610
-
irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
599
+
irq = vgic_get_vcpu_irq(vcpu, intid);
611
600
raw_spin_lock_irqsave(&irq->irq_lock, flags);
612
601
if (irq->owner && irq->owner != owner)
613
602
ret = -EEXIST;
···
1019
1008
if (!vgic_initialized(vcpu->kvm))
1020
1009
return false;
1021
1010
1022
-
irq = vgic_get_irq(vcpu->kvm, vcpu, vintid);
1011
+
irq = vgic_get_vcpu_irq(vcpu, vintid);
1023
1012
raw_spin_lock_irqsave(&irq->irq_lock, flags);
1024
1013
map_is_active = irq->hw && irq->active;
1025
1014
raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
+2
-25
arch/arm64/kvm/vgic/vgic.h
+2
-25
arch/arm64/kvm/vgic/vgic.h
···
146
146
return ret;
147
147
}
148
148
149
-
static inline int vgic_its_read_entry_lock(struct vgic_its *its, gpa_t eaddr,
150
-
u64 *eval, unsigned long esize)
151
-
{
152
-
struct kvm *kvm = its->dev->kvm;
153
-
154
-
if (KVM_BUG_ON(esize != sizeof(*eval), kvm))
155
-
return -EINVAL;
156
-
157
-
return kvm_read_guest_lock(kvm, eaddr, eval, esize);
158
-
159
-
}
160
-
161
-
static inline int vgic_its_write_entry_lock(struct vgic_its *its, gpa_t eaddr,
162
-
u64 eval, unsigned long esize)
163
-
{
164
-
struct kvm *kvm = its->dev->kvm;
165
-
166
-
if (KVM_BUG_ON(esize != sizeof(eval), kvm))
167
-
return -EINVAL;
168
-
169
-
return vgic_write_guest_lock(kvm, eaddr, &eval, esize);
170
-
}
171
-
172
149
/*
173
150
* This struct provides an intermediate representation of the fields contained
174
151
* in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
···
179
202
const struct vgic_register_region *
180
203
vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
181
204
gpa_t addr, int len);
182
-
struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
183
-
u32 intid);
205
+
struct vgic_irq *vgic_get_irq(struct kvm *kvm, u32 intid);
206
+
struct vgic_irq *vgic_get_vcpu_irq(struct kvm_vcpu *vcpu, u32 intid);
184
207
void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
185
208
bool vgic_get_phys_line_level(struct vgic_irq *irq);
186
209
void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending);
+1
arch/riscv/Kconfig
+1
arch/riscv/Kconfig
+1
arch/riscv/include/asm/csr.h
+1
arch/riscv/include/asm/csr.h
···
199
199
/* xENVCFG flags */
200
200
#define ENVCFG_STCE (_AC(1, ULL) << 63)
201
201
#define ENVCFG_PBMTE (_AC(1, ULL) << 62)
202
+
#define ENVCFG_ADUE (_AC(1, ULL) << 61)
202
203
#define ENVCFG_PMM (_AC(0x3, ULL) << 32)
203
204
#define ENVCFG_PMM_PMLEN_0 (_AC(0x0, ULL) << 32)
204
205
#define ENVCFG_PMM_PMLEN_7 (_AC(0x2, ULL) << 32)
+2
arch/riscv/include/asm/hwcap.h
+2
arch/riscv/include/asm/hwcap.h
+12
-1
arch/riscv/include/asm/pgtable.h
+12
-1
arch/riscv/include/asm/pgtable.h
···
113
113
#include <asm/tlbflush.h>
114
114
#include <linux/mm_types.h>
115
115
#include <asm/compat.h>
116
+
#include <asm/cpufeature.h>
116
117
117
118
#define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT)
118
119
···
285
284
}
286
285
287
286
#ifdef CONFIG_RISCV_ISA_SVNAPOT
288
-
#include <asm/cpufeature.h>
289
287
290
288
static __always_inline bool has_svnapot(void)
291
289
{
···
653
653
prot |= _PAGE_NOCACHE;
654
654
655
655
return __pgprot(prot);
656
+
}
657
+
658
+
/*
659
+
* Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By
660
+
* default the M-mode firmware enables the hardware updating scheme when only Svadu is present in
661
+
* DT.
662
+
*/
663
+
#define arch_has_hw_pte_young arch_has_hw_pte_young
664
+
static inline bool arch_has_hw_pte_young(void)
665
+
{
666
+
return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU);
656
667
}
657
668
658
669
/*
+2
arch/riscv/include/uapi/asm/kvm.h
+2
arch/riscv/include/uapi/asm/kvm.h
+12
arch/riscv/kernel/cpufeature.c
+12
arch/riscv/kernel/cpufeature.c
···
136
136
return -EPROBE_DEFER;
137
137
}
138
138
139
+
static int riscv_ext_svadu_validate(const struct riscv_isa_ext_data *data,
140
+
const unsigned long *isa_bitmap)
141
+
{
142
+
/* SVADE has already been detected, use SVADE only */
143
+
if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SVADE))
144
+
return -EOPNOTSUPP;
145
+
146
+
return 0;
147
+
}
148
+
139
149
static const unsigned int riscv_zk_bundled_exts[] = {
140
150
RISCV_ISA_EXT_ZBKB,
141
151
RISCV_ISA_EXT_ZBKC,
···
397
387
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
398
388
__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts),
399
389
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
390
+
__RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE),
391
+
__RISCV_ISA_EXT_DATA_VALIDATE(svadu, RISCV_ISA_EXT_SVADU, riscv_ext_svadu_validate),
400
392
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
401
393
__RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT),
402
394
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
+4
arch/riscv/kvm/vcpu.c
+4
arch/riscv/kvm/vcpu.c
···
551
551
if (riscv_isa_extension_available(isa, ZICBOZ))
552
552
cfg->henvcfg |= ENVCFG_CBZE;
553
553
554
+
if (riscv_isa_extension_available(isa, SVADU) &&
555
+
!riscv_isa_extension_available(isa, SVADE))
556
+
cfg->henvcfg |= ENVCFG_ADUE;
557
+
554
558
if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
555
559
cfg->hstateen0 |= SMSTATEEN0_HSENVCFG;
556
560
if (riscv_isa_extension_available(isa, SSAIA))
+15
arch/riscv/kvm/vcpu_onereg.c
+15
arch/riscv/kvm/vcpu_onereg.c
···
15
15
#include <asm/cacheflush.h>
16
16
#include <asm/cpufeature.h>
17
17
#include <asm/kvm_vcpu_vector.h>
18
+
#include <asm/pgtable.h>
18
19
#include <asm/vector.h>
19
20
20
21
#define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0)
···
41
40
KVM_ISA_EXT_ARR(SSCOFPMF),
42
41
KVM_ISA_EXT_ARR(SSNPM),
43
42
KVM_ISA_EXT_ARR(SSTC),
43
+
KVM_ISA_EXT_ARR(SVADE),
44
+
KVM_ISA_EXT_ARR(SVADU),
44
45
KVM_ISA_EXT_ARR(SVINVAL),
45
46
KVM_ISA_EXT_ARR(SVNAPOT),
46
47
KVM_ISA_EXT_ARR(SVPBMT),
···
115
112
case KVM_RISCV_ISA_EXT_SSCOFPMF:
116
113
/* Sscofpmf depends on interrupt filtering defined in ssaia */
117
114
return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA);
115
+
case KVM_RISCV_ISA_EXT_SVADU:
116
+
/*
117
+
* The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
118
+
* Guest OS can use Svadu only when host OS enable Svadu.
119
+
*/
120
+
return arch_has_hw_pte_young();
118
121
case KVM_RISCV_ISA_EXT_V:
119
122
return riscv_v_vstate_ctrl_user_allowed();
120
123
default:
···
194
185
/* Extensions which can be disabled using Smstateen */
195
186
case KVM_RISCV_ISA_EXT_SSAIA:
196
187
return riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN);
188
+
case KVM_RISCV_ISA_EXT_SVADE:
189
+
/*
190
+
* The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
191
+
* Svade is not allowed to disable when the platform use Svade.
192
+
*/
193
+
return arch_has_hw_pte_young();
197
194
default:
198
195
break;
199
196
}
-1
include/kvm/arm_vgic.h
-1
include/kvm/arm_vgic.h
+8
tools/testing/selftests/kvm/riscv/get-reg-list.c
+8
tools/testing/selftests/kvm/riscv/get-reg-list.c
···
47
47
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF:
48
48
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSNPM:
49
49
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC:
50
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADE:
51
+
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU:
50
52
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL:
51
53
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT:
52
54
case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:
···
424
422
KVM_ISA_EXT_ARR(SSCOFPMF),
425
423
KVM_ISA_EXT_ARR(SSNPM),
426
424
KVM_ISA_EXT_ARR(SSTC),
425
+
KVM_ISA_EXT_ARR(SVADE),
426
+
KVM_ISA_EXT_ARR(SVADU),
427
427
KVM_ISA_EXT_ARR(SVINVAL),
428
428
KVM_ISA_EXT_ARR(SVNAPOT),
429
429
KVM_ISA_EXT_ARR(SVPBMT),
···
959
955
KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF);
960
956
KVM_ISA_EXT_SIMPLE_CONFIG(ssnpm, SSNPM);
961
957
KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC);
958
+
KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE);
959
+
KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU);
962
960
KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);
963
961
KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);
964
962
KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
···
1026
1020
&config_sscofpmf,
1027
1021
&config_ssnpm,
1028
1022
&config_sstc,
1023
+
&config_svade,
1024
+
&config_svadu,
1029
1025
&config_svinval,
1030
1026
&config_svnapot,
1031
1027
&config_svpbmt,