Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: mediatek: mt7986: add common header
Add header files for register definition and structure.
Signed-off-by: Maso Huang <maso.huang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230817101338.18782-2-maso.huang@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Maso Huang
and committed by
Mark Brown
c4c3c32d
17b9f438
+245
+49
sound/soc/mediatek/mt7986/mt7986-afe-common.h
+49
sound/soc/mediatek/mt7986/mt7986-afe-common.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* mt7986-afe-common.h -- MediaTek 7986 audio driver definitions
4
+
*
5
+
* Copyright (c) 2023 MediaTek Inc.
6
+
* Authors: Vic Wu <vic.wu@mediatek.com>
7
+
* Maso Huang <maso.huang@mediatek.com>
8
+
*/
9
+
10
+
#ifndef _MT_7986_AFE_COMMON_H_
11
+
#define _MT_7986_AFE_COMMON_H_
12
+
13
+
#include <sound/soc.h>
14
+
#include <linux/clk.h>
15
+
#include <linux/list.h>
16
+
#include <linux/regmap.h>
17
+
#include "../common/mtk-base-afe.h"
18
+
19
+
enum {
20
+
MT7986_MEMIF_DL1,
21
+
MT7986_MEMIF_VUL12,
22
+
MT7986_MEMIF_NUM,
23
+
MT7986_DAI_ETDM = MT7986_MEMIF_NUM,
24
+
MT7986_DAI_NUM,
25
+
};
26
+
27
+
enum {
28
+
MT7986_IRQ_0,
29
+
MT7986_IRQ_1,
30
+
MT7986_IRQ_2,
31
+
MT7986_IRQ_NUM,
32
+
};
33
+
34
+
struct mt7986_afe_private {
35
+
struct clk_bulk_data *clks;
36
+
int num_clks;
37
+
38
+
int pm_runtime_bypass_reg_ctl;
39
+
40
+
/* dai */
41
+
void *dai_priv[MT7986_DAI_NUM];
42
+
};
43
+
44
+
unsigned int mt7986_afe_rate_transform(struct device *dev,
45
+
unsigned int rate);
46
+
47
+
/* dai register */
48
+
int mt7986_dai_etdm_register(struct mtk_base_afe *afe);
49
+
#endif
+196
sound/soc/mediatek/mt7986/mt7986-reg.h
+196
sound/soc/mediatek/mt7986/mt7986-reg.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* mt7986-reg.h -- MediaTek 7986 audio driver reg definition
4
+
*
5
+
* Copyright (c) 2023 MediaTek Inc.
6
+
* Authors: Vic Wu <vic.wu@mediatek.com>
7
+
* Maso Huang <maso.huang@mediatek.com>
8
+
*/
9
+
10
+
#ifndef _MT7986_REG_H_
11
+
#define _MT7986_REG_H_
12
+
13
+
#define AUDIO_TOP_CON2 0x0008
14
+
#define AUDIO_TOP_CON4 0x0010
15
+
#define AUDIO_ENGEN_CON0 0x0014
16
+
#define AFE_IRQ_MCU_EN 0x0100
17
+
#define AFE_IRQ_MCU_STATUS 0x0120
18
+
#define AFE_IRQ_MCU_CLR 0x0128
19
+
#define AFE_IRQ0_MCU_CFG0 0x0140
20
+
#define AFE_IRQ0_MCU_CFG1 0x0144
21
+
#define AFE_IRQ1_MCU_CFG0 0x0148
22
+
#define AFE_IRQ1_MCU_CFG1 0x014c
23
+
#define AFE_IRQ2_MCU_CFG0 0x0150
24
+
#define AFE_IRQ2_MCU_CFG1 0x0154
25
+
#define ETDM_IN5_CON0 0x13f0
26
+
#define ETDM_IN5_CON1 0x13f4
27
+
#define ETDM_IN5_CON2 0x13f8
28
+
#define ETDM_IN5_CON3 0x13fc
29
+
#define ETDM_IN5_CON4 0x1400
30
+
#define ETDM_OUT5_CON0 0x1570
31
+
#define ETDM_OUT5_CON4 0x1580
32
+
#define ETDM_OUT5_CON5 0x1584
33
+
#define ETDM_4_7_COWORK_CON0 0x15e0
34
+
#define ETDM_4_7_COWORK_CON1 0x15e4
35
+
#define AFE_CONN018_1 0x1b44
36
+
#define AFE_CONN018_4 0x1b50
37
+
#define AFE_CONN019_1 0x1b64
38
+
#define AFE_CONN019_4 0x1b70
39
+
#define AFE_CONN124_1 0x2884
40
+
#define AFE_CONN124_4 0x2890
41
+
#define AFE_CONN125_1 0x28a4
42
+
#define AFE_CONN125_4 0x28b0
43
+
#define AFE_CONN_RS_0 0x3920
44
+
#define AFE_CONN_RS_3 0x392c
45
+
#define AFE_CONN_16BIT_0 0x3960
46
+
#define AFE_CONN_16BIT_3 0x396c
47
+
#define AFE_CONN_24BIT_0 0x3980
48
+
#define AFE_CONN_24BIT_3 0x398c
49
+
#define AFE_MEMIF_CON0 0x3d98
50
+
#define AFE_MEMIF_RD_MON 0x3da0
51
+
#define AFE_MEMIF_WR_MON 0x3da4
52
+
#define AFE_DL0_BASE_MSB 0x3e40
53
+
#define AFE_DL0_BASE 0x3e44
54
+
#define AFE_DL0_CUR_MSB 0x3e48
55
+
#define AFE_DL0_CUR 0x3e4c
56
+
#define AFE_DL0_END_MSB 0x3e50
57
+
#define AFE_DL0_END 0x3e54
58
+
#define AFE_DL0_RCH_MON 0x3e58
59
+
#define AFE_DL0_LCH_MON 0x3e5c
60
+
#define AFE_DL0_CON0 0x3e60
61
+
#define AFE_VUL0_BASE_MSB 0x4220
62
+
#define AFE_VUL0_BASE 0x4224
63
+
#define AFE_VUL0_CUR_MSB 0x4228
64
+
#define AFE_VUL0_CUR 0x422c
65
+
#define AFE_VUL0_END_MSB 0x4230
66
+
#define AFE_VUL0_END 0x4234
67
+
#define AFE_VUL0_CON0 0x4238
68
+
69
+
#define AFE_MAX_REGISTER AFE_VUL0_CON0
70
+
#define AFE_IRQ_STATUS_BITS 0x7
71
+
#define AFE_IRQ_CNT_SHIFT 0
72
+
#define AFE_IRQ_CNT_MASK 0xffffff
73
+
74
+
/* AUDIO_TOP_CON2 */
75
+
#define CLK_OUT5_PDN BIT(14)
76
+
#define CLK_OUT5_PDN_MASK BIT(14)
77
+
#define CLK_IN5_PDN BIT(7)
78
+
#define CLK_IN5_PDN_MASK BIT(7)
79
+
80
+
/* AUDIO_TOP_CON4 */
81
+
#define PDN_APLL_TUNER2 BIT(12)
82
+
#define PDN_APLL_TUNER2_MASK BIT(12)
83
+
84
+
/* AUDIO_ENGEN_CON0 */
85
+
#define AUD_APLL2_EN BIT(3)
86
+
#define AUD_APLL2_EN_MASK BIT(3)
87
+
#define AUD_26M_EN BIT(0)
88
+
#define AUD_26M_EN_MASK BIT(0)
89
+
90
+
/* AFE_DL0_CON0 */
91
+
#define DL0_ON_SFT 28
92
+
#define DL0_ON_MASK 0x1
93
+
#define DL0_ON_MASK_SFT BIT(28)
94
+
#define DL0_MINLEN_SFT 20
95
+
#define DL0_MINLEN_MASK 0xf
96
+
#define DL0_MINLEN_MASK_SFT (0xf << 20)
97
+
#define DL0_MODE_SFT 8
98
+
#define DL0_MODE_MASK 0x1f
99
+
#define DL0_MODE_MASK_SFT (0x1f << 8)
100
+
#define DL0_PBUF_SIZE_SFT 5
101
+
#define DL0_PBUF_SIZE_MASK 0x3
102
+
#define DL0_PBUF_SIZE_MASK_SFT (0x3 << 5)
103
+
#define DL0_MONO_SFT 4
104
+
#define DL0_MONO_MASK 0x1
105
+
#define DL0_MONO_MASK_SFT BIT(4)
106
+
#define DL0_HALIGN_SFT 2
107
+
#define DL0_HALIGN_MASK 0x1
108
+
#define DL0_HALIGN_MASK_SFT BIT(2)
109
+
#define DL0_HD_MODE_SFT 0
110
+
#define DL0_HD_MODE_MASK 0x3
111
+
#define DL0_HD_MODE_MASK_SFT (0x3 << 0)
112
+
113
+
/* AFE_VUL0_CON0 */
114
+
#define VUL0_ON_SFT 28
115
+
#define VUL0_ON_MASK 0x1
116
+
#define VUL0_ON_MASK_SFT BIT(28)
117
+
#define VUL0_MODE_SFT 8
118
+
#define VUL0_MODE_MASK 0x1f
119
+
#define VUL0_MODE_MASK_SFT (0x1f << 8)
120
+
#define VUL0_MONO_SFT 4
121
+
#define VUL0_MONO_MASK 0x1
122
+
#define VUL0_MONO_MASK_SFT BIT(4)
123
+
#define VUL0_HALIGN_SFT 2
124
+
#define VUL0_HALIGN_MASK 0x1
125
+
#define VUL0_HALIGN_MASK_SFT BIT(2)
126
+
#define VUL0_HD_MODE_SFT 0
127
+
#define VUL0_HD_MODE_MASK 0x3
128
+
#define VUL0_HD_MODE_MASK_SFT (0x3 << 0)
129
+
130
+
/* AFE_IRQ_MCU_CON */
131
+
#define IRQ_MCU_MODE_SFT 4
132
+
#define IRQ_MCU_MODE_MASK 0x1f
133
+
#define IRQ_MCU_MODE_MASK_SFT (0x1f << 4)
134
+
#define IRQ_MCU_ON_SFT 0
135
+
#define IRQ_MCU_ON_MASK 0x1
136
+
#define IRQ_MCU_ON_MASK_SFT BIT(0)
137
+
#define IRQ0_MCU_CLR_SFT 0
138
+
#define IRQ0_MCU_CLR_MASK 0x1
139
+
#define IRQ0_MCU_CLR_MASK_SFT BIT(0)
140
+
#define IRQ1_MCU_CLR_SFT 1
141
+
#define IRQ1_MCU_CLR_MASK 0x1
142
+
#define IRQ1_MCU_CLR_MASK_SFT BIT(1)
143
+
#define IRQ2_MCU_CLR_SFT 2
144
+
#define IRQ2_MCU_CLR_MASK 0x1
145
+
#define IRQ2_MCU_CLR_MASK_SFT BIT(2)
146
+
147
+
/* ETDM_IN5_CON2 */
148
+
#define IN_CLK_SRC(x) ((x) << 10)
149
+
#define IN_CLK_SRC_SFT 10
150
+
#define IN_CLK_SRC_MASK GENMASK(12, 10)
151
+
152
+
/* ETDM_IN5_CON3 */
153
+
#define IN_SEL_FS(x) ((x) << 26)
154
+
#define IN_SEL_FS_SFT 26
155
+
#define IN_SEL_FS_MASK GENMASK(30, 26)
156
+
157
+
/* ETDM_IN5_CON4 */
158
+
#define IN_RELATCH(x) ((x) << 20)
159
+
#define IN_RELATCH_SFT 20
160
+
#define IN_RELATCH_MASK GENMASK(24, 20)
161
+
#define IN_CLK_INV BIT(18)
162
+
#define IN_CLK_INV_MASK BIT(18)
163
+
164
+
/* ETDM_IN5_CON0 & ETDM_OUT5_CON0 */
165
+
#define RELATCH_SRC_MASK GENMASK(30, 28)
166
+
#define ETDM_CH_NUM_MASK GENMASK(27, 23)
167
+
#define ETDM_WRD_LEN_MASK GENMASK(20, 16)
168
+
#define ETDM_BIT_LEN_MASK GENMASK(15, 11)
169
+
#define ETDM_FMT_MASK GENMASK(8, 6)
170
+
#define ETDM_SYNC BIT(1)
171
+
#define ETDM_SYNC_MASK BIT(1)
172
+
#define ETDM_EN BIT(0)
173
+
#define ETDM_EN_MASK BIT(0)
174
+
175
+
/* ETDM_OUT5_CON4 */
176
+
#define OUT_RELATCH(x) ((x) << 24)
177
+
#define OUT_RELATCH_SFT 24
178
+
#define OUT_RELATCH_MASK GENMASK(28, 24)
179
+
#define OUT_CLK_SRC(x) ((x) << 6)
180
+
#define OUT_CLK_SRC_SFT 6
181
+
#define OUT_CLK_SRC_MASK GENMASK(8, 6)
182
+
#define OUT_SEL_FS(x) (x)
183
+
#define OUT_SEL_FS_SFT 0
184
+
#define OUT_SEL_FS_MASK GENMASK(4, 0)
185
+
186
+
/* ETDM_OUT5_CON5 */
187
+
#define ETDM_CLK_DIV BIT(12)
188
+
#define ETDM_CLK_DIV_MASK BIT(12)
189
+
#define OUT_CLK_INV BIT(9)
190
+
#define OUT_CLK_INV_MASK BIT(9)
191
+
192
+
/* ETDM_4_7_COWORK_CON0 */
193
+
#define OUT_SEL(x) ((x) << 12)
194
+
#define OUT_SEL_SFT 12
195
+
#define OUT_SEL_MASK GENMASK(15, 12)
196
+
#endif