Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pinctrl-v3.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pinctrl fixes from Linus Walleij:
"Allright allright I've been lazy over christmas and New Years. Here
are a few collected pin control fixes eventually. Details:
A set of assorted pin control fixes for the Rockchip and STi drivers"
* tag 'pinctrl-v3.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: st: Add irq_disable hook to st_gpio_irqchip
pinctrl: st: avoid multiple mutex lock
pinctrl: rockchip: Fix enable/disable/mask/unmask
pinctrl: rockchip: Handle wakeup pins
+58
-4
+54
-3
drivers/pinctrl/pinctrl-rockchip.c
+54
-3
drivers/pinctrl/pinctrl-rockchip.c
···
89
89
* @reg_pull: optional separate register for additional pull settings
90
90
* @clk: clock of the gpio bank
91
91
* @irq: interrupt of the gpio bank
92
+
* @saved_enables: Saved content of GPIO_INTEN at suspend time.
92
93
* @pin_base: first pin number
93
94
* @nr_pins: number of pins in this bank
94
95
* @name: name of the bank
···
108
107
struct regmap *regmap_pull;
109
108
struct clk *clk;
110
109
int irq;
110
+
u32 saved_enables;
111
111
u32 pin_base;
112
112
u8 nr_pins;
113
113
char *name;
···
1545
1543
return 0;
1546
1544
}
1547
1545
1546
+
static void rockchip_irq_suspend(struct irq_data *d)
1547
+
{
1548
+
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1549
+
struct rockchip_pin_bank *bank = gc->private;
1550
+
1551
+
bank->saved_enables = irq_reg_readl(gc, GPIO_INTEN);
1552
+
irq_reg_writel(gc, gc->wake_active, GPIO_INTEN);
1553
+
}
1554
+
1555
+
static void rockchip_irq_resume(struct irq_data *d)
1556
+
{
1557
+
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1558
+
struct rockchip_pin_bank *bank = gc->private;
1559
+
1560
+
irq_reg_writel(gc, bank->saved_enables, GPIO_INTEN);
1561
+
}
1562
+
1563
+
static void rockchip_irq_disable(struct irq_data *d)
1564
+
{
1565
+
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1566
+
u32 val;
1567
+
1568
+
irq_gc_lock(gc);
1569
+
1570
+
val = irq_reg_readl(gc, GPIO_INTEN);
1571
+
val &= ~d->mask;
1572
+
irq_reg_writel(gc, val, GPIO_INTEN);
1573
+
1574
+
irq_gc_unlock(gc);
1575
+
}
1576
+
1577
+
static void rockchip_irq_enable(struct irq_data *d)
1578
+
{
1579
+
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1580
+
u32 val;
1581
+
1582
+
irq_gc_lock(gc);
1583
+
1584
+
val = irq_reg_readl(gc, GPIO_INTEN);
1585
+
val |= d->mask;
1586
+
irq_reg_writel(gc, val, GPIO_INTEN);
1587
+
1588
+
irq_gc_unlock(gc);
1589
+
}
1590
+
1548
1591
static int rockchip_interrupts_register(struct platform_device *pdev,
1549
1592
struct rockchip_pinctrl *info)
1550
1593
{
···
1628
1581
gc = irq_get_domain_generic_chip(bank->domain, 0);
1629
1582
gc->reg_base = bank->reg_base;
1630
1583
gc->private = bank;
1631
-
gc->chip_types[0].regs.mask = GPIO_INTEN;
1584
+
gc->chip_types[0].regs.mask = GPIO_INTMASK;
1632
1585
gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1633
1586
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1634
-
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1635
-
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1587
+
gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
1588
+
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
1589
+
gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
1590
+
gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
1636
1591
gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1592
+
gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
1593
+
gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
1637
1594
gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1638
1595
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
1639
1596
+4
-1
drivers/pinctrl/pinctrl-st.c
+4
-1
drivers/pinctrl/pinctrl-st.c
···
1012
1012
struct seq_file *s, unsigned pin_id)
1013
1013
{
1014
1014
unsigned long config;
1015
-
st_pinconf_get(pctldev, pin_id, &config);
1016
1015
1016
+
mutex_unlock(&pctldev->mutex);
1017
+
st_pinconf_get(pctldev, pin_id, &config);
1018
+
mutex_lock(&pctldev->mutex);
1017
1019
seq_printf(s, "[OE:%ld,PU:%ld,OD:%ld]\n"
1018
1020
"\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
1019
1021
"de:%ld,rt-clk:%ld,rt-delay:%ld]",
···
1445
1443
1446
1444
static struct irq_chip st_gpio_irqchip = {
1447
1445
.name = "GPIO",
1446
+
.irq_disable = st_gpio_irq_mask,
1448
1447
.irq_mask = st_gpio_irq_mask,
1449
1448
.irq_unmask = st_gpio_irq_unmask,
1450
1449
.irq_set_type = st_gpio_irq_set_type,