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RDMA/mlx5: Fix UMR modifying of mkey page size

When changing the page size on an mkey, the driver needs to set the
appropriate bits in the mkey mask to indicate which fields are being
modified.
The 6th bit of a page size in mlx5 driver is considered an extension,
and this bit has a dedicated capability and mask bits.

Previously, the driver was not setting this mask in the mkey mask when
performing page size changes, regardless of its hardware support,
potentially leading to an incorrect page size updates.

This fixes the issue by setting the relevant bit in the mkey mask when
performing page size changes on an mkey and the 6th bit of this field is
supported by the hardware.

Fixes: cef7dde8836a ("net/mlx5: Expand mkey page size to support 6 bits")
Signed-off-by: Edward Srouji <edwards@nvidia.com>
Reviewed-by: Michael Guralnik <michaelgur@nvidia.com>
Link: https://patch.msgid.link/9f43a9c73bf2db6085a99dc836f7137e76579f09.1751979184.git.leon@kernel.org
Signed-off-by: Leon Romanovsky <leon@kernel.org>

authored by

Edward Srouji and committed by
Leon Romanovsky c4f96972 8feaf983

+5 -2
+4 -2
drivers/infiniband/hw/mlx5/umr.c
··· 32 32 return cpu_to_be64(result); 33 33 } 34 34 35 - static __be64 get_umr_update_translation_mask(void) 35 + static __be64 get_umr_update_translation_mask(struct mlx5_ib_dev *dev) 36 36 { 37 37 u64 result; 38 38 39 39 result = MLX5_MKEY_MASK_LEN | 40 40 MLX5_MKEY_MASK_PAGE_SIZE | 41 41 MLX5_MKEY_MASK_START_ADDR; 42 + if (MLX5_CAP_GEN_2(dev->mdev, umr_log_entity_size_5)) 43 + result |= MLX5_MKEY_MASK_PAGE_SIZE_5; 42 44 43 45 return cpu_to_be64(result); 44 46 } ··· 656 654 flags & MLX5_IB_UPD_XLT_ENABLE || flags & MLX5_IB_UPD_XLT_ADDR; 657 655 658 656 if (update_translation) { 659 - wqe->ctrl_seg.mkey_mask |= get_umr_update_translation_mask(); 657 + wqe->ctrl_seg.mkey_mask |= get_umr_update_translation_mask(dev); 660 658 if (!mr->ibmr.length) 661 659 MLX5_SET(mkc, &wqe->mkey_seg, length64, 1); 662 660 }
+1
include/linux/mlx5/device.h
··· 280 280 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 281 281 MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25, 282 282 MLX5_MKEY_MASK_FREE = 1ull << 29, 283 + MLX5_MKEY_MASK_PAGE_SIZE_5 = 1ull << 42, 283 284 MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47, 284 285 }; 285 286