Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB
Add the match data for the pinctrl found in the EyeQ6Lplus OLB. The pin
control is identical in function to the one present in the EyeQ5 but
has a single bank of 32 pins.
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
authored by
Benoît Monin
and committed by
Thomas Bogendoerfer
c4fc0fb9
7cfa9474
+97
-2
+2
-2
drivers/pinctrl/Kconfig
+2
-2
drivers/pinctrl/Kconfig
···
254
254
config PINCTRL_EYEQ5
255
255
bool "Mobileye EyeQ5 pinctrl driver"
256
256
depends on OF
257
-
depends on MACH_EYEQ5 || COMPILE_TEST
257
+
depends on MACH_EYEQ5 || MACH_EYEQ6LPLUS || COMPILE_TEST
258
258
select PINMUX
259
259
select GENERIC_PINCONF
260
260
select AUXILIARY_BUS
261
-
default MACH_EYEQ5
261
+
default MACH_EYEQ5 || MACH_EYEQ6LPLUS
262
262
help
263
263
Pin controller driver for the Mobileye EyeQ5 platform. It does both
264
264
pin config & pin muxing. It does not handle GPIO.
+95
drivers/pinctrl/pinctrl-eyeq5.c
+95
drivers/pinctrl/pinctrl-eyeq5.c
···
229
229
.banks = eq5p_eyeq5_banks,
230
230
};
231
231
232
+
static const struct pinctrl_pin_desc eq5p_eyeq6lplus_pins[] = {
233
+
PINCTRL_PIN(0, "PA0"), /* GPIO_A0_TIMER0_CK0 */
234
+
PINCTRL_PIN(1, "PA1"), /* GPIO_A1_TIMER0_EOC */
235
+
PINCTRL_PIN(2, "PA2"), /* GPIO_A2_TIMER1_CK */
236
+
PINCTRL_PIN(3, "PA3"), /* GPIO_A3_TIMER1_EOC1 */
237
+
PINCTRL_PIN(4, "PA4"), /* GPIO_A4_SSI_UART_RX */
238
+
PINCTRL_PIN(5, "PA5"), /* GPIO_A5_SSI_UART_TX */
239
+
PINCTRL_PIN(6, "PA6"), /* GPIO_A6_SPI_0_CS */
240
+
PINCTRL_PIN(7, "PA7"), /* GPIO_A7_SPI_0_DI */
241
+
PINCTRL_PIN(8, "PA8"), /* GPIO_A8_SPI_0_CK */
242
+
PINCTRL_PIN(9, "PA9"), /* GPIO_A9_SPI_0_DO */
243
+
PINCTRL_PIN(10, "PA10"), /* GPIO_A10_SPI_0_CS1 */
244
+
PINCTRL_PIN(11, "PA11"), /* GPIO_A11_UART_0_RX */
245
+
PINCTRL_PIN(12, "PA12"), /* GPIO_A12_UART_0_TX */
246
+
PINCTRL_PIN(13, "PA13"), /* GPIO_A13_TIMER2_CK */
247
+
PINCTRL_PIN(14, "PA14"), /* GPIO_A14_TIMER2_EOC */
248
+
PINCTRL_PIN(15, "PA15"), /* GPIO_A15_TIMER3_CK */
249
+
PINCTRL_PIN(16, "PA16"), /* GPIO_A16_TIMER_EOC */
250
+
PINCTRL_PIN(17, "PA17"), /* GPIO_A17_TIMER_EXT0_INCA P1 */
251
+
PINCTRL_PIN(18, "PA18"), /* GPIO_A18_TIMER_EXT0_INCA P2 */
252
+
PINCTRL_PIN(19, "PA19"), /* GPIO_A19_TIMER_EXT0_OUT CMP1 */
253
+
PINCTRL_PIN(20, "PA20"), /* GPIO_A20_TIMER_EXT0_OUT CMP2 */
254
+
PINCTRL_PIN(21, "PA21"), /* GPIO_A21_SPI_1_CS0 */
255
+
PINCTRL_PIN(22, "PA22"), /* GPIO_A22_SPI_1_DI */
256
+
PINCTRL_PIN(23, "PA23"), /* GPIO_A23_SPI_1_CK */
257
+
PINCTRL_PIN(24, "PA24"), /* GPIO_A24_SPI_1_DO */
258
+
PINCTRL_PIN(25, "PA25"), /* GPIO_A25_SPI_1_CS1 */
259
+
PINCTRL_PIN(26, "PA26"), /* GPIO_A26_TIMER_EXT1_INCA P1 */
260
+
PINCTRL_PIN(27, "PA27"), /* GPIO_A27_TIMER_EXT1_INCA P2 */
261
+
PINCTRL_PIN(28, "PA28"), /* GPIO_A28_TIMER_EXT1_OUTC MP1 */
262
+
PINCTRL_PIN(29, "PA29"), /* GPIO_A29_TIMER_EXT1_OUTC MP2 */
263
+
PINCTRL_PIN(30, "PA30"), /* GPIO_A30_EXT_CLK */
264
+
PINCTRL_PIN(31, "PA31"), /* GPIO_A31_VDI_MCLK */
265
+
};
266
+
267
+
static const char * const eq5p_eyeq6lplus_gpio_groups[] = {
268
+
/* Bank A */
269
+
"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
270
+
"PA8", "PA9", "PA10", "PA11", "PA12", "PA13", "PA14", "PA15",
271
+
"PA16", "PA17", "PA18", "PA19", "PA20", "PA21", "PA22", "PA23",
272
+
"PA24", "PA25", "PA26", "PA27", "PA28", "PA29", "PA30", "PA31",
273
+
};
274
+
275
+
/* Groups of functions on bank A */
276
+
static const char * const eq5p_eyeq6lplus_timer0_groups[] = { "PA0", "PA1" };
277
+
static const char * const eq5p_eyeq6lplus_timer1_groups[] = { "PA2", "PA3" };
278
+
static const char * const eq5p_eyeq6lplus_uart_ssi_groups[] = { "PA4", "PA5" };
279
+
static const char * const eq5p_eyeq6lplus_spi0_groups[] = { "PA6", "PA7", "PA8", "PA9", "PA10" };
280
+
static const char * const eq5p_eyeq6lplus_uart0_groups[] = { "PA11", "PA12" };
281
+
static const char * const eq5p_eyeq6lplus_timer2_groups[] = { "PA13", "PA14" };
282
+
static const char * const eq5p_eyeq6lplus_timer3_groups[] = { "PA15", "PA16" };
283
+
static const char * const eq5p_eyeq6lplus_timer_ext0_groups[] = { "PA17", "PA18", "PA19", "PA20" };
284
+
static const char * const eq5p_eyeq6lplus_spi1_groups[] = {
285
+
"PA21", "PA22", "PA23", "PA24", "PA25"
286
+
};
287
+
static const char * const eq5p_eyeq6lplus_timer_ext1_groups[] = { "PA26", "PA27", "PA28", "PA29" };
288
+
static const char * const eq5p_eyeq6lplus_ext_ref_clk_groups[] = { "PA30" };
289
+
static const char * const eq5p_eyeq6lplus_mipi_ref_clk_groups[] = { "PA31" };
290
+
291
+
static const struct pinfunction eq5p_eyeq6lplus_functions[] = {
292
+
/* gpios function */
293
+
EQ5P_PINFUNCTION("gpio", eq5p_eyeq6lplus_gpio_groups),
294
+
295
+
/* Bank A alternate functions */
296
+
EQ5P_PINFUNCTION("timer0", eq5p_eyeq6lplus_timer0_groups),
297
+
EQ5P_PINFUNCTION("timer1", eq5p_eyeq6lplus_timer1_groups),
298
+
EQ5P_PINFUNCTION("uart_ssi", eq5p_eyeq6lplus_uart_ssi_groups),
299
+
EQ5P_PINFUNCTION("spi0", eq5p_eyeq6lplus_spi0_groups),
300
+
EQ5P_PINFUNCTION("uart0", eq5p_eyeq6lplus_uart0_groups),
301
+
EQ5P_PINFUNCTION("timer2", eq5p_eyeq6lplus_timer2_groups),
302
+
EQ5P_PINFUNCTION("timer3", eq5p_eyeq6lplus_timer3_groups),
303
+
EQ5P_PINFUNCTION("timer_ext0", eq5p_eyeq6lplus_timer_ext0_groups),
304
+
EQ5P_PINFUNCTION("spi1", eq5p_eyeq6lplus_spi1_groups),
305
+
EQ5P_PINFUNCTION("timer_ext1", eq5p_eyeq6lplus_timer_ext1_groups),
306
+
EQ5P_PINFUNCTION("ext_ref_clk", eq5p_eyeq6lplus_ext_ref_clk_groups),
307
+
EQ5P_PINFUNCTION("mipi_ref_clk", eq5p_eyeq6lplus_mipi_ref_clk_groups),
308
+
};
309
+
310
+
static const struct eq5p_bank eq5p_eyeq6lplus_banks[] = {
311
+
{
312
+
.npins = ARRAY_SIZE(eq5p_eyeq6lplus_pins),
313
+
.regs = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},
314
+
},
315
+
};
316
+
317
+
static const struct eq5p_match_data eq5p_eyeq6lplus_data = {
318
+
.npins = ARRAY_SIZE(eq5p_eyeq6lplus_pins),
319
+
.nfunctions = ARRAY_SIZE(eq5p_eyeq6lplus_functions),
320
+
.nbanks = ARRAY_SIZE(eq5p_eyeq6lplus_banks),
321
+
.pins = eq5p_eyeq6lplus_pins,
322
+
.functions = eq5p_eyeq6lplus_functions,
323
+
.banks = eq5p_eyeq6lplus_banks,
324
+
};
325
+
232
326
static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl,
233
327
const struct eq5p_bank *bank,
234
328
enum eq5p_regs reg, u32 mask, u32 val)
···
733
639
734
640
static const struct of_device_id eq5p_match_table[] = {
735
641
{ .compatible = "mobileye,eyeq5-olb", .data = &eq5p_eyeq5_data },
642
+
{ .compatible = "mobileye,eyeq6lplus-olb", .data = &eq5p_eyeq6lplus_data },
736
643
{}
737
644
};
738
645
MODULE_DEVICE_TABLE(of, eq5p_match_table);