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[PATCH] ppc32/8xx: Fix r3 trashing due to 8MB TLB page instantiation

Instantiation of 8MB pages on the TLB cache for the kernel static
mapping trashes r3 register on !CONFIG_8xx_CPU6 configurations.
This ensures r3 gets saved and restored.

Signed-off-by: Marcelo Tosatti <marcelo@kvack.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

authored by

Marcelo Tosatti and committed by
Paul Mackerras
c51e078f e4de0021

-4
-4
arch/ppc/kernel/head_8xx.S
··· 355 355 356 356 . = 0x1200 357 357 DataStoreTLBMiss: 358 - #ifdef CONFIG_8xx_CPU6 359 358 stw r3, 8(r0) 360 - #endif 361 359 DO_8xx_CPU6(0x3f80, r3) 362 360 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 363 361 mfcr r10 ··· 415 417 lwz r11, 0(r0) 416 418 mtcr r11 417 419 lwz r11, 4(r0) 418 - #ifdef CONFIG_8xx_CPU6 419 420 lwz r3, 8(r0) 420 - #endif 421 421 rfi 422 422 423 423 /* This is an instruction TLB error on the MPC8xx. This could be due