Merge tag 'riscv-for-v5.2/fixes-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Paul Walmsley:
"Minor RISC-V fixes and one defconfig update.

The fixes have no functional impact:

- Fix some comment text in the memory management vmalloc_fault path.

- Fix some warnings from the DT compiler in our newly-added DT files.

- Change the newly-added DT bindings such that SoC IP blocks with
external I/O are marked as "disabled" by default, then enable them
explicitly in board DT files when the devices are used on the
board. This aligns the bindings with existing upstream practice.

- Add the MIT license as an option for a minor header file, at the
request of one of the U-Boot maintainers.

The RISC-V defconfig update builds the SiFive SPI driver and the
MMC-SPI driver by default. The intention here is to make v5.2 more
usable for testers and users with RISC-V hardware"

* tag 'riscv-for-v5.2/fixes-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: mm: Fix code comment
dt-bindings: clock: sifive: add MIT license as an option for the header file
dt-bindings: riscv: resolve 'make dt_binding_check' warnings
riscv: dts: Re-organize the DT nodes
RISC-V: defconfig: enable MMC & SPI for RISC-V

Linus Torvalds 7 years ago c57582ad c949c30b

+39 -16

6 changed files

expand all

Documentation

devicetree

bindings

riscv

cpus.yaml

arch

riscv

boot

dts

sifive

fu540-c000.dtsi

hifive-unleashed-a00.dts

configs

defconfig

fault.c

include

dt-bindings

clock

sifive-fu540-prci.h

+14 -12

Documentation/devicetree/bindings/riscv/cpus.yaml

··· 152 152 - | 153 153 // Example 2: Spike ISA Simulator with 1 Hart 154 154 cpus { 155 - cpu@0 { 156 - device_type = "cpu"; 157 - reg = <0>; 158 - compatible = "riscv"; 159 - riscv,isa = "rv64imafdc"; 160 - mmu-type = "riscv,sv48"; 161 - interrupt-controller { 162 - #interrupt-cells = <1>; 163 - interrupt-controller; 164 - compatible = "riscv,cpu-intc"; 165 - }; 166 - }; 155 + #address-cells = <1>; 156 + #size-cells = <0>; 157 + cpu@0 { 158 + device_type = "cpu"; 159 + reg = <0>; 160 + compatible = "riscv"; 161 + riscv,isa = "rv64imafdc"; 162 + mmu-type = "riscv,sv48"; 163 + interrupt-controller { 164 + #interrupt-cells = <1>; 165 + interrupt-controller; 166 + compatible = "riscv,cpu-intc"; 167 + }; 168 + }; 167 169 }; 168 170 ...

arch/riscv/boot/dts/sifive/fu540-c000.dtsi

··· 163 163 interrupt-parent = <&plic0>; 164 164 interrupts = <4>; 165 165 clocks = <&prci PRCI_CLK_TLCLK>; 166 + status = "disabled"; 166 167 }; 167 168 uart1: serial@10011000 { 168 169 compatible = "sifive,fu540-c000-uart", "sifive,uart0"; ··· 171 170 interrupt-parent = <&plic0>; 172 171 interrupts = <5>; 173 172 clocks = <&prci PRCI_CLK_TLCLK>; 173 + status = "disabled"; 174 174 }; 175 175 i2c0: i2c@10030000 { 176 176 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; ··· 183 181 reg-io-width = <1>; 184 182 #address-cells = <1>; 185 183 #size-cells = <0>; 184 + status = "disabled"; 186 185 }; 187 186 qspi0: spi@10040000 { 188 187 compatible = "sifive,fu540-c000-spi", "sifive,spi0"; ··· 194 191 clocks = <&prci PRCI_CLK_TLCLK>; 195 192 #address-cells = <1>; 196 193 #size-cells = <0>; 194 + status = "disabled"; 197 195 }; 198 196 qspi1: spi@10041000 { 199 197 compatible = "sifive,fu540-c000-spi", "sifive,spi0"; ··· 205 201 clocks = <&prci PRCI_CLK_TLCLK>; 206 202 #address-cells = <1>; 207 203 #size-cells = <0>; 204 + status = "disabled"; 208 205 }; 209 206 qspi2: spi@10050000 { 210 207 compatible = "sifive,fu540-c000-spi", "sifive,spi0"; ··· 215 210 clocks = <&prci PRCI_CLK_TLCLK>; 216 211 #address-cells = <1>; 217 212 #size-cells = <0>; 213 + status = "disabled"; 218 214 }; 219 215 }; 220 216 };

+13

arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts

··· 42 42 }; 43 43 }; 44 44 45 + &uart0 { 46 + status = "okay"; 47 + }; 48 + 49 + &uart1 { 50 + status = "okay"; 51 + }; 52 + 53 + &i2c0 { 54 + status = "okay"; 55 + }; 56 + 45 57 &qspi0 { 58 + status = "okay"; 46 59 flash@0 { 47 60 compatible = "issi,is25wp256", "jedec,spi-nor"; 48 61 reg = <0>;

arch/riscv/configs/defconfig

··· 69 69 CONFIG_CLK_SIFIVE=y 70 70 CONFIG_CLK_SIFIVE_FU540_PRCI=y 71 71 CONFIG_SIFIVE_PLIC=y 72 + CONFIG_SPI_SIFIVE=y 72 73 CONFIG_EXT4_FS=y 73 74 CONFIG_EXT4_FS_POSIX_ACL=y 74 75 CONFIG_AUTOFS4_FS=y ··· 85 84 CONFIG_CRYPTO_USER_API_HASH=y 86 85 CONFIG_CRYPTO_DEV_VIRTIO=y 87 86 CONFIG_PRINTK_TIME=y 87 + CONFIG_SPI=y 88 + CONFIG_MMC_SPI=y 89 + CONFIG_MMC=y 90 + CONFIG_DEVTMPFS_MOUNT=y 88 91 # CONFIG_RCU_TRACE is not set

-3

arch/riscv/mm/fault.c

··· 272 272 * entries, but in RISC-V, SFENCE.VMA specifies an 273 273 * ordering constraint, not a cache flush; it is 274 274 * necessary even after writing invalid entries. 275 - * Relying on flush_tlb_fix_spurious_fault would 276 - * suffice, but the extra traps reduce 277 - * performance. So, eagerly SFENCE.VMA. 278 275 */ 279 276 local_flush_tlb_page(addr); 280 277

+1 -1

include/dt-bindings/clock/sifive-fu540-prci.h

Configure Feed

Configure Feed