tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"Not a huge amount happening, some MAINTAINERS updates, radeon, vmwgfx
and tegra fixes"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/vmwgfx: avoid null pointer dereference at failure paths
drm/vmwgfx: Make sure backing mobs are cleared when allocated. Update driver date.
drm/vmwgfx: Remove some unused surface formats
drm/radeon: enable speaker allocation setup on dce3.2
drm/radeon: change audio enable logic
drm/radeon: fix audio disable on dce6+
drm/radeon: free uvd ring on unload
drm/radeon: disable pll sharing for DP on DCE4.1
drm/radeon: fix missing bo reservation
drm/radeon: print the supported atpx function mask
MAINTAINERS: update drm git tree entry
MAINTAINERS: add entry for drm radeon driver
drm/tegra: Add guard to avoid double disable/enable of RGB outputs
gpu: host1x: do not check previously handled gathers
drm/tegra: fix typo 'CONFIG_TEGRA_DRM_FBDEV'

Linus Torvalds c59224d1 a53c8ceb

+118 -63
+11 -1
MAINTAINERS
··· 2848 2848 DRM DRIVERS 2849 2849 M: David Airlie <airlied@linux.ie> 2850 2850 L: dri-devel@lists.freedesktop.org 2851 - T: git git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6.git 2851 + T: git git://people.freedesktop.org/~airlied/linux 2852 2852 S: Maintained 2853 2853 F: drivers/gpu/drm/ 2854 2854 F: include/drm/ 2855 2855 F: include/uapi/drm/ 2856 + 2857 + RADEON DRM DRIVERS 2858 + M: Alex Deucher <alexander.deucher@amd.com> 2859 + M: Christian König <christian.koenig@amd.com> 2860 + L: dri-devel@lists.freedesktop.org 2861 + T: git git://people.freedesktop.org/~agd5f/linux 2862 + S: Supported 2863 + F: drivers/gpu/drm/radeon/ 2864 + F: include/drm/radeon* 2865 + F: include/uapi/drm/radeon* 2856 2866 2857 2867 INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets) 2858 2868 M: Daniel Vetter <daniel.vetter@ffwll.ch>
+15 -1
drivers/gpu/drm/radeon/atombios_crtc.c
··· 1774 1774 return ATOM_PPLL1; 1775 1775 DRM_ERROR("unable to allocate a PPLL\n"); 1776 1776 return ATOM_PPLL_INVALID; 1777 + } else if (ASIC_IS_DCE41(rdev)) { 1778 + /* Don't share PLLs on DCE4.1 chips */ 1779 + if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1780 + if (rdev->clock.dp_extclk) 1781 + /* skip PPLL programming if using ext clock */ 1782 + return ATOM_PPLL_INVALID; 1783 + } 1784 + pll_in_use = radeon_get_pll_use_mask(crtc); 1785 + if (!(pll_in_use & (1 << ATOM_PPLL1))) 1786 + return ATOM_PPLL1; 1787 + if (!(pll_in_use & (1 << ATOM_PPLL2))) 1788 + return ATOM_PPLL2; 1789 + DRM_ERROR("unable to allocate a PPLL\n"); 1790 + return ATOM_PPLL_INVALID; 1777 1791 } else if (ASIC_IS_DCE4(rdev)) { 1778 1792 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1779 1793 * depending on the asic: ··· 1815 1801 if (pll != ATOM_PPLL_INVALID) 1816 1802 return pll; 1817 1803 } 1818 - } else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */ 1804 + } else { 1819 1805 /* use the same PPLL for all monitors with the same clock */ 1820 1806 pll = radeon_get_shared_nondp_ppll(crtc); 1821 1807 if (pll != ATOM_PPLL_INVALID)
+9 -6
drivers/gpu/drm/radeon/dce6_afmt.c
··· 278 278 return !ASIC_IS_NODCE(rdev); 279 279 } 280 280 281 - static void dce6_audio_enable(struct radeon_device *rdev, 282 - struct r600_audio_pin *pin, 283 - bool enable) 281 + void dce6_audio_enable(struct radeon_device *rdev, 282 + struct r600_audio_pin *pin, 283 + bool enable) 284 284 { 285 + if (!pin) 286 + return; 287 + 285 288 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, 286 - AUDIO_ENABLED); 287 - DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id); 289 + enable ? AUDIO_ENABLED : 0); 288 290 } 289 291 290 292 static const u32 pin_offsets[7] = ··· 325 323 rdev->audio.pin[i].connected = false; 326 324 rdev->audio.pin[i].offset = pin_offsets[i]; 327 325 rdev->audio.pin[i].id = i; 328 - dce6_audio_enable(rdev, &rdev->audio.pin[i], true); 326 + /* disable audio. it will be set up later */ 327 + dce6_audio_enable(rdev, &rdev->audio.pin[i], false); 329 328 } 330 329 331 330 return 0;
+1 -1
drivers/gpu/drm/radeon/evergreen.c
··· 5475 5475 radeon_wb_fini(rdev); 5476 5476 radeon_ib_pool_fini(rdev); 5477 5477 radeon_irq_kms_fini(rdev); 5478 - evergreen_pcie_gart_fini(rdev); 5479 5478 uvd_v1_0_fini(rdev); 5480 5479 radeon_uvd_fini(rdev); 5480 + evergreen_pcie_gart_fini(rdev); 5481 5481 r600_vram_scratch_fini(rdev); 5482 5482 radeon_gem_fini(rdev); 5483 5483 radeon_fence_driver_fini(rdev);
+15 -11
drivers/gpu/drm/radeon/evergreen_hdmi.c
··· 306 306 return; 307 307 offset = dig->afmt->offset; 308 308 309 + /* disable audio prior to setting up hw */ 310 + if (ASIC_IS_DCE6(rdev)) { 311 + dig->afmt->pin = dce6_audio_get_pin(rdev); 312 + dce6_audio_enable(rdev, dig->afmt->pin, false); 313 + } else { 314 + dig->afmt->pin = r600_audio_get_pin(rdev); 315 + r600_audio_enable(rdev, dig->afmt->pin, false); 316 + } 317 + 309 318 evergreen_audio_set_dto(encoder, mode->clock); 310 319 311 320 WREG32(HDMI_VBI_PACKET_CONTROL + offset, ··· 418 409 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 419 410 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); 420 411 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); 412 + 413 + /* enable audio after to setting up hw */ 414 + if (ASIC_IS_DCE6(rdev)) 415 + dce6_audio_enable(rdev, dig->afmt->pin, true); 416 + else 417 + r600_audio_enable(rdev, dig->afmt->pin, true); 421 418 } 422 419 423 420 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) 424 421 { 425 - struct drm_device *dev = encoder->dev; 426 - struct radeon_device *rdev = dev->dev_private; 427 422 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 428 423 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 429 424 ··· 439 426 return; 440 427 if (!enable && !dig->afmt->enabled) 441 428 return; 442 - 443 - if (enable) { 444 - if (ASIC_IS_DCE6(rdev)) 445 - dig->afmt->pin = dce6_audio_get_pin(rdev); 446 - else 447 - dig->afmt->pin = r600_audio_get_pin(rdev); 448 - } else { 449 - dig->afmt->pin = NULL; 450 - } 451 429 452 430 dig->afmt->enabled = enable; 453 431
+8 -6
drivers/gpu/drm/radeon/r600_audio.c
··· 142 142 } 143 143 144 144 /* enable the audio stream */ 145 - static void r600_audio_enable(struct radeon_device *rdev, 146 - struct r600_audio_pin *pin, 147 - bool enable) 145 + void r600_audio_enable(struct radeon_device *rdev, 146 + struct r600_audio_pin *pin, 147 + bool enable) 148 148 { 149 149 u32 value = 0; 150 + 151 + if (!pin) 152 + return; 150 153 151 154 if (ASIC_IS_DCE4(rdev)) { 152 155 if (enable) { ··· 161 158 WREG32_P(R600_AUDIO_ENABLE, 162 159 enable ? 0x81000000 : 0x0, ~0x81000000); 163 160 } 164 - DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id); 165 161 } 166 162 167 163 /* ··· 180 178 rdev->audio.pin[0].status_bits = 0; 181 179 rdev->audio.pin[0].category_code = 0; 182 180 rdev->audio.pin[0].id = 0; 183 - 184 - r600_audio_enable(rdev, &rdev->audio.pin[0], true); 181 + /* disable audio. it will be set up later */ 182 + r600_audio_enable(rdev, &rdev->audio.pin[0], false); 185 183 186 184 return 0; 187 185 }
+7 -8
drivers/gpu/drm/radeon/r600_hdmi.c
··· 329 329 u8 *sadb; 330 330 int sad_count; 331 331 332 - /* XXX: setting this register causes hangs on some asics */ 333 - return; 334 - 335 332 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 336 333 if (connector->encoder == encoder) { 337 334 radeon_connector = to_radeon_connector(connector); ··· 457 460 return; 458 461 offset = dig->afmt->offset; 459 462 463 + /* disable audio prior to setting up hw */ 464 + dig->afmt->pin = r600_audio_get_pin(rdev); 465 + r600_audio_enable(rdev, dig->afmt->pin, false); 466 + 460 467 r600_audio_set_dto(encoder, mode->clock); 461 468 462 469 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, ··· 532 531 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); 533 532 534 533 r600_hdmi_audio_workaround(encoder); 534 + 535 + /* enable audio after to setting up hw */ 536 + r600_audio_enable(rdev, dig->afmt->pin, true); 535 537 } 536 538 537 539 /* ··· 654 650 return; 655 651 if (!enable && !dig->afmt->enabled) 656 652 return; 657 - 658 - if (enable) 659 - dig->afmt->pin = r600_audio_get_pin(rdev); 660 - else 661 - dig->afmt->pin = NULL; 662 653 663 654 /* Older chipsets require setting HDMI and routing manually */ 664 655 if (!ASIC_IS_DCE3(rdev)) {
+6
drivers/gpu/drm/radeon/radeon.h
··· 2747 2747 void r600_audio_update_hdmi(struct work_struct *work); 2748 2748 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2749 2749 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2750 + void r600_audio_enable(struct radeon_device *rdev, 2751 + struct r600_audio_pin *pin, 2752 + bool enable); 2753 + void dce6_audio_enable(struct radeon_device *rdev, 2754 + struct r600_audio_pin *pin, 2755 + bool enable); 2750 2756 2751 2757 /* 2752 2758 * R600 vram scratch functions
+2 -1
drivers/gpu/drm/radeon/radeon_atpx_handler.c
··· 219 219 memcpy(&output, info->buffer.pointer, size); 220 220 221 221 /* TODO: check version? */ 222 - printk("ATPX version %u\n", output.version); 222 + printk("ATPX version %u, functions 0x%08x\n", 223 + output.version, output.function_bits); 223 224 224 225 radeon_atpx_parse_functions(&atpx->functions, output.function_bits); 225 226
+6
drivers/gpu/drm/radeon/radeon_kms.c
··· 537 537 538 538 radeon_vm_init(rdev, &fpriv->vm); 539 539 540 + r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 541 + if (r) 542 + return r; 543 + 540 544 /* map the ib pool buffer read only into 541 545 * virtual address space */ 542 546 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, ··· 548 544 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, 549 545 RADEON_VM_PAGE_READABLE | 550 546 RADEON_VM_PAGE_SNOOPED); 547 + 548 + radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 551 549 if (r) { 552 550 radeon_vm_fini(rdev, &fpriv->vm); 553 551 kfree(fpriv);
+2
drivers/gpu/drm/radeon/radeon_uvd.c
··· 171 171 172 172 radeon_bo_unref(&rdev->uvd.vcpu_bo); 173 173 174 + radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]); 175 + 174 176 release_firmware(rdev->uvd_fw); 175 177 } 176 178
+1 -1
drivers/gpu/drm/radeon/rv770.c
··· 1955 1955 radeon_wb_fini(rdev); 1956 1956 radeon_ib_pool_fini(rdev); 1957 1957 radeon_irq_kms_fini(rdev); 1958 - rv770_pcie_gart_fini(rdev); 1959 1958 uvd_v1_0_fini(rdev); 1960 1959 radeon_uvd_fini(rdev); 1960 + rv770_pcie_gart_fini(rdev); 1961 1961 r600_vram_scratch_fini(rdev); 1962 1962 radeon_gem_fini(rdev); 1963 1963 radeon_fence_driver_fini(rdev);
+1 -1
drivers/gpu/drm/tegra/drm.c
··· 104 104 105 105 static void tegra_drm_lastclose(struct drm_device *drm) 106 106 { 107 - #ifdef CONFIG_TEGRA_DRM_FBDEV 107 + #ifdef CONFIG_DRM_TEGRA_FBDEV 108 108 struct tegra_drm *tegra = drm->dev_private; 109 109 110 110 tegra_fbdev_restore_mode(tegra->fbdev);
+11
drivers/gpu/drm/tegra/rgb.c
··· 15 15 struct tegra_rgb { 16 16 struct tegra_output output; 17 17 struct tegra_dc *dc; 18 + bool enabled; 18 19 19 20 struct clk *clk_parent; 20 21 struct clk *clk; ··· 90 89 struct tegra_rgb *rgb = to_rgb(output); 91 90 unsigned long value; 92 91 92 + if (rgb->enabled) 93 + return 0; 94 + 93 95 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); 94 96 95 97 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; ··· 126 122 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 127 123 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 128 124 125 + rgb->enabled = true; 126 + 129 127 return 0; 130 128 } 131 129 ··· 135 129 { 136 130 struct tegra_rgb *rgb = to_rgb(output); 137 131 unsigned long value; 132 + 133 + if (!rgb->enabled) 134 + return 0; 138 135 139 136 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL); 140 137 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | ··· 152 143 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 153 144 154 145 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); 146 + 147 + rgb->enabled = false; 155 148 156 149 return 0; 157 150 }
+1 -6
drivers/gpu/drm/vmwgfx/svga3d_reg.h
··· 261 261 /* Planar video formats. */ 262 262 SVGA3D_YV12 = 121, 263 263 264 - /* Shader constant formats. */ 265 - SVGA3D_SURFACE_SHADERCONST_FLOAT = 122, 266 - SVGA3D_SURFACE_SHADERCONST_INT = 123, 267 - SVGA3D_SURFACE_SHADERCONST_BOOL = 124, 268 - 269 - SVGA3D_FORMAT_MAX = 125, 264 + SVGA3D_FORMAT_MAX = 122, 270 265 } SVGA3dSurfaceFormat; 271 266 272 267 typedef uint32 SVGA3dColor; /* a, r, g, b */
+1 -1
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
··· 40 40 #include <drm/ttm/ttm_module.h> 41 41 #include "vmwgfx_fence.h" 42 42 43 - #define VMWGFX_DRIVER_DATE "20121114" 43 + #define VMWGFX_DRIVER_DATE "20140228" 44 44 #define VMWGFX_DRIVER_MAJOR 2 45 45 #define VMWGFX_DRIVER_MINOR 5 46 46 #define VMWGFX_DRIVER_PATCHLEVEL 0
+19 -16
drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
··· 188 188 189 189 bo = otable->page_table->pt_bo; 190 190 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); 191 - if (unlikely(cmd == NULL)) 192 - DRM_ERROR("Failed reserving FIFO space for OTable setup.\n"); 193 - 194 - memset(cmd, 0, sizeof(*cmd)); 195 - cmd->header.id = SVGA_3D_CMD_SET_OTABLE_BASE; 196 - cmd->header.size = sizeof(cmd->body); 197 - cmd->body.type = type; 198 - cmd->body.baseAddress = 0; 199 - cmd->body.sizeInBytes = 0; 200 - cmd->body.validSizeInBytes = 0; 201 - cmd->body.ptDepth = SVGA3D_MOBFMT_INVALID; 202 - vmw_fifo_commit(dev_priv, sizeof(*cmd)); 191 + if (unlikely(cmd == NULL)) { 192 + DRM_ERROR("Failed reserving FIFO space for OTable " 193 + "takedown.\n"); 194 + } else { 195 + memset(cmd, 0, sizeof(*cmd)); 196 + cmd->header.id = SVGA_3D_CMD_SET_OTABLE_BASE; 197 + cmd->header.size = sizeof(cmd->body); 198 + cmd->body.type = type; 199 + cmd->body.baseAddress = 0; 200 + cmd->body.sizeInBytes = 0; 201 + cmd->body.validSizeInBytes = 0; 202 + cmd->body.ptDepth = SVGA3D_MOBFMT_INVALID; 203 + vmw_fifo_commit(dev_priv, sizeof(*cmd)); 204 + } 203 205 204 206 if (bo) { 205 207 int ret; ··· 564 562 if (unlikely(cmd == NULL)) { 565 563 DRM_ERROR("Failed reserving FIFO space for Memory " 566 564 "Object unbinding.\n"); 565 + } else { 566 + cmd->header.id = SVGA_3D_CMD_DESTROY_GB_MOB; 567 + cmd->header.size = sizeof(cmd->body); 568 + cmd->body.mobid = mob->id; 569 + vmw_fifo_commit(dev_priv, sizeof(*cmd)); 567 570 } 568 - cmd->header.id = SVGA_3D_CMD_DESTROY_GB_MOB; 569 - cmd->header.size = sizeof(cmd->body); 570 - cmd->body.mobid = mob->id; 571 - vmw_fifo_commit(dev_priv, sizeof(*cmd)); 572 571 if (bo) { 573 572 vmw_fence_single_bo(bo, NULL); 574 573 ttm_bo_unreserve(bo);
+1 -2
drivers/gpu/drm/vmwgfx/vmwgfx_resource.c
··· 427 427 INIT_LIST_HEAD(&vmw_bo->res_list); 428 428 429 429 ret = ttm_bo_init(bdev, &vmw_bo->base, size, 430 - (user) ? ttm_bo_type_device : 431 - ttm_bo_type_kernel, placement, 430 + ttm_bo_type_device, placement, 432 431 0, interruptible, 433 432 NULL, acc_size, NULL, bo_free); 434 433 return ret;
+1 -1
drivers/gpu/host1x/job.c
··· 538 538 539 539 g->base = job->gather_addr_phys[i]; 540 540 541 - for (j = 0; j < job->num_gathers; j++) 541 + for (j = i + 1; j < job->num_gathers; j++) 542 542 if (job->gathers[j].bo == g->bo) 543 543 job->gathers[j].handled = true; 544 544