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perf vendor events power10: Update JSON/events

Update JSON/events for power10 platform with additional events.

Reviewed-by: Ian Rogers <irogers@google.com>
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: Disha Goel <disgoel@linux.vnet.ibm.com>
Cc: Hari Bathini <hbathini@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org
Link: https://lore.kernel.org/r/20240827053206.538814-1-kjain@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

authored by

Kajol Jain and committed by
Arnaldo Carvalho de Melo c5d50457 7bedcbae

+40
+25
tools/perf/pmu-events/arch/powerpc/power10/datasource.json
··· 15 15 "BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory due to a demand miss." 16 16 }, 17 17 { 18 + "EventCode": "0x0000004080", 19 + "EventName": "PM_INST_FROM_L1", 20 + "BriefDescription": "An instruction fetch hit in the L1. Each fetch group contains 8 instructions. The same line can hit 4 times if 32 sequential instructions are fetched." 21 + }, 22 + { 23 + "EventCode": "0x000000026080", 24 + "EventName": "PM_L2_LD_MISS", 25 + "BriefDescription": "All successful D-Side Load dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." 26 + }, 27 + { 28 + "EventCode": "0x000000026880", 29 + "EventName": "PM_L2_ST_MISS", 30 + "BriefDescription": "All successful D-Side Store dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." 31 + }, 32 + { 33 + "EventCode": "0x010000046880", 34 + "EventName": "PM_L2_ST_HIT", 35 + "BriefDescription": "All successful D-side store dispatches for this thread that were L2 hits. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." 36 + }, 37 + { 38 + "EventCode": "0x000000036880", 39 + "EventName": "PM_L2_INST_MISS", 40 + "BriefDescription": "All successful instruction (demand and prefetch) dispatches for this thread that missed in the L2. Since the event happens in a 2:1 clock domain and is time-sliced across all 4 threads, the event count should be multiplied by 2." 41 + }, 42 + { 18 43 "EventCode": "0x000300000000C040", 19 44 "EventName": "PM_INST_FROM_L2", 20 45 "BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss."
+10
tools/perf/pmu-events/arch/powerpc/power10/frontend.json
··· 93 93 "EventCode": "0x400FC", 94 94 "EventName": "PM_ITLB_MISS", 95 95 "BriefDescription": "Instruction TLB reload (after a miss), all page sizes. Includes only demand misses." 96 + }, 97 + { 98 + "EventCode": "0x00000040B8", 99 + "EventName": "PM_PRED_BR_TKN_COND_DIR", 100 + "BriefDescription": "A conditional branch finished with correctly predicted direction. Resolved taken." 101 + }, 102 + { 103 + "EventCode": "0x00000048B8", 104 + "EventName": "PM_PRED_BR_NTKN_COND_DIR", 105 + "BriefDescription": "A conditional branch finished with correctly predicted direction. Resolved not taken." 96 106 } 97 107 ]
+5
tools/perf/pmu-events/arch/powerpc/power10/pmc.json
··· 105 105 "BriefDescription": "Processor cycles gated by the run latch." 106 106 }, 107 107 { 108 + "EventCode": "0x200F8", 109 + "EventName": "PM_EXT_INT", 110 + "BriefDescription": "Cycles an external interrupt was active." 111 + }, 112 + { 108 113 "EventCode": "0x30010", 109 114 "EventName": "PM_PMC2_OVERFLOW", 110 115 "BriefDescription": "The event selected for PMC2 caused the event counter to overflow."