Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'irq-urgent-2022-02-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Thomas Gleixner:
"Interrupt chip driver fixes:
- Don't install an hotplug notifier for GICV3-ITS on systems which do
not need it to prevent a warning in the notifier about inconsistent
state
- Add the missing device tree matching for the T-HEAD PLIC variant so
the related SoC is properly supported"
* tag 'irq-urgent-2022-02-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/sifive-plic: Add missing thead,c900-plic match string
dt-bindings: update riscv plic compatible string
irqchip/gic-v3-its: Skip HP notifier when no ITS is registered
+19
-6
+15
-6
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+15
-6
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
···
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35
contains a specific memory layout, which is documented in chapter 8 of the
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36
SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
37
37
38
+
The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
39
+
T-HEAD PLIC implementation requires setting a delegation bit to allow access
40
+
from S-mode. So add thead,c900-plic to distinguish them.
41
+
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maintainers:
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- Sagar Kadam <sagar.kadam@sifive.com>
40
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- Paul Walmsley <paul.walmsley@sifive.com>
···
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properties:
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compatible:
49
-
items:
50
-
- enum:
51
-
- sifive,fu540-c000-plic
52
-
- starfive,jh7100-plic
53
-
- canaan,k210-plic
54
-
- const: sifive,plic-1.0.0
45
+
oneOf:
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+
- items:
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+
- enum:
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+
- sifive,fu540-c000-plic
49
+
- starfive,jh7100-plic
50
+
- canaan,k210-plic
51
+
- const: sifive,plic-1.0.0
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+
- items:
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+
- enum:
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+
- allwinner,sun20i-d1-plic
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+
- const: thead,c900-plic
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reg:
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maxItems: 1
+3
drivers/irqchip/irq-gic-v3-its.c
+3
drivers/irqchip/irq-gic-v3-its.c
···
5517
5517
if (!efi_enabled(EFI_CONFIG_TABLES))
5518
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return 0;
5519
5519
5520
+
if (list_empty(&its_nodes))
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+
return 0;
5522
+
5520
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gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID;
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state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
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"irqchip/arm/gicv3/memreserve:online",
+1
drivers/irqchip/irq-sifive-plic.c
+1
drivers/irqchip/irq-sifive-plic.c