tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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cxl/pci: Add sysfs attribute for CXL 1.1 device link status

Add sysfs attribute for CXL 1.1 device link status to the cxl pci device.

In CXL1.1, the link status of the device is included in the RCRB mapped to
the memory mapped register area. Critically, that arrangement makes the
link status and control registers invisible to existing PCI user tooling.

Export those registers via sysfs with the expectation that PCI user
tooling will alternatively look for these sysfs files when attempting to
access to these CXL 1.1 endpoints registers.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Kobayashi,Daisuke <kobayashi.da-06@fujitsu.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Link: https://patch.msgid.link/20241002011549.408412-3-kobayashi.da-06@fujitsu.com
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

authored by

Kobayashi,Daisuke and committed by
Dave Jiang c5eaec79 7a01213d

+78
+78
drivers/cxl/pci.c
··· 820 820 return 0; 821 821 } 822 822 823 + static ssize_t rcd_pcie_cap_emit(struct device *dev, u16 offset, char *buf, size_t width) 824 + { 825 + struct cxl_dev_state *cxlds = dev_get_drvdata(dev); 826 + struct cxl_memdev *cxlmd = cxlds->cxlmd; 827 + struct device *root_dev; 828 + struct cxl_dport *dport; 829 + struct cxl_port *root __free(put_cxl_port) = 830 + cxl_mem_find_port(cxlmd, &dport); 831 + 832 + if (!root) 833 + return -ENXIO; 834 + 835 + root_dev = root->uport_dev; 836 + if (!root_dev) 837 + return -ENXIO; 838 + 839 + guard(device)(root_dev); 840 + if (!root_dev->driver) 841 + return -ENXIO; 842 + 843 + switch (width) { 844 + case 2: 845 + return sysfs_emit(buf, "%#x\n", 846 + readw(dport->regs.rcd_pcie_cap + offset)); 847 + case 4: 848 + return sysfs_emit(buf, "%#x\n", 849 + readl(dport->regs.rcd_pcie_cap + offset)); 850 + default: 851 + return -EINVAL; 852 + } 853 + } 854 + 855 + static ssize_t rcd_link_cap_show(struct device *dev, 856 + struct device_attribute *attr, char *buf) 857 + { 858 + return rcd_pcie_cap_emit(dev, PCI_EXP_LNKCAP, buf, sizeof(u32)); 859 + } 860 + static DEVICE_ATTR_RO(rcd_link_cap); 861 + 862 + static ssize_t rcd_link_ctrl_show(struct device *dev, 863 + struct device_attribute *attr, char *buf) 864 + { 865 + return rcd_pcie_cap_emit(dev, PCI_EXP_LNKCTL, buf, sizeof(u16)); 866 + } 867 + static DEVICE_ATTR_RO(rcd_link_ctrl); 868 + 869 + static ssize_t rcd_link_status_show(struct device *dev, 870 + struct device_attribute *attr, char *buf) 871 + { 872 + return rcd_pcie_cap_emit(dev, PCI_EXP_LNKSTA, buf, sizeof(u16)); 873 + } 874 + static DEVICE_ATTR_RO(rcd_link_status); 875 + 876 + static struct attribute *cxl_rcd_attrs[] = { 877 + &dev_attr_rcd_link_cap.attr, 878 + &dev_attr_rcd_link_ctrl.attr, 879 + &dev_attr_rcd_link_status.attr, 880 + NULL 881 + }; 882 + 883 + static umode_t cxl_rcd_visible(struct kobject *kobj, struct attribute *a, int n) 884 + { 885 + struct device *dev = kobj_to_dev(kobj); 886 + struct pci_dev *pdev = to_pci_dev(dev); 887 + 888 + if (is_cxl_restricted(pdev)) 889 + return a->mode; 890 + 891 + return 0; 892 + } 893 + 894 + static struct attribute_group cxl_rcd_group = { 895 + .attrs = cxl_rcd_attrs, 896 + .is_visible = cxl_rcd_visible, 897 + }; 898 + __ATTRIBUTE_GROUPS(cxl_rcd); 899 + 823 900 static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 824 901 { 825 902 struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); ··· 1106 1029 .id_table = cxl_mem_pci_tbl, 1107 1030 .probe = cxl_pci_probe, 1108 1031 .err_handler = &cxl_error_handlers, 1032 + .dev_groups = cxl_rcd_groups, 1109 1033 .driver = { 1110 1034 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1111 1035 },