+66 -37

drivers/gpu/drm/display/drm_dp_helper.c

reviewed

··· 2705 2705 EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr); 2706 2706 2707 2707 /** 2708 2708 + * drm_dp_dsc_slice_count_to_mask() - Convert a slice count to a slice count mask 2709 2709 + * @slice_count: slice count 2710 2710 + * 2711 2711 + * Convert @slice_count to a slice count mask. 2712 2712 + * 2713 2713 + * Returns the slice count mask. 2714 2714 + */ 2715 2715 + u32 drm_dp_dsc_slice_count_to_mask(int slice_count) 2716 2716 + { 2717 2717 + return BIT(slice_count - 1); 2718 2718 + } 2719 2719 + EXPORT_SYMBOL(drm_dp_dsc_slice_count_to_mask); 2720 2720 + 2721 2721 + /** 2722 2722 + * drm_dp_dsc_sink_slice_count_mask() - Get the mask of valid DSC sink slice counts 2723 2723 + * @dsc_dpcd: the sink's DSC DPCD capabilities 2724 2724 + * @is_edp: %true for an eDP sink 2725 2725 + * 2726 2726 + * Get the mask of supported slice counts from the sink's DSC DPCD register. 2727 2727 + * 2728 2728 + * Returns: 2729 2729 + * Mask of slice counts supported by the DSC sink: 2730 2730 + * - > 0: bit#0,1,3,5..,23 set if the sink supports 1,2,4,6..,24 slices 2731 2731 + * - 0: if the sink doesn't support any slices 2732 2732 + */ 2733 2733 + u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2734 2734 + bool is_edp) 2735 2735 + { 2736 2736 + u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; 2737 2737 + u32 mask = 0; 2738 2738 + 2739 2739 + if (!is_edp) { 2740 2740 + /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ 2741 2741 + u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; 2742 2742 + 2743 2743 + if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) 2744 2744 + mask |= drm_dp_dsc_slice_count_to_mask(24); 2745 2745 + if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) 2746 2746 + mask |= drm_dp_dsc_slice_count_to_mask(20); 2747 2747 + if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) 2748 2748 + mask |= drm_dp_dsc_slice_count_to_mask(16); 2749 2749 + } 2750 2750 + 2751 2751 + /* DP, eDP v1.5+ */ 2752 2752 + if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) 2753 2753 + mask |= drm_dp_dsc_slice_count_to_mask(12); 2754 2754 + if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) 2755 2755 + mask |= drm_dp_dsc_slice_count_to_mask(10); 2756 2756 + if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) 2757 2757 + mask |= drm_dp_dsc_slice_count_to_mask(8); 2758 2758 + if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) 2759 2759 + mask |= drm_dp_dsc_slice_count_to_mask(6); 2760 2760 + /* DP, eDP v1.4+ */ 2761 2761 + if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2762 2762 + mask |= drm_dp_dsc_slice_count_to_mask(4); 2763 2763 + if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2764 2764 + mask |= drm_dp_dsc_slice_count_to_mask(2); 2765 2765 + if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2766 2766 + mask |= drm_dp_dsc_slice_count_to_mask(1); 2767 2767 + 2768 2768 + return mask; 2769 2769 + } 2770 2770 + EXPORT_SYMBOL(drm_dp_dsc_sink_slice_count_mask); 2771 2771 + 2772 2772 + /** 2708 2773 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count 2709 2774 * supported by the DSC sink. 2710 2775 * @dsc_dpcd: DSC capabilities from DPCD ··· 2788 2723 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2789 2724 bool is_edp) 2790 2725 { 2791 2791 - u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; 2792 2792 - 2793 2793 - if (is_edp) { 2794 2794 - /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */ 2795 2795 - if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2796 2796 - return 4; 2797 2797 - if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2798 2798 - return 2; 2799 2799 - if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2800 2800 - return 1; 2801 2801 - } else { 2802 2802 - /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ 2803 2803 - u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; 2804 2804 - 2805 2805 - if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) 2806 2806 - return 24; 2807 2807 - if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) 2808 2808 - return 20; 2809 2809 - if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) 2810 2810 - return 16; 2811 2811 - if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) 2812 2812 - return 12; 2813 2813 - if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) 2814 2814 - return 10; 2815 2815 - if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) 2816 2816 - return 8; 2817 2817 - if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) 2818 2818 - return 6; 2819 2819 - if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2820 2820 - return 4; 2821 2821 - if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2822 2822 - return 2; 2823 2823 - if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2824 2824 - return 1; 2825 2825 - } 2826 2826 - 2827 2827 - return 0; 2726 2726 + return fls(drm_dp_dsc_sink_slice_count_mask(dsc_dpcd, is_edp)); 2828 2727 } 2829 2728 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); 2830 2729

+12 -8

drivers/gpu/drm/i915/Makefile

reviewed

··· 27 27 i915_config.o \ 28 28 i915_driver.o \ 29 29 i915_drm_client.o \ 30 30 + i915_edram.o \ 31 31 + i915_freq.o \ 30 32 i915_getparam.o \ 33 33 + i915_gmch.o \ 31 34 i915_ioctl.o \ 32 35 i915_irq.o \ 33 36 i915_mitigations.o \ ··· 57 54 vlv_iosf_sb.o \ 58 55 vlv_suspend.o 59 56 60 60 - # core peripheral code 61 61 - i915-y += \ 62 62 - soc/intel_dram.o \ 63 63 - soc/intel_gmch.o \ 64 64 - soc/intel_rom.o 65 65 - 66 57 # core library code 67 58 i915-y += \ 68 59 i915_memcpy.o \ ··· 73 76 i915_debugfs_params.o 74 77 i915-$(CONFIG_PERF_EVENTS) += \ 75 78 i915_pmu.o 79 79 + 80 80 + # core display adaptation 81 81 + i915-y += \ 82 82 + i915_display_pc8.o \ 83 83 + i915_hdcp_gsc.o \ 84 84 + i915_panic.o 76 85 77 86 # "Graphics Technology" (aka we talk to the gpu) 78 87 gt-y += \ ··· 270 267 display/intel_dpll_mgr.o \ 271 268 display/intel_dpt.o \ 272 269 display/intel_dpt_common.o \ 270 270 + display/intel_dram.o \ 273 271 display/intel_drrs.o \ 274 272 display/intel_dsb.o \ 275 273 display/intel_dsb_buffer.o \ ··· 284 280 display/intel_frontbuffer.o \ 285 281 display/intel_global_state.o \ 286 282 display/intel_hdcp.o \ 287 287 - display/intel_hdcp_gsc.o \ 288 283 display/intel_hdcp_gsc_message.o \ 289 284 display/intel_hotplug.o \ 290 285 display/intel_hotplug_irq.o \ ··· 295 292 display/intel_modeset_setup.o \ 296 293 display/intel_modeset_verify.o \ 297 294 display/intel_overlay.o \ 298 298 - display/intel_panic.o \ 295 295 + display/intel_parent.o \ 299 296 display/intel_pch.o \ 300 297 display/intel_pch_display.o \ 301 298 display/intel_pch_refclk.o \ ··· 304 301 display/intel_pmdemand.o \ 305 302 display/intel_psr.o \ 306 303 display/intel_quirks.o \ 304 304 + display/intel_rom.o \ 307 305 display/intel_sbi.o \ 308 306 display/intel_sprite.o \ 309 307 display/intel_sprite_uapi.o \

+2 -3

drivers/gpu/drm/i915/display/g4x_dp.c

reviewed

··· 302 302 { 303 303 struct intel_display *display = to_intel_display(encoder); 304 304 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 305 305 - intel_wakeref_t wakeref; 305 305 + struct ref_tracker *wakeref; 306 306 bool ret; 307 307 308 308 wakeref = intel_display_power_get_if_enabled(display, ··· 684 684 struct intel_display *display = to_intel_display(state); 685 685 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 686 686 u32 dp_reg = intel_de_read(display, intel_dp->output_reg); 687 687 - intel_wakeref_t wakeref; 688 687 689 688 if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN)) 690 689 return; 691 690 692 692 - with_intel_pps_lock(intel_dp, wakeref) { 691 691 + with_intel_pps_lock(intel_dp) { 693 692 if (display->platform.valleyview || display->platform.cherryview) 694 693 vlv_pps_port_enable_unlocked(encoder, pipe_config); 695 694

+1 -1

drivers/gpu/drm/i915/display/g4x_hdmi.c

reviewed

··· 68 68 { 69 69 struct intel_display *display = to_intel_display(encoder); 70 70 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 71 71 - intel_wakeref_t wakeref; 71 71 + struct ref_tracker *wakeref; 72 72 bool ret; 73 73 74 74 wakeref = intel_display_power_get_if_enabled(display,

+4 -5

drivers/gpu/drm/i915/display/i9xx_plane.c

reviewed

··· 22 22 #include "intel_fb.h" 23 23 #include "intel_fbc.h" 24 24 #include "intel_frontbuffer.h" 25 25 - #include "intel_panic.h" 26 25 #include "intel_plane.h" 27 26 #include "intel_sprite.h" 28 27 ··· 133 134 enum i9xx_plane_id i9xx_plane) 134 135 { 135 136 if (i9xx_plane_has_fbc(display, i9xx_plane)) 136 136 - return display->fbc[INTEL_FBC_A]; 137 137 + return display->fbc.instances[INTEL_FBC_A]; 137 138 else 138 139 return NULL; 139 140 } ··· 723 724 struct intel_display *display = to_intel_display(plane); 724 725 enum intel_display_power_domain power_domain; 725 726 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; 726 726 - intel_wakeref_t wakeref; 727 727 + struct ref_tracker *wakeref; 727 728 bool ret; 728 729 u32 val; 729 730 ··· 818 819 { 819 820 struct intel_display *display = to_intel_display(plane); 820 821 821 821 - if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) 822 822 + if (intel_plane_can_async_flip(plane, fb->format, fb->modifier)) 822 823 return 256 * 1024; 823 824 824 825 /* FIXME undocumented so not sure what's actually needed */ ··· 842 843 { 843 844 struct intel_display *display = to_intel_display(plane); 844 845 845 845 - if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) 846 846 + if (intel_plane_can_async_flip(plane, fb->format, fb->modifier)) 846 847 return 256 * 1024; 847 848 848 849 if (intel_scanout_needs_vtd_wa(display))

+2 -3

drivers/gpu/drm/i915/display/i9xx_wm.c

reviewed

··· 7 7 8 8 #include <drm/drm_print.h> 9 9 10 10 - #include "soc/intel_dram.h" 11 11 - 12 10 #include "i915_drv.h" 13 11 #include "i915_reg.h" 14 12 #include "i9xx_wm.h" ··· 17 19 #include "intel_display.h" 18 20 #include "intel_display_regs.h" 19 21 #include "intel_display_trace.h" 22 22 + #include "intel_dram.h" 20 23 #include "intel_fb.h" 21 24 #include "intel_mchbar_regs.h" 22 25 #include "intel_wm.h" ··· 90 91 91 92 static const struct cxsr_latency *pnv_get_cxsr_latency(struct intel_display *display) 92 93 { 93 93 - const struct dram_info *dram_info = intel_dram_info(display->drm); 94 94 + const struct dram_info *dram_info = intel_dram_info(display); 94 95 bool is_ddr3 = dram_info->type == INTEL_DRAM_DDR3; 95 96 int i; 96 97

+2 -2

drivers/gpu/drm/i915/display/icl_dsi.c

reviewed

··· 1411 1411 enum port port; 1412 1412 1413 1413 for_each_dsi_port(port, intel_dsi->ports) { 1414 1414 - intel_wakeref_t wakeref; 1414 1414 + struct ref_tracker *wakeref; 1415 1415 1416 1416 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1417 1417 intel_display_power_put(display, ··· 1722 1722 struct intel_display *display = to_intel_display(encoder); 1723 1723 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1724 1724 enum transcoder dsi_trans; 1725 1725 - intel_wakeref_t wakeref; 1725 1725 + struct ref_tracker *wakeref; 1726 1726 enum port port; 1727 1727 bool ret = false; 1728 1728 u32 tmp;

+2 -4

drivers/gpu/drm/i915/display/intel_alpm.c

reviewed

··· 326 326 if (intel_dp->as_sdp_supported) { 327 327 u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1; 328 328 329 329 - if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 330 330 - DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP) 329 329 + if (crtc_state->link_off_after_as_sdp_when_pr_active) 331 330 pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU; 332 332 - if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 333 333 - DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR)) 331 331 + if (crtc_state->disable_as_sdp_when_pr_active) 334 332 pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE; 335 333 336 334 intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),

+3 -3

drivers/gpu/drm/i915/display/intel_audio.c

reviewed

··· 1042 1042 static unsigned long intel_audio_component_get_power(struct device *kdev) 1043 1043 { 1044 1044 struct intel_display *display = to_intel_display(kdev); 1045 1045 - intel_wakeref_t wakeref; 1045 1045 + struct ref_tracker *wakeref; 1046 1046 1047 1047 /* Catch potential impedance mismatches before they occur! */ 1048 1048 - BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); 1048 1048 + BUILD_BUG_ON(sizeof(wakeref) > sizeof(unsigned long)); 1049 1049 1050 1050 wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK); 1051 1051 ··· 1074 1074 unsigned long cookie) 1075 1075 { 1076 1076 struct intel_display *display = to_intel_display(kdev); 1077 1077 - intel_wakeref_t wakeref = (intel_wakeref_t)cookie; 1077 1077 + struct ref_tracker *wakeref = (struct ref_tracker *)cookie; 1078 1078 1079 1079 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 1080 1080 if (--display->audio.power_refcount == 0)

+73 -3

drivers/gpu/drm/i915/display/intel_bios.c

reviewed

··· 34 34 #include <drm/drm_fixed.h> 35 35 #include <drm/drm_print.h> 36 36 37 37 - #include "soc/intel_rom.h" 38 38 - 39 37 #include "intel_display.h" 40 38 #include "intel_display_core.h" 41 39 #include "intel_display_rpm.h" 42 40 #include "intel_display_types.h" 43 41 #include "intel_display_utils.h" 44 42 #include "intel_gmbus.h" 43 43 + #include "intel_rom.h" 45 44 46 45 #define _INTEL_BIOS_PRIVATE 47 46 #include "intel_vbt_defs.h" ··· 2528 2529 return devdata->child.edp_data_rate_override & edp_rate_override_mask(rate); 2529 2530 } 2530 2531 2532 2532 + static void sanitize_dedicated_external(struct intel_bios_encoder_data *devdata, 2533 2533 + enum port port) 2534 2534 + { 2535 2535 + struct intel_display *display = devdata->display; 2536 2536 + 2537 2537 + if (!intel_bios_encoder_is_dedicated_external(devdata)) 2538 2538 + return; 2539 2539 + 2540 2540 + /* 2541 2541 + * Since dedicated_external is for ports connected to PHYs outside of 2542 2542 + * the Type-C subsystem, clear bits that would only make sense for ports 2543 2543 + * with PHYs in the Type-C subsystem. 2544 2544 + */ 2545 2545 + 2546 2546 + /* 2547 2547 + * Bit dp_usb_type_c is marked as "don't care" in Bspec when 2548 2548 + * dedicated_external is set. 2549 2549 + */ 2550 2550 + if (devdata->child.dp_usb_type_c) { 2551 2551 + drm_dbg_kms(display->drm, 2552 2552 + "VBT claims Port %c supports USB Type-C, but the port is dedicated external, ignoring\n", 2553 2553 + port_name(port)); 2554 2554 + devdata->child.dp_usb_type_c = 0; 2555 2555 + } 2556 2556 + 2557 2557 + /* 2558 2558 + * Bit tbt is marked as "don't care" in Bspec when dedicated_external is 2559 2559 + * set. 2560 2560 + */ 2561 2561 + if (devdata->child.tbt) { 2562 2562 + drm_dbg_kms(display->drm, 2563 2563 + "VBT claims Port %c supports TBT, but the port is dedicated external, ignoring\n", 2564 2564 + port_name(port)); 2565 2565 + devdata->child.tbt = 0; 2566 2566 + } 2567 2567 + 2568 2568 + /* 2569 2569 + * DDI allocation for TC capable ports only make sense for PHYs in the 2570 2570 + * Type-C subsystem. 2571 2571 + */ 2572 2572 + if (devdata->child.dyn_port_over_tc) { 2573 2573 + drm_dbg_kms(display->drm, 2574 2574 + "VBT claims Port %c supports dynamic DDI allocation in TCSS, but the port is dedicated external, ignoring\n", 2575 2575 + port_name(port)); 2576 2576 + devdata->child.dyn_port_over_tc = 0; 2577 2577 + } 2578 2578 + } 2579 2579 + 2531 2580 static void sanitize_device_type(struct intel_bios_encoder_data *devdata, 2532 2581 enum port port) 2533 2582 { ··· 2740 2693 supports_typec_usb, supports_tbt, 2741 2694 devdata->dsc != NULL); 2742 2695 2696 2696 + if (intel_bios_encoder_is_dedicated_external(devdata)) 2697 2697 + drm_dbg_kms(display->drm, 2698 2698 + "Port %c is dedicated external\n", 2699 2699 + port_name(port)); 2700 2700 + 2701 2701 + if (intel_bios_encoder_supports_dyn_port_over_tc(devdata)) 2702 2702 + drm_dbg_kms(display->drm, 2703 2703 + "Port %c supports dynamic DDI allocation in TCSS\n", 2704 2704 + port_name(port)); 2705 2705 + 2743 2706 hdmi_level_shift = intel_bios_hdmi_level_shift(devdata); 2744 2707 if (hdmi_level_shift >= 0) { 2745 2708 drm_dbg_kms(display->drm, ··· 2807 2750 return; 2808 2751 } 2809 2752 2753 2753 + sanitize_dedicated_external(devdata, port); 2810 2754 sanitize_device_type(devdata, port); 2811 2755 sanitize_hdmi_level_shift(devdata, port); 2812 2756 } ··· 2835 2777 { 2836 2778 BUILD_BUG_ON(sizeof(struct child_device_config) < 40); 2837 2779 2838 2838 - if (version > 263) 2780 2780 + if (version > 264) 2839 2781 return -ENOENT; 2840 2782 else if (version >= 263) 2841 2783 return 44; ··· 3777 3719 bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata) 3778 3720 { 3779 3721 return devdata->display->vbt.version >= 209 && devdata->child.tbt; 3722 3722 + } 3723 3723 + 3724 3724 + bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata) 3725 3725 + { 3726 3726 + return devdata->display->vbt.version >= 264 && 3727 3727 + devdata->child.dedicated_external; 3728 3728 + } 3729 3729 + 3730 3730 + bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata) 3731 3731 + { 3732 3732 + return devdata->display->vbt.version >= 264 && 3733 3733 + devdata->child.dyn_port_over_tc; 3780 3734 } 3781 3735 3782 3736 bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata)

+2

drivers/gpu/drm/i915/display/intel_bios.h

reviewed

··· 79 79 bool intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata); 80 80 bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata); 81 81 bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata); 82 82 + bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata); 83 83 + bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata); 82 84 bool intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata); 83 85 bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata); 84 86 bool intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata);

+6

drivers/gpu/drm/i915/display/intel_bo.c

reviewed

··· 6 6 #include "gem/i915_gem_mman.h" 7 7 #include "gem/i915_gem_object.h" 8 8 #include "gem/i915_gem_object_frontbuffer.h" 9 9 + #include "pxp/intel_pxp.h" 9 10 #include "i915_debugfs.h" 10 11 #include "intel_bo.h" 11 12 ··· 28 27 bool intel_bo_is_protected(struct drm_gem_object *obj) 29 28 { 30 29 return i915_gem_object_is_protected(to_intel_bo(obj)); 30 30 + } 31 31 + 32 32 + int intel_bo_key_check(struct drm_gem_object *obj) 33 33 + { 34 34 + return intel_pxp_key_check(obj, false); 31 35 } 32 36 33 37 int intel_bo_fb_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)

+1

drivers/gpu/drm/i915/display/intel_bo.h

reviewed

··· 16 16 bool intel_bo_is_userptr(struct drm_gem_object *obj); 17 17 bool intel_bo_is_shmem(struct drm_gem_object *obj); 18 18 bool intel_bo_is_protected(struct drm_gem_object *obj); 19 19 + int intel_bo_key_check(struct drm_gem_object *obj); 19 20 int intel_bo_fb_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 20 21 int intel_bo_read_from_page(struct drm_gem_object *obj, u64 offset, void *dst, int size); 21 22

+2 -3

drivers/gpu/drm/i915/display/intel_bw.c

reviewed

··· 6 6 #include <drm/drm_atomic_state_helper.h> 7 7 #include <drm/drm_print.h> 8 8 9 9 - #include "soc/intel_dram.h" 10 10 - 11 9 #include "i915_drv.h" 12 10 #include "i915_reg.h" 13 11 #include "intel_bw.h" ··· 14 16 #include "intel_display_regs.h" 15 17 #include "intel_display_types.h" 16 18 #include "intel_display_utils.h" 19 19 + #include "intel_dram.h" 17 20 #include "intel_mchbar_regs.h" 18 21 #include "intel_pcode.h" 19 22 #include "intel_uncore.h" ··· 799 800 800 801 void intel_bw_init_hw(struct intel_display *display) 801 802 { 802 802 - const struct dram_info *dram_info = intel_dram_info(display->drm); 803 803 + const struct dram_info *dram_info = intel_dram_info(display); 803 804 804 805 if (!HAS_DISPLAY(display)) 805 806 return;

+5 -8

drivers/gpu/drm/i915/display/intel_cdclk.c

reviewed

··· 28 28 #include <drm/drm_fixed.h> 29 29 #include <drm/drm_print.h> 30 30 31 31 - #include "soc/intel_dram.h" 32 32 - 33 31 #include "hsw_ips.h" 34 34 - #include "i915_drv.h" 35 32 #include "i915_reg.h" 36 33 #include "intel_atomic.h" 37 34 #include "intel_audio.h" ··· 39 42 #include "intel_display_regs.h" 40 43 #include "intel_display_types.h" 41 44 #include "intel_display_utils.h" 45 45 + #include "intel_dram.h" 42 46 #include "intel_mchbar_regs.h" 43 47 #include "intel_pci_config.h" 44 48 #include "intel_pcode.h" 45 49 #include "intel_plane.h" 46 50 #include "intel_psr.h" 51 51 + #include "intel_step.h" 47 52 #include "intel_vdsc.h" 48 53 #include "skl_watermark.h" 49 54 #include "skl_watermark_regs.h" ··· 667 668 { 668 669 int cdclk = cdclk_config->cdclk; 669 670 u32 val, cmd = cdclk_config->voltage_level; 670 670 - intel_wakeref_t wakeref; 671 671 + struct ref_tracker *wakeref; 671 672 int ret; 672 673 673 674 switch (cdclk) { ··· 757 758 { 758 759 int cdclk = cdclk_config->cdclk; 759 760 u32 val, cmd = cdclk_config->voltage_level; 760 760 - intel_wakeref_t wakeref; 761 761 + struct ref_tracker *wakeref; 761 762 int ret; 762 763 763 764 switch (cdclk) { ··· 3737 3738 3738 3739 static int i9xx_hrawclk(struct intel_display *display) 3739 3740 { 3740 3740 - struct drm_i915_private *i915 = to_i915(display->drm); 3741 3741 - 3742 3741 /* hrawclock is 1/4 the FSB frequency */ 3743 3743 - return DIV_ROUND_CLOSEST(intel_fsb_freq(i915), 4); 3742 3742 + return DIV_ROUND_CLOSEST(intel_fsb_freq(display), 4); 3744 3743 } 3745 3744 3746 3745 /**

+1 -2

drivers/gpu/drm/i915/display/intel_cmtg.c

reviewed

··· 85 85 enum transcoder trans) 86 86 { 87 87 enum intel_display_power_domain power_domain; 88 88 - intel_wakeref_t wakeref; 89 88 u32 val = 0; 90 89 91 90 if (!HAS_TRANSCODER(display, trans)) ··· 92 93 93 94 power_domain = POWER_DOMAIN_TRANSCODER(trans); 94 95 95 95 - with_intel_display_power_if_enabled(display, power_domain, wakeref) 96 96 + with_intel_display_power_if_enabled(display, power_domain) 96 97 val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans)); 97 98 98 99 return val & CMTG_SECONDARY_MODE;

+2

drivers/gpu/drm/i915/display/intel_colorop.c

reviewed

··· 2 2 /* 3 3 * Copyright © 2025 Intel Corporation 4 4 */ 5 5 + 5 6 #include "intel_colorop.h" 7 7 + #include "intel_display_types.h" 6 8 7 9 struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop) 8 10 {

+3 -1

drivers/gpu/drm/i915/display/intel_colorop.h

reviewed

··· 6 6 #ifndef __INTEL_COLOROP_H__ 7 7 #define __INTEL_COLOROP_H__ 8 8 9 9 - #include "intel_display_types.h" 9 9 + enum intel_color_block; 10 10 + struct drm_colorop; 11 11 + struct intel_colorop; 10 12 11 13 struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop); 12 14 struct intel_colorop *intel_colorop_alloc(void);

+2 -12

drivers/gpu/drm/i915/display/intel_connector.c

reviewed

··· 156 156 int intel_connector_register(struct drm_connector *_connector) 157 157 { 158 158 struct intel_connector *connector = to_intel_connector(_connector); 159 159 - struct drm_i915_private *i915 = to_i915(_connector->dev); 160 159 int ret; 161 160 162 161 ret = intel_panel_register(connector); 163 162 if (ret) 164 164 - goto err; 165 165 - 166 166 - if (i915_inject_probe_failure(i915)) { 167 167 - ret = -EFAULT; 168 168 - goto err_panel; 169 169 - } 163 163 + return ret; 170 164 171 165 intel_connector_debugfs_add(connector); 172 166 173 167 return 0; 174 174 - 175 175 - err_panel: 176 176 - intel_panel_unregister(connector); 177 177 - err: 178 178 - return ret; 179 168 } 169 169 + ALLOW_ERROR_INJECTION(intel_connector_register, ERRNO); 180 170 181 171 void intel_connector_unregister(struct drm_connector *_connector) 182 172 {

+3 -3

drivers/gpu/drm/i915/display/intel_crt.c

reviewed

··· 109 109 { 110 110 struct intel_display *display = to_intel_display(encoder); 111 111 struct intel_crt *crt = intel_encoder_to_crt(encoder); 112 112 - intel_wakeref_t wakeref; 112 112 + struct ref_tracker *wakeref; 113 113 bool ret; 114 114 115 115 wakeref = intel_display_power_get_if_enabled(display, ··· 847 847 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 848 848 struct intel_encoder *encoder = &crt->base; 849 849 struct drm_atomic_state *state; 850 850 - intel_wakeref_t wakeref; 850 850 + struct ref_tracker *wakeref; 851 851 int status; 852 852 853 853 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n", ··· 936 936 struct intel_display *display = to_intel_display(connector->dev); 937 937 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 938 938 struct intel_encoder *encoder = &crt->base; 939 939 - intel_wakeref_t wakeref; 939 939 + struct ref_tracker *wakeref; 940 940 struct i2c_adapter *ddc; 941 941 int ret; 942 942

+23 -8

drivers/gpu/drm/i915/display/intel_crtc.c

reviewed

··· 13 13 #include <drm/drm_vblank.h> 14 14 #include <drm/drm_vblank_work.h> 15 15 16 16 - #include "i915_drv.h" 17 17 - #include "i915_vgpu.h" 18 16 #include "i9xx_plane.h" 19 17 #include "icl_dsi.h" 20 18 #include "intel_atomic.h" ··· 26 28 #include "intel_drrs.h" 27 29 #include "intel_dsi.h" 28 30 #include "intel_fifo_underrun.h" 31 31 + #include "intel_parent.h" 29 32 #include "intel_pipe_crc.h" 30 33 #include "intel_plane.h" 31 34 #include "intel_psr.h" ··· 308 309 .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, 309 310 }; 310 311 311 311 - int intel_crtc_init(struct intel_display *display, enum pipe pipe) 312 312 + static int __intel_crtc_init(struct intel_display *display, enum pipe pipe) 312 313 { 313 314 struct intel_plane *primary, *cursor; 314 315 const struct drm_crtc_funcs *funcs; ··· 395 396 396 397 drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe); 397 398 398 398 - if (HAS_CASF(display)) 399 399 + if (HAS_CASF(display) && crtc->num_scalers >= 2) 399 400 drm_crtc_create_sharpness_strength_property(&crtc->base); 400 401 401 402 return 0; ··· 404 405 intel_crtc_free(crtc); 405 406 406 407 return ret; 408 408 + } 409 409 + 410 410 + int intel_crtc_init(struct intel_display *display) 411 411 + { 412 412 + enum pipe pipe; 413 413 + int ret; 414 414 + 415 415 + drm_dbg_kms(display->drm, "%d display pipe%s available.\n", 416 416 + INTEL_NUM_PIPES(display), str_plural(INTEL_NUM_PIPES(display))); 417 417 + 418 418 + for_each_pipe(display, pipe) { 419 419 + ret = __intel_crtc_init(display, pipe); 420 420 + if (ret) 421 421 + return ret; 422 422 + } 423 423 + 424 424 + return 0; 407 425 } 408 426 409 427 int intel_crtc_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, ··· 569 553 570 554 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 571 555 new_plane_state, i) { 572 572 - if (old_plane_state->uapi.crtc == &crtc->base) 556 556 + if (old_plane_state->hw.crtc == &crtc->base) 573 557 intel_plane_init_cursor_vblank_work(old_plane_state, 574 558 new_plane_state); 575 559 } ··· 687 671 int scanline_end = intel_get_crtc_scanline(crtc); 688 672 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); 689 673 ktime_t end_vbl_time = ktime_get(); 690 690 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 691 674 692 675 drm_WARN_ON(display->drm, new_crtc_state->use_dsb); 693 676 ··· 721 706 int i; 722 707 723 708 for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { 724 724 - if (old_plane_state->uapi.crtc == &crtc->base && 709 709 + if (old_plane_state->hw.crtc == &crtc->base && 725 710 old_plane_state->unpin_work.vblank) { 726 711 drm_vblank_work_schedule(&old_plane_state->unpin_work, 727 712 drm_crtc_accurate_vblank_count(&crtc->base) + 1, ··· 752 737 753 738 local_irq_enable(); 754 739 755 755 - if (intel_vgpu_active(dev_priv)) 740 740 + if (intel_parent_vgpu_active(display)) 756 741 goto out; 757 742 758 743 if (crtc->debug.start_vbl_count &&

+1 -1

drivers/gpu/drm/i915/display/intel_crtc.h

reviewed

··· 37 37 void intel_crtc_prepare_vblank_event(struct intel_crtc_state *crtc_state, 38 38 struct drm_pending_vblank_event **event); 39 39 u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state); 40 40 - int intel_crtc_init(struct intel_display *display, enum pipe pipe); 40 40 + int intel_crtc_init(struct intel_display *display); 41 41 int intel_crtc_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, 42 42 struct drm_file *file_priv); 43 43 struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);

+3 -2

drivers/gpu/drm/i915/display/intel_cursor.c

reviewed

··· 324 324 { 325 325 struct intel_display *display = to_intel_display(plane); 326 326 enum intel_display_power_domain power_domain; 327 327 - intel_wakeref_t wakeref; 327 327 + struct ref_tracker *wakeref; 328 328 bool ret; 329 329 330 330 power_domain = POWER_DOMAIN_PIPE(PIPE_A); ··· 727 727 { 728 728 struct intel_display *display = to_intel_display(plane); 729 729 enum intel_display_power_domain power_domain; 730 730 - intel_wakeref_t wakeref; 730 730 + struct ref_tracker *wakeref; 731 731 bool ret; 732 732 u32 val; 733 733 ··· 974 974 .atomic_duplicate_state = intel_plane_duplicate_state, 975 975 .atomic_destroy_state = intel_plane_destroy_state, 976 976 .format_mod_supported = intel_cursor_format_mod_supported, 977 977 + .format_mod_supported_async = intel_plane_format_mod_supported_async, 977 978 }; 978 979 979 980 static void intel_cursor_add_size_hints_property(struct intel_plane *plane)

+617 -474

drivers/gpu/drm/i915/display/intel_cx0_phy.c

reviewed

··· 11 11 #include "intel_alpm.h" 12 12 #include "intel_cx0_phy.h" 13 13 #include "intel_cx0_phy_regs.h" 14 14 + #include "intel_display_regs.h" 14 15 #include "intel_ddi.h" 15 16 #include "intel_ddi_buf_trans.h" 16 17 #include "intel_de.h" ··· 105 104 * We also do the msgbus timer programming here to ensure that the timer 106 105 * is already programmed before any access to the msgbus. 107 106 */ 108 108 - static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder) 107 107 + static struct ref_tracker *intel_cx0_phy_transaction_begin(struct intel_encoder *encoder) 109 108 { 110 109 struct intel_display *display = to_intel_display(encoder); 111 110 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 112 112 - intel_wakeref_t wakeref; 111 111 + struct ref_tracker *wakeref; 113 112 114 113 intel_psr_pause(intel_dp); 115 114 wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); ··· 118 117 return wakeref; 119 118 } 120 119 121 121 - static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref) 120 120 + static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, struct ref_tracker *wakeref) 122 121 { 123 122 struct intel_display *display = to_intel_display(encoder); 124 123 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); ··· 445 444 } 446 445 } 447 446 447 447 + static void intel_c10_msgbus_access_begin(struct intel_encoder *encoder, 448 448 + u8 lane_mask) 449 449 + { 450 450 + if (!intel_encoder_is_c10phy(encoder)) 451 451 + return; 452 452 + 453 453 + intel_cx0_rmw(encoder, lane_mask, PHY_C10_VDR_CONTROL(1), 454 454 + 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); 455 455 + } 456 456 + 457 457 + static void intel_c10_msgbus_access_commit(struct intel_encoder *encoder, 458 458 + u8 lane_mask, bool master_lane) 459 459 + { 460 460 + u8 val = C10_VDR_CTRL_UPDATE_CFG; 461 461 + 462 462 + if (!intel_encoder_is_c10phy(encoder)) 463 463 + return; 464 464 + 465 465 + if (master_lane) 466 466 + val |= C10_VDR_CTRL_MASTER_LANE; 467 467 + 468 468 + intel_cx0_rmw(encoder, lane_mask, PHY_C10_VDR_CONTROL(1), 469 469 + 0, val, MB_WRITE_COMMITTED); 470 470 + } 471 471 + 448 472 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, 449 473 const struct intel_crtc_state *crtc_state) 450 474 { 451 475 struct intel_display *display = to_intel_display(encoder); 452 476 const struct intel_ddi_buf_trans *trans; 453 477 u8 owned_lane_mask; 454 454 - intel_wakeref_t wakeref; 478 478 + struct ref_tracker *wakeref; 455 479 int n_entries, ln; 456 480 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 457 481 ··· 493 467 return; 494 468 } 495 469 470 470 + intel_c10_msgbus_access_begin(encoder, owned_lane_mask); 471 471 + 496 472 if (intel_encoder_is_c10phy(encoder)) { 497 497 - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 498 498 - 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); 499 473 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3), 500 474 C10_CMN3_TXVBOOST_MASK, 501 475 C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)), ··· 534 508 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2, 535 509 MB_WRITE_COMMITTED); 536 510 537 537 - if (intel_encoder_is_c10phy(encoder)) 538 538 - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 539 539 - 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); 511 511 + intel_c10_msgbus_access_commit(encoder, owned_lane_mask, false); 540 512 541 513 intel_cx0_phy_transaction_end(encoder, wakeref); 542 514 } ··· 2029 2005 }; 2030 2006 2031 2007 static const struct intel_c10pll_state * const * 2032 2032 - intel_c10pll_tables_get(struct intel_crtc_state *crtc_state, 2008 2008 + intel_c10pll_tables_get(const struct intel_crtc_state *crtc_state, 2033 2009 struct intel_encoder *encoder) 2034 2010 { 2035 2011 if (intel_crtc_has_dp_encoder(crtc_state)) { ··· 2059 2035 } 2060 2036 } 2061 2037 2038 2038 + #define C10_PLL_SSC_REG_START_IDX 4 2039 2039 + #define C10_PLL_SSC_REG_COUNT 5 2040 2040 + 2041 2041 + static bool intel_c10pll_ssc_enabled(const struct intel_c10pll_state *pll_state) 2042 2042 + { 2043 2043 + return memchr_inv(&pll_state->pll[C10_PLL_SSC_REG_START_IDX], 2044 2044 + 0, sizeof(pll_state->pll[0]) * C10_PLL_SSC_REG_COUNT); 2045 2045 + } 2046 2046 + 2062 2047 static void intel_c10pll_update_pll(struct intel_encoder *encoder, 2063 2048 struct intel_cx0pll_state *pll_state) 2064 2049 { ··· 2077 2044 if (pll_state->ssc_enabled) 2078 2045 return; 2079 2046 2080 2080 - drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); 2081 2081 - for (i = 4; i < 9; i++) 2047 2047 + drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 2048 2048 + C10_PLL_SSC_REG_START_IDX + C10_PLL_SSC_REG_COUNT); 2049 2049 + for (i = C10_PLL_SSC_REG_START_IDX; 2050 2050 + i < C10_PLL_SSC_REG_START_IDX + C10_PLL_SSC_REG_COUNT; 2051 2051 + i++) 2082 2052 pll_state->c10.pll[i] = 0; 2083 2053 } 2084 2054 2055 2055 + static bool c10pll_state_is_dp(const struct intel_c10pll_state *pll_state) 2056 2056 + { 2057 2057 + return !REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); 2058 2058 + } 2059 2059 + 2060 2060 + static bool c20pll_state_is_dp(const struct intel_c20pll_state *pll_state) 2061 2061 + { 2062 2062 + return pll_state->vdr.serdes_rate & PHY_C20_IS_DP; 2063 2063 + } 2064 2064 + 2065 2065 + static bool cx0pll_state_is_dp(const struct intel_cx0pll_state *pll_state) 2066 2066 + { 2067 2067 + if (pll_state->use_c10) 2068 2068 + return c10pll_state_is_dp(&pll_state->c10); 2069 2069 + 2070 2070 + return c20pll_state_is_dp(&pll_state->c20); 2071 2071 + } 2072 2072 + 2073 2073 + /* 2074 2074 + * TODO: Convert the following to align with intel_c20pll_find_table() and 2075 2075 + * intel_c20pll_calc_state_from_table(). 2076 2076 + */ 2085 2077 static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder, 2086 2078 const struct intel_c10pll_state * const *tables, 2087 2087 - bool is_dp, int port_clock, 2079 2079 + bool is_dp, int port_clock, int lane_count, 2088 2080 struct intel_cx0pll_state *pll_state) 2089 2081 { 2082 2082 + struct intel_display *display = to_intel_display(encoder); 2090 2083 int i; 2091 2084 2092 2085 for (i = 0; tables[i]; i++) { ··· 2120 2061 pll_state->c10 = *tables[i]; 2121 2062 intel_cx0pll_update_ssc(encoder, pll_state, is_dp); 2122 2063 intel_c10pll_update_pll(encoder, pll_state); 2064 2064 + 2123 2065 pll_state->use_c10 = true; 2066 2066 + pll_state->lane_count = lane_count; 2067 2067 + 2068 2068 + drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&pll_state->c10)); 2124 2069 2125 2070 return 0; 2126 2071 } ··· 2133 2070 return -EINVAL; 2134 2071 } 2135 2072 2136 2136 - static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state, 2137 2137 - struct intel_encoder *encoder) 2073 2073 + static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state, 2074 2074 + struct intel_encoder *encoder, 2075 2075 + struct intel_dpll_hw_state *hw_state) 2138 2076 { 2077 2077 + struct intel_display *display = to_intel_display(encoder); 2078 2078 + bool is_dp = intel_crtc_has_dp_encoder(crtc_state); 2139 2079 const struct intel_c10pll_state * const *tables; 2140 2080 int err; 2141 2081 ··· 2146 2080 if (!tables) 2147 2081 return -EINVAL; 2148 2082 2149 2149 - err = intel_c10pll_calc_state_from_table(encoder, tables, 2150 2150 - intel_crtc_has_dp_encoder(crtc_state), 2151 2151 - crtc_state->port_clock, 2152 2152 - &crtc_state->dpll_hw_state.cx0pll); 2083 2083 + err = intel_c10pll_calc_state_from_table(encoder, tables, is_dp, 2084 2084 + crtc_state->port_clock, crtc_state->lane_count, 2085 2085 + &hw_state->cx0pll); 2153 2086 2154 2087 if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 2155 2088 return err; 2156 2089 2157 2090 /* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed tables */ 2158 2158 - intel_snps_hdmi_pll_compute_c10pll(&crtc_state->dpll_hw_state.cx0pll.c10, 2091 2091 + intel_snps_hdmi_pll_compute_c10pll(&hw_state->cx0pll.c10, 2159 2092 crtc_state->port_clock); 2160 2160 - intel_c10pll_update_pll(encoder, 2161 2161 - &crtc_state->dpll_hw_state.cx0pll); 2162 2162 - crtc_state->dpll_hw_state.cx0pll.use_c10 = true; 2093 2093 + intel_c10pll_update_pll(encoder, &hw_state->cx0pll); 2094 2094 + 2095 2095 + hw_state->cx0pll.use_c10 = true; 2096 2096 + hw_state->cx0pll.lane_count = crtc_state->lane_count; 2097 2097 + 2098 2098 + drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&hw_state->cx0pll.c10)); 2163 2099 2164 2100 return 0; 2165 2101 } 2166 2102 2167 2103 static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, 2168 2168 - const struct intel_c10pll_state *pll_state); 2104 2104 + const struct intel_c10pll_state *pll_state) 2105 2105 + { 2106 2106 + unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; 2107 2107 + unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400; 2108 2108 + int tmpclk = 0; 2109 2109 + 2110 2110 + if (pll_state->pll[0] & C10_PLL0_FRACEN) { 2111 2111 + frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; 2112 2112 + frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; 2113 2113 + frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; 2114 2114 + } 2115 2115 + 2116 2116 + multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | 2117 2117 + pll_state->pll[2]) / 2 + 16; 2118 2118 + 2119 2119 + tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]); 2120 2120 + hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); 2121 2121 + 2122 2122 + tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + 2123 2123 + DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), 2124 2124 + 10 << (tx_clk_div + 16)); 2125 2125 + tmpclk *= (hdmi_div ? 2 : 1); 2126 2126 + 2127 2127 + return tmpclk; 2128 2128 + } 2129 2129 + 2130 2130 + static int readout_enabled_lane_count(struct intel_encoder *encoder) 2131 2131 + { 2132 2132 + struct intel_display *display = to_intel_display(encoder); 2133 2133 + u8 enabled_tx_lane_count = 0; 2134 2134 + int max_tx_lane_count = 4; 2135 2135 + bool lane_reversal; 2136 2136 + int tx_lane; 2137 2137 + 2138 2138 + lane_reversal = intel_de_read(display, XELPDP_PORT_BUF_CTL1(display, encoder->port)) & 2139 2139 + XELPDP_PORT_REVERSAL; 2140 2140 + 2141 2141 + /* 2142 2142 + * TODO: also check inactive TX lanes in all PHY lanes owned by the 2143 2143 + * display. For now checking only those PHY lane(s) which are owned 2144 2144 + * based on the active TX lane count (i.e. 2145 2145 + * 1,2 active TX lanes -> PHY lane#0 2146 2146 + * 3,4 active TX lanes -> PHY lane#0 and PHY lane#1). 2147 2147 + * 2148 2148 + * In case of lane reversal for 1, 2 active TX lanes, only PHY 2149 2149 + * lane#1 is used. This is only possible in TypeC legacy mode or if 2150 2150 + * the port is connected to a non-TC PHY. In both of these cases both 2151 2151 + * PHY lane#0 and #1 are owned by display, so check all 4 TX lanes in 2152 2152 + * both PHY lanes in those cases. 2153 2153 + */ 2154 2154 + if (!lane_reversal) 2155 2155 + max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display, 2156 2156 + DDI_BUF_CTL(encoder->port))); 2157 2157 + 2158 2158 + if (!drm_WARN_ON(display->drm, max_tx_lane_count == 0)) 2159 2159 + max_tx_lane_count = round_up(max_tx_lane_count, 2); 2160 2160 + 2161 2161 + for (tx_lane = 0; tx_lane < max_tx_lane_count; tx_lane++) { 2162 2162 + u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; 2163 2163 + int tx = tx_lane % 2 + 1; 2164 2164 + u8 val; 2165 2165 + 2166 2166 + val = intel_cx0_read(encoder, phy_lane_mask, PHY_CX0_TX_CONTROL(tx, 2)); 2167 2167 + if (!(val & CONTROL2_DISABLE_SINGLE_TX)) 2168 2168 + enabled_tx_lane_count++; 2169 2169 + } 2170 2170 + 2171 2171 + return enabled_tx_lane_count; 2172 2172 + } 2173 2173 + 2174 2174 + static bool readout_ssc_state(struct intel_encoder *encoder, bool is_mpll_b) 2175 2175 + { 2176 2176 + struct intel_display *display = to_intel_display(encoder); 2177 2177 + 2178 2178 + return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) & 2179 2179 + (is_mpll_b ? XELPDP_SSC_ENABLE_PLLB : XELPDP_SSC_ENABLE_PLLA); 2180 2180 + } 2169 2181 2170 2182 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, 2171 2171 - struct intel_c10pll_state *pll_state) 2183 2183 + struct intel_cx0pll_state *cx0pll_state) 2172 2184 { 2185 2185 + struct intel_c10pll_state *pll_state = &cx0pll_state->c10; 2186 2186 + struct intel_display *display = to_intel_display(encoder); 2187 2187 + enum phy phy = intel_encoder_to_phy(encoder); 2173 2188 u8 lane = INTEL_CX0_LANE0; 2174 2174 - intel_wakeref_t wakeref; 2189 2189 + struct ref_tracker *wakeref; 2175 2190 int i; 2191 2191 + 2192 2192 + cx0pll_state->use_c10 = true; 2176 2193 2177 2194 wakeref = intel_cx0_phy_transaction_begin(encoder); 2178 2195 ··· 2263 2114 * According to C10 VDR Register programming Sequence we need 2264 2115 * to do this to read PHY internal registers from MsgBus. 2265 2116 */ 2266 2266 - intel_cx0_rmw(encoder, lane, PHY_C10_VDR_CONTROL(1), 2267 2267 - 0, C10_VDR_CTRL_MSGBUS_ACCESS, 2268 2268 - MB_WRITE_COMMITTED); 2117 2117 + intel_c10_msgbus_access_begin(encoder, lane); 2118 2118 + 2119 2119 + cx0pll_state->lane_count = readout_enabled_lane_count(encoder); 2269 2120 2270 2121 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) 2271 2122 pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i)); ··· 2276 2127 intel_cx0_phy_transaction_end(encoder, wakeref); 2277 2128 2278 2129 pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state); 2130 2130 + 2131 2131 + cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true); 2132 2132 + 2133 2133 + if (cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state)) 2134 2134 + drm_dbg_kms(display->drm, 2135 2135 + "PHY %c: SSC state mismatch: port SSC is %s, PLL SSC is %s\n", 2136 2136 + phy_name(phy), 2137 2137 + str_enabled_disabled(cx0pll_state->ssc_enabled), 2138 2138 + str_enabled_disabled(intel_c10pll_ssc_enabled(pll_state))); 2279 2139 } 2280 2140 2281 2141 static void intel_c10_pll_program(struct intel_display *display, ··· 2293 2135 { 2294 2136 int i; 2295 2137 2296 2296 - intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), 2297 2297 - 0, C10_VDR_CTRL_MSGBUS_ACCESS, 2298 2298 - MB_WRITE_COMMITTED); 2138 2138 + intel_c10_msgbus_access_begin(encoder, INTEL_CX0_BOTH_LANES); 2299 2139 2300 2140 /* Program the pll values only for the master lane */ 2301 2141 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) ··· 2308 2152 intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH, 2309 2153 C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10, 2310 2154 MB_WRITE_COMMITTED); 2311 2311 - intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1), 2312 2312 - 0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, 2313 2313 - MB_WRITE_COMMITTED); 2155 2155 + 2156 2156 + intel_c10_msgbus_access_commit(encoder, INTEL_CX0_LANE0, true); 2314 2157 } 2315 2158 2316 2316 - static void intel_c10pll_dump_hw_state(struct intel_display *display, 2159 2159 + static void intel_c10pll_dump_hw_state(struct drm_printer *p, 2317 2160 const struct intel_c10pll_state *hw_state) 2318 2161 { 2319 2162 bool fracen; ··· 2321 2166 unsigned int multiplier, tx_clk_div; 2322 2167 2323 2168 fracen = hw_state->pll[0] & C10_PLL0_FRACEN; 2324 2324 - drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ", 2325 2325 - str_yes_no(fracen)); 2169 2169 + drm_printf(p, "c10pll_hw_state: clock: %d, fracen: %s, ", 2170 2170 + hw_state->clock, str_yes_no(fracen)); 2326 2171 2327 2172 if (fracen) { 2328 2173 frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11]; 2329 2174 frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13]; 2330 2175 frac_den = hw_state->pll[10] << 8 | hw_state->pll[9]; 2331 2331 - drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n", 2332 2332 - frac_quot, frac_rem, frac_den); 2176 2176 + drm_printf(p, "quot: %u, rem: %u, den: %u,\n", 2177 2177 + frac_quot, frac_rem, frac_den); 2333 2178 } 2334 2179 2335 2180 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 | 2336 2181 hw_state->pll[2]) / 2 + 16; 2337 2182 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]); 2338 2338 - drm_dbg_kms(display->drm, 2339 2339 - "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div); 2183 2183 + drm_printf(p, 2184 2184 + "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div); 2340 2185 2341 2341 - drm_dbg_kms(display->drm, "c10pll_rawhw_state:"); 2342 2342 - drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, 2343 2343 - hw_state->cmn); 2186 2186 + drm_printf(p, "c10pll_rawhw_state:"); 2187 2187 + drm_printf(p, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn); 2344 2188 2345 2189 BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4); 2346 2190 for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) 2347 2347 - drm_dbg_kms(display->drm, 2348 2348 - "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", 2349 2349 - i, hw_state->pll[i], i + 1, hw_state->pll[i + 1], 2350 2350 - i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); 2191 2191 + drm_printf(p, 2192 2192 + "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", 2193 2193 + i, hw_state->pll[i], i + 1, hw_state->pll[i + 1], 2194 2194 + i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); 2351 2195 } 2352 2196 2353 2197 /* ··· 2364 2210 return pdev && IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(host_bridge_pci_dev_id); 2365 2211 } 2366 2212 2367 2367 - static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_crtc_state *crtc_state) 2213 2213 + static u16 intel_c20_hdmi_tmds_tx_cgf_1(const struct intel_crtc_state *crtc_state) 2368 2214 { 2369 2215 struct intel_display *display = to_intel_display(crtc_state); 2370 2216 u16 tx_misc; ··· 2388 2234 C20_PHY_TX_DCC_BYPASS | C20_PHY_TX_TERM_CTL(tx_term_ctrl)); 2389 2235 } 2390 2236 2391 2391 - static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state) 2237 2237 + static int intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state *crtc_state, 2238 2238 + struct intel_c20pll_state *pll_state) 2392 2239 { 2393 2393 - struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; 2394 2240 u64 datarate; 2395 2241 u64 mpll_tx_clk_div; 2396 2242 u64 vco_freq_shift; ··· 2458 2304 } 2459 2305 2460 2306 static const struct intel_c20pll_state * const * 2461 2461 - intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, 2307 2307 + intel_c20_pll_tables_get(const struct intel_crtc_state *crtc_state, 2462 2308 struct intel_encoder *encoder) 2463 2309 { 2464 2310 struct intel_display *display = to_intel_display(crtc_state); ··· 2484 2330 2485 2331 MISSING_CASE(encoder->type); 2486 2332 return NULL; 2487 2487 - } 2488 2488 - 2489 2489 - static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state, 2490 2490 - struct intel_encoder *encoder) 2491 2491 - { 2492 2492 - const struct intel_c20pll_state * const *tables; 2493 2493 - int i; 2494 2494 - 2495 2495 - /* try computed C20 HDMI tables before using consolidated tables */ 2496 2496 - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 2497 2497 - if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0) 2498 2498 - return 0; 2499 2499 - } 2500 2500 - 2501 2501 - tables = intel_c20_pll_tables_get(crtc_state, encoder); 2502 2502 - if (!tables) 2503 2503 - return -EINVAL; 2504 2504 - 2505 2505 - for (i = 0; tables[i]; i++) { 2506 2506 - if (crtc_state->port_clock == tables[i]->clock) { 2507 2507 - crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; 2508 2508 - intel_cx0pll_update_ssc(encoder, 2509 2509 - &crtc_state->dpll_hw_state.cx0pll, 2510 2510 - intel_crtc_has_dp_encoder(crtc_state)); 2511 2511 - crtc_state->dpll_hw_state.cx0pll.use_c10 = false; 2512 2512 - return 0; 2513 2513 - } 2514 2514 - } 2515 2515 - 2516 2516 - return -EINVAL; 2517 2517 - } 2518 2518 - 2519 2519 - int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, 2520 2520 - struct intel_encoder *encoder) 2521 2521 - { 2522 2522 - if (intel_encoder_is_c10phy(encoder)) 2523 2523 - return intel_c10pll_calc_state(crtc_state, encoder); 2524 2524 - return intel_c20pll_calc_state(crtc_state, encoder); 2525 2525 - } 2526 2526 - 2527 2527 - static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state) 2528 2528 - { 2529 2529 - return state->tx[0] & C20_PHY_USE_MPLLB; 2530 2530 - } 2531 2531 - 2532 2532 - static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder, 2533 2533 - const struct intel_c20pll_state *pll_state) 2534 2534 - { 2535 2535 - unsigned int frac, frac_en, frac_quot, frac_rem, frac_den; 2536 2536 - unsigned int multiplier, refclk = 38400; 2537 2537 - unsigned int tx_clk_div; 2538 2538 - unsigned int ref_clk_mpllb_div; 2539 2539 - unsigned int fb_clk_div4_en; 2540 2540 - unsigned int ref, vco; 2541 2541 - unsigned int tx_rate_mult; 2542 2542 - unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); 2543 2543 - 2544 2544 - if (intel_c20phy_use_mpllb(pll_state)) { 2545 2545 - tx_rate_mult = 1; 2546 2546 - frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); 2547 2547 - frac_quot = pll_state->mpllb[8]; 2548 2548 - frac_rem = pll_state->mpllb[9]; 2549 2549 - frac_den = pll_state->mpllb[7]; 2550 2550 - multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); 2551 2551 - tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); 2552 2552 - ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); 2553 2553 - fb_clk_div4_en = 0; 2554 2554 - } else { 2555 2555 - tx_rate_mult = 2; 2556 2556 - frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); 2557 2557 - frac_quot = pll_state->mplla[8]; 2558 2558 - frac_rem = pll_state->mplla[9]; 2559 2559 - frac_den = pll_state->mplla[7]; 2560 2560 - multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); 2561 2561 - tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); 2562 2562 - ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); 2563 2563 - fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); 2564 2564 - } 2565 2565 - 2566 2566 - if (frac_en) 2567 2567 - frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den); 2568 2568 - else 2569 2569 - frac = 0; 2570 2570 - 2571 2571 - ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div); 2572 2572 - vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10); 2573 2573 - 2574 2574 - return vco << tx_rate_mult >> tx_clk_div >> tx_rate; 2575 2575 - } 2576 2576 - 2577 2577 - static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, 2578 2578 - struct intel_c20pll_state *pll_state) 2579 2579 - { 2580 2580 - struct intel_display *display = to_intel_display(encoder); 2581 2581 - bool cntx; 2582 2582 - intel_wakeref_t wakeref; 2583 2583 - int i; 2584 2584 - 2585 2585 - wakeref = intel_cx0_phy_transaction_begin(encoder); 2586 2586 - 2587 2587 - /* 1. Read current context selection */ 2588 2588 - cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE; 2589 2589 - 2590 2590 - /* Read Tx configuration */ 2591 2591 - for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { 2592 2592 - if (cntx) 2593 2593 - pll_state->tx[i] = intel_c20_sram_read(encoder, 2594 2594 - INTEL_CX0_LANE0, 2595 2595 - PHY_C20_B_TX_CNTX_CFG(display, i)); 2596 2596 - else 2597 2597 - pll_state->tx[i] = intel_c20_sram_read(encoder, 2598 2598 - INTEL_CX0_LANE0, 2599 2599 - PHY_C20_A_TX_CNTX_CFG(display, i)); 2600 2600 - } 2601 2601 - 2602 2602 - /* Read common configuration */ 2603 2603 - for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { 2604 2604 - if (cntx) 2605 2605 - pll_state->cmn[i] = intel_c20_sram_read(encoder, 2606 2606 - INTEL_CX0_LANE0, 2607 2607 - PHY_C20_B_CMN_CNTX_CFG(display, i)); 2608 2608 - else 2609 2609 - pll_state->cmn[i] = intel_c20_sram_read(encoder, 2610 2610 - INTEL_CX0_LANE0, 2611 2611 - PHY_C20_A_CMN_CNTX_CFG(display, i)); 2612 2612 - } 2613 2613 - 2614 2614 - if (intel_c20phy_use_mpllb(pll_state)) { 2615 2615 - /* MPLLB configuration */ 2616 2616 - for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { 2617 2617 - if (cntx) 2618 2618 - pll_state->mpllb[i] = intel_c20_sram_read(encoder, 2619 2619 - INTEL_CX0_LANE0, 2620 2620 - PHY_C20_B_MPLLB_CNTX_CFG(display, i)); 2621 2621 - else 2622 2622 - pll_state->mpllb[i] = intel_c20_sram_read(encoder, 2623 2623 - INTEL_CX0_LANE0, 2624 2624 - PHY_C20_A_MPLLB_CNTX_CFG(display, i)); 2625 2625 - } 2626 2626 - } else { 2627 2627 - /* MPLLA configuration */ 2628 2628 - for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { 2629 2629 - if (cntx) 2630 2630 - pll_state->mplla[i] = intel_c20_sram_read(encoder, 2631 2631 - INTEL_CX0_LANE0, 2632 2632 - PHY_C20_B_MPLLA_CNTX_CFG(display, i)); 2633 2633 - else 2634 2634 - pll_state->mplla[i] = intel_c20_sram_read(encoder, 2635 2635 - INTEL_CX0_LANE0, 2636 2636 - PHY_C20_A_MPLLA_CNTX_CFG(display, i)); 2637 2637 - } 2638 2638 - } 2639 2639 - 2640 2640 - pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state); 2641 2641 - 2642 2642 - intel_cx0_phy_transaction_end(encoder, wakeref); 2643 2643 - } 2644 2644 - 2645 2645 - static void intel_c20pll_dump_hw_state(struct intel_display *display, 2646 2646 - const struct intel_c20pll_state *hw_state) 2647 2647 - { 2648 2648 - int i; 2649 2649 - 2650 2650 - drm_dbg_kms(display->drm, "c20pll_hw_state:\n"); 2651 2651 - drm_dbg_kms(display->drm, 2652 2652 - "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", 2653 2653 - hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); 2654 2654 - drm_dbg_kms(display->drm, 2655 2655 - "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", 2656 2656 - hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); 2657 2657 - 2658 2658 - if (intel_c20phy_use_mpllb(hw_state)) { 2659 2659 - for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) 2660 2660 - drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, 2661 2661 - hw_state->mpllb[i]); 2662 2662 - } else { 2663 2663 - for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) 2664 2664 - drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i, 2665 2665 - hw_state->mplla[i]); 2666 2666 - } 2667 2667 - } 2668 2668 - 2669 2669 - void intel_cx0pll_dump_hw_state(struct intel_display *display, 2670 2670 - const struct intel_cx0pll_state *hw_state) 2671 2671 - { 2672 2672 - if (hw_state->use_c10) 2673 2673 - intel_c10pll_dump_hw_state(display, &hw_state->c10); 2674 2674 - else 2675 2675 - intel_c20pll_dump_hw_state(display, &hw_state->c20); 2676 2333 } 2677 2334 2678 2335 static u8 intel_c20_get_dp_rate(u32 clock) ··· 2550 2585 return false; 2551 2586 } 2552 2587 2553 2553 - static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder) 2554 2554 - { 2555 2555 - struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2556 2556 - 2557 2557 - /* banks should not be cleared for DPALT/USB4/TBT modes */ 2558 2558 - /* TODO: optimize re-calibration in legacy mode */ 2559 2559 - return intel_tc_port_in_legacy_mode(intel_dig_port); 2560 2560 - } 2561 2561 - 2562 2588 static int intel_get_c20_custom_width(u32 clock, bool dp) 2563 2589 { 2564 2590 if (dp && is_dp2(clock)) ··· 2560 2604 return 0; 2561 2605 } 2562 2606 2607 2607 + static void intel_c20_calc_vdr_params(struct intel_c20pll_vdr_state *vdr, bool is_dp, 2608 2608 + int port_clock) 2609 2609 + { 2610 2610 + vdr->custom_width = intel_get_c20_custom_width(port_clock, is_dp); 2611 2611 + 2612 2612 + vdr->serdes_rate = 0; 2613 2613 + vdr->hdmi_rate = 0; 2614 2614 + 2615 2615 + if (is_dp) { 2616 2616 + vdr->serdes_rate = PHY_C20_IS_DP | 2617 2617 + PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)); 2618 2618 + } else { 2619 2619 + if (intel_hdmi_is_frl(port_clock)) 2620 2620 + vdr->serdes_rate = PHY_C20_IS_HDMI_FRL; 2621 2621 + 2622 2622 + vdr->hdmi_rate = intel_c20_get_hdmi_rate(port_clock); 2623 2623 + } 2624 2624 + } 2625 2625 + 2626 2626 + #define PHY_C20_SERDES_RATE_MASK (PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK | PHY_C20_IS_HDMI_FRL) 2627 2627 + 2628 2628 + static void intel_c20_readout_vdr_params(struct intel_encoder *encoder, 2629 2629 + struct intel_c20pll_vdr_state *vdr, bool *cntx) 2630 2630 + { 2631 2631 + u8 serdes; 2632 2632 + 2633 2633 + serdes = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE); 2634 2634 + *cntx = serdes & PHY_C20_CONTEXT_TOGGLE; 2635 2635 + 2636 2636 + vdr->custom_width = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_WIDTH) & 2637 2637 + PHY_C20_CUSTOM_WIDTH_MASK; 2638 2638 + 2639 2639 + vdr->serdes_rate = serdes & PHY_C20_SERDES_RATE_MASK; 2640 2640 + if (!(vdr->serdes_rate & PHY_C20_IS_DP)) 2641 2641 + vdr->hdmi_rate = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_HDMI_RATE) & 2642 2642 + PHY_C20_HDMI_RATE_MASK; 2643 2643 + else 2644 2644 + vdr->hdmi_rate = 0; 2645 2645 + } 2646 2646 + 2647 2647 + static void intel_c20_program_vdr_params(struct intel_encoder *encoder, 2648 2648 + const struct intel_c20pll_vdr_state *vdr, 2649 2649 + u8 owned_lane_mask) 2650 2650 + { 2651 2651 + struct intel_display *display = to_intel_display(encoder); 2652 2652 + 2653 2653 + drm_WARN_ON(display->drm, vdr->custom_width & ~PHY_C20_CUSTOM_WIDTH_MASK); 2654 2654 + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH, 2655 2655 + PHY_C20_CUSTOM_WIDTH_MASK, vdr->custom_width, 2656 2656 + MB_WRITE_COMMITTED); 2657 2657 + 2658 2658 + drm_WARN_ON(display->drm, vdr->serdes_rate & ~PHY_C20_SERDES_RATE_MASK); 2659 2659 + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, 2660 2660 + PHY_C20_SERDES_RATE_MASK, vdr->serdes_rate, 2661 2661 + MB_WRITE_COMMITTED); 2662 2662 + 2663 2663 + if (vdr->serdes_rate & PHY_C20_IS_DP) 2664 2664 + return; 2665 2665 + 2666 2666 + drm_WARN_ON(display->drm, vdr->hdmi_rate & ~PHY_C20_HDMI_RATE_MASK); 2667 2667 + intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE, 2668 2668 + PHY_C20_HDMI_RATE_MASK, vdr->hdmi_rate, 2669 2669 + MB_WRITE_COMMITTED); 2670 2670 + } 2671 2671 + 2672 2672 + static const struct intel_c20pll_state * 2673 2673 + intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state, 2674 2674 + struct intel_encoder *encoder) 2675 2675 + { 2676 2676 + const struct intel_c20pll_state * const *tables; 2677 2677 + int i; 2678 2678 + 2679 2679 + tables = intel_c20_pll_tables_get(crtc_state, encoder); 2680 2680 + if (!tables) 2681 2681 + return NULL; 2682 2682 + 2683 2683 + for (i = 0; tables[i]; i++) 2684 2684 + if (crtc_state->port_clock == tables[i]->clock) 2685 2685 + return tables[i]; 2686 2686 + 2687 2687 + return NULL; 2688 2688 + } 2689 2689 + 2690 2690 + static int intel_c20pll_calc_state_from_table(const struct intel_crtc_state *crtc_state, 2691 2691 + struct intel_encoder *encoder, 2692 2692 + struct intel_cx0pll_state *pll_state) 2693 2693 + { 2694 2694 + const struct intel_c20pll_state *table; 2695 2695 + 2696 2696 + table = intel_c20_pll_find_table(crtc_state, encoder); 2697 2697 + if (!table) 2698 2698 + return -EINVAL; 2699 2699 + 2700 2700 + pll_state->c20 = *table; 2701 2701 + 2702 2702 + intel_cx0pll_update_ssc(encoder, pll_state, intel_crtc_has_dp_encoder(crtc_state)); 2703 2703 + 2704 2704 + return 0; 2705 2705 + } 2706 2706 + 2707 2707 + static int intel_c20pll_calc_state(const struct intel_crtc_state *crtc_state, 2708 2708 + struct intel_encoder *encoder, 2709 2709 + struct intel_dpll_hw_state *hw_state) 2710 2710 + { 2711 2711 + struct intel_display *display = to_intel_display(encoder); 2712 2712 + bool is_dp = intel_crtc_has_dp_encoder(crtc_state); 2713 2713 + int err = -ENOENT; 2714 2714 + 2715 2715 + hw_state->cx0pll.use_c10 = false; 2716 2716 + hw_state->cx0pll.lane_count = crtc_state->lane_count; 2717 2717 + 2718 2718 + /* try computed C20 HDMI tables before using consolidated tables */ 2719 2719 + if (!is_dp) 2720 2720 + /* TODO: Update SSC state for HDMI as well */ 2721 2721 + err = intel_c20_compute_hdmi_tmds_pll(crtc_state, &hw_state->cx0pll.c20); 2722 2722 + 2723 2723 + if (err) 2724 2724 + err = intel_c20pll_calc_state_from_table(crtc_state, encoder, 2725 2725 + &hw_state->cx0pll); 2726 2726 + 2727 2727 + if (err) 2728 2728 + return err; 2729 2729 + 2730 2730 + intel_c20_calc_vdr_params(&hw_state->cx0pll.c20.vdr, 2731 2731 + is_dp, crtc_state->port_clock); 2732 2732 + 2733 2733 + drm_WARN_ON(display->drm, is_dp != c20pll_state_is_dp(&hw_state->cx0pll.c20)); 2734 2734 + 2735 2735 + return 0; 2736 2736 + } 2737 2737 + 2738 2738 + int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state, 2739 2739 + struct intel_encoder *encoder, 2740 2740 + struct intel_dpll_hw_state *hw_state) 2741 2741 + { 2742 2742 + memset(hw_state, 0, sizeof(*hw_state)); 2743 2743 + 2744 2744 + if (intel_encoder_is_c10phy(encoder)) 2745 2745 + return intel_c10pll_calc_state(crtc_state, encoder, hw_state); 2746 2746 + return intel_c20pll_calc_state(crtc_state, encoder, hw_state); 2747 2747 + } 2748 2748 + 2749 2749 + static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state) 2750 2750 + { 2751 2751 + return state->tx[0] & C20_PHY_USE_MPLLB; 2752 2752 + } 2753 2753 + 2754 2754 + static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder, 2755 2755 + const struct intel_c20pll_state *pll_state) 2756 2756 + { 2757 2757 + unsigned int frac, frac_en, frac_quot, frac_rem, frac_den; 2758 2758 + unsigned int multiplier, refclk = 38400; 2759 2759 + unsigned int tx_clk_div; 2760 2760 + unsigned int ref_clk_mpllb_div; 2761 2761 + unsigned int fb_clk_div4_en; 2762 2762 + unsigned int ref, vco; 2763 2763 + unsigned int tx_rate_mult; 2764 2764 + unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); 2765 2765 + 2766 2766 + if (intel_c20phy_use_mpllb(pll_state)) { 2767 2767 + tx_rate_mult = 1; 2768 2768 + frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); 2769 2769 + frac_quot = pll_state->mpllb[8]; 2770 2770 + frac_rem = pll_state->mpllb[9]; 2771 2771 + frac_den = pll_state->mpllb[7]; 2772 2772 + multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); 2773 2773 + tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); 2774 2774 + ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); 2775 2775 + fb_clk_div4_en = 0; 2776 2776 + } else { 2777 2777 + tx_rate_mult = 2; 2778 2778 + frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); 2779 2779 + frac_quot = pll_state->mplla[8]; 2780 2780 + frac_rem = pll_state->mplla[9]; 2781 2781 + frac_den = pll_state->mplla[7]; 2782 2782 + multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); 2783 2783 + tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); 2784 2784 + ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); 2785 2785 + fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); 2786 2786 + } 2787 2787 + 2788 2788 + if (frac_en) 2789 2789 + frac = frac_quot + DIV_ROUND_CLOSEST(frac_rem, frac_den); 2790 2790 + else 2791 2791 + frac = 0; 2792 2792 + 2793 2793 + ref = DIV_ROUND_CLOSEST(refclk * (1 << (1 + fb_clk_div4_en)), 1 << ref_clk_mpllb_div); 2794 2794 + vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10); 2795 2795 + 2796 2796 + return vco << tx_rate_mult >> tx_clk_div >> tx_rate; 2797 2797 + } 2798 2798 + 2799 2799 + static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, 2800 2800 + struct intel_cx0pll_state *cx0pll_state) 2801 2801 + { 2802 2802 + struct intel_c20pll_state *pll_state = &cx0pll_state->c20; 2803 2803 + struct intel_display *display = to_intel_display(encoder); 2804 2804 + bool cntx; 2805 2805 + struct ref_tracker *wakeref; 2806 2806 + int i; 2807 2807 + 2808 2808 + cx0pll_state->use_c10 = false; 2809 2809 + 2810 2810 + wakeref = intel_cx0_phy_transaction_begin(encoder); 2811 2811 + 2812 2812 + cx0pll_state->lane_count = readout_enabled_lane_count(encoder); 2813 2813 + 2814 2814 + /* 1. Read VDR params and current context selection */ 2815 2815 + intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx); 2816 2816 + 2817 2817 + /* Read Tx configuration */ 2818 2818 + for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { 2819 2819 + if (cntx) 2820 2820 + pll_state->tx[i] = intel_c20_sram_read(encoder, 2821 2821 + INTEL_CX0_LANE0, 2822 2822 + PHY_C20_B_TX_CNTX_CFG(display, i)); 2823 2823 + else 2824 2824 + pll_state->tx[i] = intel_c20_sram_read(encoder, 2825 2825 + INTEL_CX0_LANE0, 2826 2826 + PHY_C20_A_TX_CNTX_CFG(display, i)); 2827 2827 + } 2828 2828 + 2829 2829 + /* Read common configuration */ 2830 2830 + for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { 2831 2831 + if (cntx) 2832 2832 + pll_state->cmn[i] = intel_c20_sram_read(encoder, 2833 2833 + INTEL_CX0_LANE0, 2834 2834 + PHY_C20_B_CMN_CNTX_CFG(display, i)); 2835 2835 + else 2836 2836 + pll_state->cmn[i] = intel_c20_sram_read(encoder, 2837 2837 + INTEL_CX0_LANE0, 2838 2838 + PHY_C20_A_CMN_CNTX_CFG(display, i)); 2839 2839 + } 2840 2840 + 2841 2841 + if (intel_c20phy_use_mpllb(pll_state)) { 2842 2842 + /* MPLLB configuration */ 2843 2843 + for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { 2844 2844 + if (cntx) 2845 2845 + pll_state->mpllb[i] = intel_c20_sram_read(encoder, 2846 2846 + INTEL_CX0_LANE0, 2847 2847 + PHY_C20_B_MPLLB_CNTX_CFG(display, i)); 2848 2848 + else 2849 2849 + pll_state->mpllb[i] = intel_c20_sram_read(encoder, 2850 2850 + INTEL_CX0_LANE0, 2851 2851 + PHY_C20_A_MPLLB_CNTX_CFG(display, i)); 2852 2852 + } 2853 2853 + } else { 2854 2854 + /* MPLLA configuration */ 2855 2855 + for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { 2856 2856 + if (cntx) 2857 2857 + pll_state->mplla[i] = intel_c20_sram_read(encoder, 2858 2858 + INTEL_CX0_LANE0, 2859 2859 + PHY_C20_B_MPLLA_CNTX_CFG(display, i)); 2860 2860 + else 2861 2861 + pll_state->mplla[i] = intel_c20_sram_read(encoder, 2862 2862 + INTEL_CX0_LANE0, 2863 2863 + PHY_C20_A_MPLLA_CNTX_CFG(display, i)); 2864 2864 + } 2865 2865 + } 2866 2866 + 2867 2867 + pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state); 2868 2868 + 2869 2869 + intel_cx0_phy_transaction_end(encoder, wakeref); 2870 2870 + 2871 2871 + cx0pll_state->ssc_enabled = readout_ssc_state(encoder, intel_c20phy_use_mpllb(pll_state)); 2872 2872 + } 2873 2873 + 2874 2874 + static void intel_c20pll_dump_hw_state(struct drm_printer *p, 2875 2875 + const struct intel_c20pll_state *hw_state) 2876 2876 + { 2877 2877 + int i; 2878 2878 + 2879 2879 + drm_printf(p, "c20pll_hw_state: clock: %d\n", hw_state->clock); 2880 2880 + drm_printf(p, 2881 2881 + "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", 2882 2882 + hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); 2883 2883 + drm_printf(p, 2884 2884 + "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", 2885 2885 + hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); 2886 2886 + 2887 2887 + if (intel_c20phy_use_mpllb(hw_state)) { 2888 2888 + for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) 2889 2889 + drm_printf(p, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); 2890 2890 + } else { 2891 2891 + for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) 2892 2892 + drm_printf(p, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); 2893 2893 + 2894 2894 + /* For full coverage, also print the additional PLL B entry. */ 2895 2895 + BUILD_BUG_ON(ARRAY_SIZE(hw_state->mplla) + 1 != ARRAY_SIZE(hw_state->mpllb)); 2896 2896 + drm_printf(p, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); 2897 2897 + } 2898 2898 + 2899 2899 + drm_printf(p, 2900 2900 + "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n", 2901 2901 + hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate); 2902 2902 + } 2903 2903 + 2904 2904 + void intel_cx0pll_dump_hw_state(struct drm_printer *p, 2905 2905 + const struct intel_cx0pll_state *hw_state) 2906 2906 + { 2907 2907 + drm_printf(p, 2908 2908 + "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n", 2909 2909 + hw_state->lane_count, str_yes_no(hw_state->ssc_enabled), 2910 2910 + str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode)); 2911 2911 + 2912 2912 + if (hw_state->use_c10) 2913 2913 + intel_c10pll_dump_hw_state(p, &hw_state->c10); 2914 2914 + else 2915 2915 + intel_c20pll_dump_hw_state(p, &hw_state->c20); 2916 2916 + } 2917 2917 + 2918 2918 + static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder) 2919 2919 + { 2920 2920 + struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2921 2921 + 2922 2922 + /* banks should not be cleared for DPALT/USB4/TBT modes */ 2923 2923 + /* TODO: optimize re-calibration in legacy mode */ 2924 2924 + return intel_tc_port_in_legacy_mode(intel_dig_port); 2925 2925 + } 2926 2926 + 2563 2927 static void intel_c20_pll_program(struct intel_display *display, 2564 2928 struct intel_encoder *encoder, 2565 2565 - const struct intel_c20pll_state *pll_state, 2566 2566 - bool is_dp, int port_clock) 2929 2929 + const struct intel_c20pll_state *pll_state) 2567 2930 { 2568 2931 u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); 2569 2569 - u8 serdes; 2570 2932 bool cntx; 2571 2933 int i; 2572 2934 ··· 2953 2679 } 2954 2680 } 2955 2681 2956 2956 - /* 4. Program custom width to match the link protocol */ 2957 2957 - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH, 2958 2958 - PHY_C20_CUSTOM_WIDTH_MASK, 2959 2959 - PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(port_clock, is_dp)), 2960 2960 - MB_WRITE_COMMITTED); 2961 2961 - 2962 2962 - /* 5. For DP or 6. For HDMI */ 2963 2963 - serdes = 0; 2964 2964 - if (is_dp) 2965 2965 - serdes = PHY_C20_IS_DP | 2966 2966 - PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)); 2967 2967 - else if (intel_hdmi_is_frl(port_clock)) 2968 2968 - serdes = PHY_C20_IS_HDMI_FRL; 2969 2969 - 2970 2970 - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, 2971 2971 - PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK | PHY_C20_IS_HDMI_FRL, 2972 2972 - serdes, 2973 2973 - MB_WRITE_COMMITTED); 2974 2974 - 2975 2975 - if (!is_dp) 2976 2976 - intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE, 2977 2977 - PHY_C20_HDMI_RATE_MASK, 2978 2978 - intel_c20_get_hdmi_rate(port_clock), 2979 2979 - MB_WRITE_COMMITTED); 2682 2682 + /* 2683 2683 + * 4. Program custom width to match the link protocol. 2684 2684 + * 5. For DP or 6. For HDMI 2685 2685 + */ 2686 2686 + intel_c20_program_vdr_params(encoder, &pll_state->vdr, owned_lane_mask); 2980 2687 2981 2688 /* 2982 2689 * 7. Write Vendor specific registers to toggle context setting to load ··· 2968 2713 MB_WRITE_COMMITTED); 2969 2714 } 2970 2715 2971 2971 - static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, 2972 2972 - const struct intel_c10pll_state *pll_state) 2973 2973 - { 2974 2974 - unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; 2975 2975 - unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400; 2976 2976 - int tmpclk = 0; 2977 2977 - 2978 2978 - if (pll_state->pll[0] & C10_PLL0_FRACEN) { 2979 2979 - frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; 2980 2980 - frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; 2981 2981 - frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; 2982 2982 - } 2983 2983 - 2984 2984 - multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | 2985 2985 - pll_state->pll[2]) / 2 + 16; 2986 2986 - 2987 2987 - tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]); 2988 2988 - hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); 2989 2989 - 2990 2990 - tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + 2991 2991 - DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), 2992 2992 - 10 << (tx_clk_div + 16)); 2993 2993 - tmpclk *= (hdmi_div ? 2 : 1); 2994 2994 - 2995 2995 - return tmpclk; 2996 2996 - } 2997 2997 - 2998 2716 static void intel_program_port_clock_ctl(struct intel_encoder *encoder, 2999 2717 const struct intel_cx0pll_state *pll_state, 3000 3000 - bool is_dp, int port_clock, 2718 2718 + int port_clock, 3001 2719 bool lane_reversal) 3002 2720 { 3003 2721 struct intel_display *display = to_intel_display(encoder); 2722 2722 + bool is_dp = cx0pll_state_is_dp(pll_state); 3004 2723 u32 val = 0; 3005 2724 3006 2725 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), ··· 3059 2830 intel_cx0_get_powerdown_update(lane_mask), 3060 2831 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS)) 3061 2832 drm_warn(display->drm, 3062 3062 - "PHY %c failed to bring out of lane reset\n", 2833 2833 + "PHY %c failed to change powerdown state\n", 3063 2834 phy_name(phy)); 3064 2835 } 3065 2836 ··· 3167 2938 bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder)); 3168 2939 u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); 3169 2940 3170 3170 - if (intel_encoder_is_c10phy(encoder)) 3171 3171 - intel_cx0_rmw(encoder, owned_lane_mask, 3172 3172 - PHY_C10_VDR_CONTROL(1), 0, 3173 3173 - C10_VDR_CTRL_MSGBUS_ACCESS, 3174 3174 - MB_WRITE_COMMITTED); 2941 2941 + intel_c10_msgbus_access_begin(encoder, owned_lane_mask); 3175 2942 3176 2943 if (lane_reversal) 3177 2944 disables = REG_GENMASK8(3, 0) >> lane_count; ··· 3192 2967 MB_WRITE_COMMITTED); 3193 2968 } 3194 2969 3195 3195 - if (intel_encoder_is_c10phy(encoder)) 3196 3196 - intel_cx0_rmw(encoder, owned_lane_mask, 3197 3197 - PHY_C10_VDR_CONTROL(1), 0, 3198 3198 - C10_VDR_CTRL_UPDATE_CFG, 3199 3199 - MB_WRITE_COMMITTED); 2970 2970 + intel_c10_msgbus_access_commit(encoder, owned_lane_mask, false); 3200 2971 } 3201 2972 3202 2973 static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask) ··· 3217 2996 return val; 3218 2997 } 3219 2998 3220 3220 - static void __intel_cx0pll_enable(struct intel_encoder *encoder, 3221 3221 - const struct intel_cx0pll_state *pll_state, 3222 3222 - bool is_dp, int port_clock, int lane_count) 2999 2999 + static void intel_cx0pll_enable(struct intel_encoder *encoder, 3000 3000 + const struct intel_cx0pll_state *pll_state) 3223 3001 { 3002 3002 + int port_clock = pll_state->use_c10 ? pll_state->c10.clock : pll_state->c20.clock; 3224 3003 struct intel_display *display = to_intel_display(encoder); 3225 3004 enum phy phy = intel_encoder_to_phy(encoder); 3226 3005 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3227 3006 bool lane_reversal = dig_port->lane_reversal; 3228 3007 u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 : 3229 3008 INTEL_CX0_LANE0; 3230 3230 - intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); 3009 3009 + struct ref_tracker *wakeref = intel_cx0_phy_transaction_begin(encoder); 3010 3010 + 3011 3011 + /* 3012 3012 + * Lane reversal is never used in DP-alt mode, in that case the 3013 3013 + * corresponding lane swapping (based on the TypeC cable flip state 3014 3014 + * for instance) is handled automatically by the HW via a TCSS mux. 3015 3015 + */ 3016 3016 + drm_WARN_ON(display->drm, lane_reversal && intel_tc_port_in_dp_alt_mode(dig_port)); 3231 3017 3232 3018 /* 3233 3019 * 1. Program PORT_CLOCK_CTL REGISTER to configure 3234 3020 * clock muxes, gating and SSC 3235 3021 */ 3236 3236 - intel_program_port_clock_ctl(encoder, pll_state, is_dp, port_clock, lane_reversal); 3022 3022 + intel_program_port_clock_ctl(encoder, pll_state, port_clock, lane_reversal); 3237 3023 3238 3024 /* 2. Bring PHY out of reset. */ 3239 3025 intel_cx0_phy_lane_reset(encoder, lane_reversal); ··· 3262 3034 if (intel_encoder_is_c10phy(encoder)) 3263 3035 intel_c10_pll_program(display, encoder, &pll_state->c10); 3264 3036 else 3265 3265 - intel_c20_pll_program(display, encoder, &pll_state->c20, is_dp, port_clock); 3037 3037 + intel_c20_pll_program(display, encoder, &pll_state->c20); 3266 3038 3267 3039 /* 3268 3040 * 6. Program the enabled and disabled owned PHY lane 3269 3041 * transmitters over message bus 3270 3042 */ 3271 3271 - intel_cx0_program_phy_lane(encoder, lane_count, lane_reversal); 3043 3043 + intel_cx0_program_phy_lane(encoder, pll_state->lane_count, lane_reversal); 3272 3044 3273 3045 /* 3274 3046 * 7. Follow the Display Voltage Frequency Switching - Sequence ··· 3302 3074 * Frequency Change. We handle this step in bxt_set_cdclk(). 3303 3075 */ 3304 3076 3305 3305 - /* TODO: enable TBT-ALT mode */ 3077 3077 + /* 3078 3078 + * 12. Toggle powerdown if HDMI is enabled on C10 PHY. 3079 3079 + * 3080 3080 + * Wa_13013502646: 3081 3081 + * Fixes: HDMI lane to lane skew violations on C10 display PHYs. 3082 3082 + * Workaround: Toggle powerdown value by setting first to P0 and then to P2, for both 3083 3083 + * PHY lanes. 3084 3084 + */ 3085 3085 + if (!cx0pll_state_is_dp(pll_state) && pll_state->use_c10) { 3086 3086 + intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, 3087 3087 + XELPDP_P0_STATE_ACTIVE); 3088 3088 + intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, 3089 3089 + XELPDP_P2_STATE_READY); 3090 3090 + } 3091 3091 + 3306 3092 intel_cx0_phy_transaction_end(encoder, wakeref); 3307 3093 } 3308 3094 3309 3309 - static void intel_cx0pll_enable(struct intel_encoder *encoder, 3310 3310 - const struct intel_crtc_state *crtc_state) 3095 3095 + void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state) 3311 3096 { 3312 3312 - __intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll, 3313 3313 - intel_crtc_has_dp_encoder(crtc_state), 3314 3314 - crtc_state->port_clock, crtc_state->lane_count); 3097 3097 + memset(hw_state, 0, sizeof(*hw_state)); 3098 3098 + 3099 3099 + hw_state->cx0pll.tbt_mode = true; 3100 3100 + } 3101 3101 + 3102 3102 + bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display, 3103 3103 + struct intel_dpll *pll, 3104 3104 + struct intel_dpll_hw_state *hw_state) 3105 3105 + { 3106 3106 + memset(hw_state, 0, sizeof(*hw_state)); 3107 3107 + 3108 3108 + hw_state->cx0pll.tbt_mode = true; 3109 3109 + 3110 3110 + return true; 3315 3111 } 3316 3112 3317 3113 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder) ··· 3400 3148 } 3401 3149 } 3402 3150 3403 3403 - void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, 3404 3404 - const struct intel_crtc_state *crtc_state) 3151 3151 + void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, int port_clock) 3405 3152 { 3406 3153 struct intel_display *display = to_intel_display(encoder); 3407 3154 enum phy phy = intel_encoder_to_phy(encoder); ··· 3414 3163 3415 3164 mask = XELPDP_DDI_CLOCK_SELECT_MASK(display); 3416 3165 val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, 3417 3417 - intel_mtl_tbt_clock_select(display, crtc_state->port_clock)); 3166 3166 + intel_mtl_tbt_clock_select(display, port_clock)); 3418 3167 3419 3168 mask |= XELPDP_FORWARD_CLOCK_UNGATE; 3420 3169 val |= XELPDP_FORWARD_CLOCK_UNGATE; ··· 3452 3201 * clock frequency. 3453 3202 */ 3454 3203 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 3455 3455 - crtc_state->port_clock); 3204 3204 + port_clock); 3456 3205 } 3457 3206 3458 3207 void intel_mtl_pll_enable(struct intel_encoder *encoder, 3459 3459 - const struct intel_crtc_state *crtc_state) 3208 3208 + struct intel_dpll *pll, 3209 3209 + const struct intel_dpll_hw_state *dpll_hw_state) 3210 3210 + { 3211 3211 + intel_cx0pll_enable(encoder, &dpll_hw_state->cx0pll); 3212 3212 + } 3213 3213 + 3214 3214 + void intel_mtl_pll_enable_clock(struct intel_encoder *encoder, 3215 3215 + const struct intel_crtc_state *crtc_state) 3460 3216 { 3461 3217 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3462 3218 3463 3219 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 3464 3464 - intel_mtl_tbt_pll_enable(encoder, crtc_state); 3465 3465 - else 3466 3466 - intel_cx0pll_enable(encoder, crtc_state); 3220 3220 + intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock); 3467 3221 } 3468 3222 3469 3223 /* ··· 3480 3224 const struct intel_crtc_state *crtc_state) 3481 3225 { 3482 3226 struct intel_display *display = to_intel_display(encoder); 3483 3483 - intel_wakeref_t wakeref; 3227 3227 + struct ref_tracker *wakeref; 3484 3228 int i; 3485 3229 u8 owned_lane_mask; 3486 3230 ··· 3492 3236 3493 3237 wakeref = intel_cx0_phy_transaction_begin(encoder); 3494 3238 3495 3495 - if (intel_encoder_is_c10phy(encoder)) 3496 3496 - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0, 3497 3497 - C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); 3239 3239 + intel_c10_msgbus_access_begin(encoder, owned_lane_mask); 3498 3240 3499 3241 for (i = 0; i < 4; i++) { 3500 3242 int tx = i % 2 + 1; ··· 3527 3273 { 3528 3274 struct intel_display *display = to_intel_display(encoder); 3529 3275 enum phy phy = intel_encoder_to_phy(encoder); 3530 3530 - intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); 3276 3276 + struct ref_tracker *wakeref = intel_cx0_phy_transaction_begin(encoder); 3531 3277 3532 3278 /* 1. Change owned PHY lane power to Disable state. */ 3533 3279 intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, ··· 3583 3329 intel_cx0_get_pclk_pll_request(lane); 3584 3330 } 3585 3331 3586 3586 - void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) 3332 3332 + void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder) 3587 3333 { 3588 3334 struct intel_display *display = to_intel_display(encoder); 3589 3335 enum phy phy = intel_encoder_to_phy(encoder); ··· 3623 3369 3624 3370 void intel_mtl_pll_disable(struct intel_encoder *encoder) 3625 3371 { 3372 3372 + intel_cx0pll_disable(encoder); 3373 3373 + } 3374 3374 + 3375 3375 + void intel_mtl_pll_disable_clock(struct intel_encoder *encoder) 3376 3376 + { 3626 3377 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3627 3378 3628 3379 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 3629 3629 - intel_mtl_tbt_pll_disable(encoder); 3630 3630 - else 3631 3631 - intel_cx0pll_disable(encoder); 3380 3380 + intel_mtl_tbt_pll_disable_clock(encoder); 3632 3381 } 3633 3382 3634 3383 enum icl_port_dpll_id ··· 3655 3398 return ICL_PORT_DPLL_DEFAULT; 3656 3399 } 3657 3400 3658 3658 - static void intel_c10pll_state_verify(const struct intel_crtc_state *state, 3659 3659 - struct intel_crtc *crtc, 3660 3660 - struct intel_encoder *encoder, 3661 3661 - struct intel_c10pll_state *mpllb_hw_state) 3662 3662 - { 3663 3663 - struct intel_display *display = to_intel_display(state); 3664 3664 - const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10; 3665 3665 - int i; 3666 3666 - 3667 3667 - for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { 3668 3668 - u8 expected = mpllb_sw_state->pll[i]; 3669 3669 - 3670 3670 - INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->pll[i] != expected, 3671 3671 - "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", 3672 3672 - crtc->base.base.id, crtc->base.name, i, 3673 3673 - expected, mpllb_hw_state->pll[i]); 3674 3674 - } 3675 3675 - 3676 3676 - INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->tx != mpllb_sw_state->tx, 3677 3677 - "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", 3678 3678 - crtc->base.base.id, crtc->base.name, 3679 3679 - mpllb_sw_state->tx, mpllb_hw_state->tx); 3680 3680 - 3681 3681 - INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn != mpllb_sw_state->cmn, 3682 3682 - "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", 3683 3683 - crtc->base.base.id, crtc->base.name, 3684 3684 - mpllb_sw_state->cmn, mpllb_hw_state->cmn); 3685 3685 - } 3686 3686 - 3687 3687 - void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, 3401 3401 + bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, 3688 3402 struct intel_cx0pll_state *pll_state) 3689 3403 { 3690 3690 - pll_state->use_c10 = false; 3404 3404 + memset(pll_state, 0, sizeof(*pll_state)); 3691 3405 3692 3692 - pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); 3693 3693 - if (pll_state->tbt_mode) 3694 3694 - return; 3406 3406 + if (!intel_cx0_pll_is_enabled(encoder)) 3407 3407 + return false; 3695 3408 3696 3696 - if (intel_encoder_is_c10phy(encoder)) { 3697 3697 - intel_c10pll_readout_hw_state(encoder, &pll_state->c10); 3698 3698 - pll_state->use_c10 = true; 3699 3699 - } else { 3700 3700 - intel_c20pll_readout_hw_state(encoder, &pll_state->c20); 3701 3701 - } 3409 3409 + if (intel_encoder_is_c10phy(encoder)) 3410 3410 + intel_c10pll_readout_hw_state(encoder, pll_state); 3411 3411 + else 3412 3412 + intel_c20pll_readout_hw_state(encoder, pll_state); 3413 3413 + 3414 3414 + return true; 3702 3415 } 3703 3416 3704 3417 static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a, ··· 3732 3505 return intel_c20pll_calc_port_clock(encoder, &pll_state->c20); 3733 3506 } 3734 3507 3735 3735 - static void intel_c20pll_state_verify(const struct intel_crtc_state *state, 3736 3736 - struct intel_crtc *crtc, 3737 3737 - struct intel_encoder *encoder, 3738 3738 - struct intel_c20pll_state *mpll_hw_state) 3739 3739 - { 3740 3740 - struct intel_display *display = to_intel_display(state); 3741 3741 - const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20; 3742 3742 - bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state); 3743 3743 - bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state); 3744 3744 - int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state); 3745 3745 - int i; 3746 3746 - 3747 3747 - INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->clock != clock, 3748 3748 - "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)", 3749 3749 - crtc->base.base.id, crtc->base.name, 3750 3750 - mpll_sw_state->clock, mpll_hw_state->clock); 3751 3751 - 3752 3752 - INTEL_DISPLAY_STATE_WARN(display, sw_use_mpllb != hw_use_mpllb, 3753 3753 - "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)", 3754 3754 - crtc->base.base.id, crtc->base.name, 3755 3755 - sw_use_mpllb, hw_use_mpllb); 3756 3756 - 3757 3757 - if (hw_use_mpllb) { 3758 3758 - for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) { 3759 3759 - INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i], 3760 3760 - "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)", 3761 3761 - crtc->base.base.id, crtc->base.name, i, 3762 3762 - mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]); 3763 3763 - } 3764 3764 - } else { 3765 3765 - for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) { 3766 3766 - INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i], 3767 3767 - "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)", 3768 3768 - crtc->base.base.id, crtc->base.name, i, 3769 3769 - mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]); 3770 3770 - } 3771 3771 - } 3772 3772 - 3773 3773 - for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) { 3774 3774 - INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->tx[i] != mpll_sw_state->tx[i], 3775 3775 - "[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)", 3776 3776 - crtc->base.base.id, crtc->base.name, i, 3777 3777 - mpll_sw_state->tx[i], mpll_hw_state->tx[i]); 3778 3778 - } 3779 3779 - 3780 3780 - for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) { 3781 3781 - INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i], 3782 3782 - "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)", 3783 3783 - crtc->base.base.id, crtc->base.name, i, 3784 3784 - mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]); 3785 3785 - } 3786 3786 - } 3787 3787 - 3788 3788 - void intel_cx0pll_state_verify(struct intel_atomic_state *state, 3789 3789 - struct intel_crtc *crtc) 3790 3790 - { 3791 3791 - struct intel_display *display = to_intel_display(state); 3792 3792 - const struct intel_crtc_state *new_crtc_state = 3793 3793 - intel_atomic_get_new_crtc_state(state, crtc); 3794 3794 - struct intel_encoder *encoder; 3795 3795 - struct intel_cx0pll_state mpll_hw_state = {}; 3796 3796 - 3797 3797 - if (!IS_DISPLAY_VER(display, 14, 30)) 3798 3798 - return; 3799 3799 - 3800 3800 - if (!new_crtc_state->hw.active) 3801 3801 - return; 3802 3802 - 3803 3803 - /* intel_get_crtc_new_encoder() only works for modeset/fastset commits */ 3804 3804 - if (!intel_crtc_needs_modeset(new_crtc_state) && 3805 3805 - !intel_crtc_needs_fastset(new_crtc_state)) 3806 3806 - return; 3807 3807 - 3808 3808 - encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 3809 3809 - intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state); 3810 3810 - 3811 3811 - if (mpll_hw_state.tbt_mode) 3812 3812 - return; 3813 3813 - 3814 3814 - if (intel_encoder_is_c10phy(encoder)) 3815 3815 - intel_c10pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c10); 3816 3816 - else 3817 3817 - intel_c20pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c20); 3818 3818 - } 3819 3819 - 3820 3508 /* 3821 3509 * WA 14022081154 3822 3510 * The dedicated display PHYs reset to a power state that blocks S0ix, increasing idle ··· 3755 3613 for_each_intel_encoder(display->drm, encoder) { 3756 3614 struct intel_cx0pll_state pll_state = {}; 3757 3615 int port_clock = 162000; 3616 3616 + int lane_count = 4; 3758 3617 3759 3618 if (!intel_encoder_is_dig_port(encoder)) 3760 3619 continue; ··· 3768 3625 3769 3626 if (intel_c10pll_calc_state_from_table(encoder, 3770 3627 mtl_c10_edp_tables, 3771 3771 - true, port_clock, 3628 3628 + true, port_clock, lane_count, 3772 3629 &pll_state) < 0) { 3773 3630 drm_WARN_ON(display->drm, 3774 3631 "Unable to calc C10 state from the tables\n"); ··· 3779 3636 "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n", 3780 3637 encoder->base.base.id, encoder->base.name); 3781 3638 3782 3782 - __intel_cx0pll_enable(encoder, &pll_state, true, port_clock, 4); 3639 3639 + intel_cx0pll_enable(encoder, &pll_state); 3783 3640 intel_cx0pll_disable(encoder); 3784 3641 } 3785 3642 }

+23 -6

drivers/gpu/drm/i915/display/intel_cx0_phy.h

reviewed

··· 11 11 #define MB_WRITE_COMMITTED true 12 12 #define MB_WRITE_UNCOMMITTED false 13 13 14 14 + struct drm_printer; 14 15 enum icl_port_dpll_id; 15 16 struct intel_atomic_state; 16 17 struct intel_c10pll_state; ··· 20 19 struct intel_crtc_state; 21 20 struct intel_cx0pll_state; 22 21 struct intel_display; 22 22 + struct intel_dpll; 23 23 + struct intel_dpll_hw_state; 23 24 struct intel_encoder; 24 25 struct intel_hdmi; 25 26 ··· 29 26 int lane); 30 27 bool intel_encoder_is_c10phy(struct intel_encoder *encoder); 31 28 void intel_mtl_pll_enable(struct intel_encoder *encoder, 32 32 - const struct intel_crtc_state *crtc_state); 29 29 + struct intel_dpll *pll, 30 30 + const struct intel_dpll_hw_state *dpll_hw_state); 33 31 void intel_mtl_pll_disable(struct intel_encoder *encoder); 34 32 enum icl_port_dpll_id 35 33 intel_mtl_port_pll_type(struct intel_encoder *encoder, 36 34 const struct intel_crtc_state *crtc_state); 35 35 + void intel_mtl_pll_enable_clock(struct intel_encoder *encoder, 36 36 + const struct intel_crtc_state *crtc_state); 37 37 + void intel_mtl_pll_disable_clock(struct intel_encoder *encoder); 38 38 + void intel_mtl_pll_disable_clock(struct intel_encoder *encoder); 39 39 + void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, 40 40 + int port_clock); 41 41 + void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder); 37 42 38 38 - int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder); 39 39 - void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, 43 43 + int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state, 44 44 + struct intel_encoder *encoder, 45 45 + struct intel_dpll_hw_state *hw_state); 46 46 + bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, 40 47 struct intel_cx0pll_state *pll_state); 41 48 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder, 42 49 const struct intel_cx0pll_state *pll_state); 43 50 44 44 - void intel_cx0pll_dump_hw_state(struct intel_display *display, 51 51 + void intel_cx0pll_dump_hw_state(struct drm_printer *p, 45 52 const struct intel_cx0pll_state *hw_state); 46 46 - void intel_cx0pll_state_verify(struct intel_atomic_state *state, 47 47 - struct intel_crtc *crtc); 48 53 bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a, 49 54 const struct intel_cx0pll_state *b); 50 55 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, ··· 70 59 int intel_cx0_wait_for_ack(struct intel_encoder *encoder, 71 60 int command, int lane, u32 *val); 72 61 void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane); 62 62 + 63 63 + void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state); 64 64 + bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display, 65 65 + struct intel_dpll *pll, 66 66 + struct intel_dpll_hw_state *hw_state); 73 67 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder); 68 68 + 74 69 void intel_cx0_pll_power_save_wa(struct intel_display *display); 75 70 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, 76 71 const struct intel_crtc_state *crtc_state);

+89 -27

drivers/gpu/drm/i915/display/intel_ddi.c

reviewed

··· 89 89 #include "skl_scaler.h" 90 90 #include "skl_universal_plane.h" 91 91 92 92 + struct intel_dpll; 93 93 + 92 94 static const u8 index_to_dp_signal_levels[] = { 93 95 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, 94 96 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, ··· 728 726 bool enable, u32 hdcp_mask) 729 727 { 730 728 struct intel_display *display = to_intel_display(intel_encoder); 731 731 - intel_wakeref_t wakeref; 729 729 + struct ref_tracker *wakeref; 732 730 int ret = 0; 733 731 734 732 wakeref = intel_display_power_get_if_enabled(display, ··· 749 747 int type = intel_connector->base.connector_type; 750 748 enum port port = encoder->port; 751 749 enum transcoder cpu_transcoder; 752 752 - intel_wakeref_t wakeref; 750 750 + struct ref_tracker *wakeref; 753 751 enum pipe pipe = 0; 754 752 u32 ddi_mode; 755 753 bool ret; ··· 805 803 { 806 804 struct intel_display *display = to_intel_display(encoder); 807 805 enum port port = encoder->port; 808 808 - intel_wakeref_t wakeref; 806 806 + struct ref_tracker *wakeref; 809 807 enum pipe p; 810 808 u32 tmp; 811 809 u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; ··· 848 846 for_each_pipe(display, p) { 849 847 enum transcoder cpu_transcoder = (enum transcoder)p; 850 848 u32 port_mask, ddi_select, ddi_mode; 851 851 - intel_wakeref_t trans_wakeref; 849 849 + struct ref_tracker *trans_wakeref; 852 850 853 851 trans_wakeref = intel_display_power_get_if_enabled(display, 854 852 POWER_DOMAIN_TRANSCODER(cpu_transcoder)); ··· 1002 1000 struct intel_display *display = to_intel_display(dig_port); 1003 1001 enum intel_display_power_domain domain = 1004 1002 intel_ddi_main_link_aux_domain(dig_port, crtc_state); 1005 1005 - intel_wakeref_t wf; 1003 1003 + struct ref_tracker *wf; 1006 1004 1007 1005 wf = fetch_and_zero(&dig_port->aux_wakeref); 1008 1006 if (!wf) ··· 2448 2446 return; 2449 2447 } 2450 2448 2451 2451 - drm_err(display->drm, "Failed to enable FEC after retries\n"); 2449 2449 + drm_dbg_kms(display->drm, "Failed to enable FEC after retries\n"); 2452 2450 } 2453 2451 2454 2452 static void intel_ddi_disable_fec(struct intel_encoder *encoder, ··· 3130 3128 struct intel_display *display = to_intel_display(encoder); 3131 3129 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3132 3130 struct intel_dp *intel_dp = &dig_port->dp; 3133 3133 - intel_wakeref_t wakeref; 3131 3131 + struct ref_tracker *wakeref; 3134 3132 bool is_mst = intel_crtc_has_type(old_crtc_state, 3135 3133 INTEL_OUTPUT_DP_MST); 3136 3134 ··· 3198 3196 struct intel_display *display = to_intel_display(encoder); 3199 3197 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3200 3198 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3201 3201 - intel_wakeref_t wakeref; 3199 3199 + struct ref_tracker *wakeref; 3202 3200 3203 3201 dig_port->set_infoframes(encoder, false, 3204 3202 old_crtc_state, old_conn_state); ··· 3669 3667 intel_atomic_get_new_crtc_state(state, crtc); 3670 3668 struct intel_crtc *pipe_crtc; 3671 3669 3672 3672 - /* FIXME: Add MTL pll_mgr */ 3673 3673 - if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) 3670 3670 + /* FIXME: Add NVL+ and DG2 pll_mgr */ 3671 3671 + if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr) 3674 3672 return; 3675 3673 3676 3674 for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, ··· 3965 3963 3966 3964 for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { 3967 3965 enum intel_display_power_domain power_domain; 3968 3968 - intel_wakeref_t trans_wakeref; 3966 3966 + struct ref_tracker *trans_wakeref; 3969 3967 3970 3968 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3971 3969 trans_wakeref = intel_display_power_get_if_enabled(display, ··· 4257 4255 intel_ddi_get_config(encoder, crtc_state); 4258 4256 } 4259 4257 4260 4260 - static void mtl_ddi_get_config(struct intel_encoder *encoder, 4261 4261 - struct intel_crtc_state *crtc_state) 4258 4258 + static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4262 4259 { 4263 4263 - intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); 4260 4260 + return pll->info->id == DPLL_ID_ICL_TBTPLL; 4261 4261 + } 4264 4262 4265 4265 - if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) 4263 4263 + static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder, 4264 4264 + struct intel_crtc_state *crtc_state, 4265 4265 + enum icl_port_dpll_id port_dpll_id, 4266 4266 + enum intel_dpll_id pll_id) 4267 4267 + { 4268 4268 + struct intel_display *display = to_intel_display(encoder); 4269 4269 + struct icl_port_dpll *port_dpll; 4270 4270 + struct intel_dpll *pll; 4271 4271 + bool pll_active; 4272 4272 + 4273 4273 + port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; 4274 4274 + pll = intel_get_dpll_by_id(display, pll_id); 4275 4275 + 4276 4276 + if (drm_WARN_ON(display->drm, !pll)) 4277 4277 + return; 4278 4278 + 4279 4279 + port_dpll->pll = pll; 4280 4280 + pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); 4281 4281 + drm_WARN_ON(display->drm, !pll_active); 4282 4282 + 4283 4283 + icl_set_active_port_dpll(crtc_state, port_dpll_id); 4284 4284 + 4285 4285 + if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) 4266 4286 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); 4267 4287 else 4268 4268 - crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 4288 4288 + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, 4289 4289 + &crtc_state->dpll_hw_state); 4269 4290 4270 4291 intel_ddi_get_config(encoder, crtc_state); 4292 4292 + } 4293 4293 + 4294 4294 + /* 4295 4295 + * Get the configuration for either a port using a C10 PHY PLL, or a port using a 4296 4296 + * C20 PHY PLL in the cases of: 4297 4297 + * - BMG port A/B 4298 4298 + * - PTL port B eDP over TypeC PHY 4299 4299 + */ 4300 4300 + static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder, 4301 4301 + struct intel_crtc_state *crtc_state) 4302 4302 + { 4303 4303 + struct intel_display *display = to_intel_display(encoder); 4304 4304 + 4305 4305 + mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4306 4306 + mtl_port_to_pll_id(display, encoder->port)); 4307 4307 + } 4308 4308 + 4309 4309 + static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder, 4310 4310 + struct intel_crtc_state *crtc_state) 4311 4311 + { 4312 4312 + struct intel_display *display = to_intel_display(encoder); 4313 4313 + 4314 4314 + if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) 4315 4315 + mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, 4316 4316 + DPLL_ID_ICL_TBTPLL); 4317 4317 + else 4318 4318 + mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_MG_PHY, 4319 4319 + mtl_port_to_pll_id(display, encoder->port)); 4271 4320 } 4272 4321 4273 4322 static void dg2_ddi_get_config(struct intel_encoder *encoder, ··· 4356 4303 { 4357 4304 intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); 4358 4305 intel_ddi_get_config(encoder, crtc_state); 4359 4359 - } 4360 4360 - 4361 4361 - static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) 4362 4362 - { 4363 4363 - return pll->info->id == DPLL_ID_ICL_TBTPLL; 4364 4306 } 4365 4307 4366 4308 static enum icl_port_dpll_id ··· 5148 5100 port_name(port - PORT_D_XELPD + PORT_D), 5149 5101 phy_name(phy)); 5150 5102 } else if (DISPLAY_VER(display) >= 12) { 5151 5151 - enum tc_port tc_port = intel_port_to_tc(display, port); 5103 5103 + enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); 5152 5104 5153 5105 seq_buf_printf(s, "DDI %s%c/PHY %s%c", 5154 5106 port >= PORT_TC1 ? "TC" : "", ··· 5156 5108 tc_port != TC_PORT_NONE ? "TC" : "", 5157 5109 tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); 5158 5110 } else if (DISPLAY_VER(display) >= 11) { 5159 5159 - enum tc_port tc_port = intel_port_to_tc(display, port); 5111 5111 + enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); 5160 5112 5161 5113 seq_buf_printf(s, "DDI %c%s/PHY %s%c", 5162 5114 port_name(port), ··· 5300 5252 encoder->port_pll_type = intel_mtl_port_pll_type; 5301 5253 encoder->get_config = xe3plpd_ddi_get_config; 5302 5254 } else if (DISPLAY_VER(display) >= 14) { 5303 5303 - encoder->enable_clock = intel_mtl_pll_enable; 5304 5304 - encoder->disable_clock = intel_mtl_pll_disable; 5305 5305 - encoder->port_pll_type = intel_mtl_port_pll_type; 5306 5306 - encoder->get_config = mtl_ddi_get_config; 5255 5255 + encoder->enable_clock = intel_mtl_pll_enable_clock; 5256 5256 + encoder->disable_clock = intel_mtl_pll_disable_clock; 5257 5257 + encoder->port_pll_type = icl_ddi_tc_port_pll_type; 5258 5258 + if (intel_encoder_is_tc(encoder)) 5259 5259 + encoder->get_config = mtl_ddi_tc_phy_get_config; 5260 5260 + else 5261 5261 + encoder->get_config = mtl_ddi_non_tc_phy_get_config; 5307 5262 } else if (display->platform.dg2) { 5308 5263 encoder->enable_clock = intel_mpllb_enable; 5309 5264 encoder->disable_clock = intel_mpllb_disable; ··· 5422 5371 if (dig_port->aux_ch == AUX_CH_NONE) 5423 5372 goto err; 5424 5373 } 5374 5374 + 5375 5375 + /* 5376 5376 + * FIXME: We currently need to store dedicated_external because devdata 5377 5377 + * does not live long enough for when intel_encoder_is_tc() is called on 5378 5378 + * the unbind path. This needs to be fixed by making sure that the VBT 5379 5379 + * data is kept long enough, so that 5380 5380 + * intel_bios_encoder_is_dedicated_external() can be called directly 5381 5381 + * from intel_encoder_is_tc(). 5382 5382 + */ 5383 5383 + if (intel_bios_encoder_is_dedicated_external(devdata)) 5384 5384 + dig_port->dedicated_external = true; 5425 5385 5426 5386 if (intel_encoder_is_tc(encoder)) { 5427 5387 bool is_legacy =

+44 -58

drivers/gpu/drm/i915/display/intel_display.c

reviewed

··· 372 372 { 373 373 bool cur_state; 374 374 enum intel_display_power_domain power_domain; 375 375 - intel_wakeref_t wakeref; 375 375 + struct ref_tracker *wakeref; 376 376 377 377 /* we keep both pipes enabled on 830 */ 378 378 if (display->platform.i830) ··· 1810 1810 return false; 1811 1811 } 1812 1812 1813 1813 - /* Prefer intel_encoder_is_tc() */ 1813 1813 + /* 1814 1814 + * This function returns true if the DDI port respective to the PHY enumeration 1815 1815 + * is a Type-C capable port. 1816 1816 + * 1817 1817 + * Depending on the VBT, the port might be configured 1818 1818 + * as a "dedicated external" port, meaning that actual physical PHY is outside 1819 1819 + * of the Type-C subsystem and, as such, not really a "Type-C PHY". 1820 1820 + * 1821 1821 + * Prefer intel_encoder_is_tc(), especially if you really need to know if we 1822 1822 + * are dealing with Type-C connections. 1823 1823 + */ 1814 1824 bool intel_phy_is_tc(struct intel_display *display, enum phy phy) 1815 1825 { 1816 1826 /* ··· 1869 1859 } 1870 1860 1871 1861 /* Prefer intel_encoder_to_tc() */ 1862 1862 + /* 1863 1863 + * Return TC_PORT_1..I915_MAX_TC_PORTS for any TypeC DDI port. The function 1864 1864 + * can be also called for TypeC DDI ports not connected to a TypeC PHY such as 1865 1865 + * the PORT_TC1..4 ports on RKL/ADLS/BMG. 1866 1866 + */ 1872 1867 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port) 1873 1868 { 1874 1874 - if (!intel_phy_is_tc(display, intel_port_to_phy(display, port))) 1875 1875 - return TC_PORT_NONE; 1876 1876 - 1877 1869 if (DISPLAY_VER(display) >= 12) 1878 1870 return TC_PORT_1 + port - PORT_TC1; 1879 1871 else 1880 1872 return TC_PORT_1 + port - PORT_C; 1873 1873 + } 1874 1874 + 1875 1875 + /* 1876 1876 + * Return TC_PORT_1..I915_MAX_TC_PORTS for TypeC DDI ports connected to a TypeC PHY. 1877 1877 + * Note that on RKL, ADLS, BMG the PORT_TC1..4 ports are connected to a non-TypeC 1878 1878 + * PHY, so on those platforms the function returns TC_PORT_NONE. 1879 1879 + */ 1880 1880 + enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port) 1881 1881 + { 1882 1882 + if (!intel_phy_is_tc(display, intel_port_to_phy(display, port))) 1883 1883 + return TC_PORT_NONE; 1884 1884 + 1885 1885 + return intel_port_to_tc(display, port); 1881 1886 } 1882 1887 1883 1888 enum phy intel_encoder_to_phy(struct intel_encoder *encoder) ··· 1919 1894 bool intel_encoder_is_tc(struct intel_encoder *encoder) 1920 1895 { 1921 1896 struct intel_display *display = to_intel_display(encoder); 1897 1897 + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1898 1898 + 1899 1899 + if (dig_port && dig_port->dedicated_external) 1900 1900 + return false; 1922 1901 1923 1902 return intel_phy_is_tc(display, intel_encoder_to_phy(encoder)); 1924 1903 } ··· 1931 1902 { 1932 1903 struct intel_display *display = to_intel_display(encoder); 1933 1904 1934 1934 - return intel_port_to_tc(display, encoder->port); 1905 1905 + return intel_tc_phy_port_to_tc(display, encoder->port); 1935 1906 } 1936 1907 1937 1908 enum intel_display_power_domain ··· 3049 3020 struct intel_display *display = to_intel_display(crtc); 3050 3021 enum intel_display_power_domain power_domain; 3051 3022 enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; 3052 3052 - intel_wakeref_t wakeref; 3023 3023 + struct ref_tracker *wakeref; 3053 3024 bool ret = false; 3054 3025 u32 tmp; 3055 3026 ··· 3393 3364 struct intel_display *display = to_intel_display(crtc); 3394 3365 enum intel_display_power_domain power_domain; 3395 3366 enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; 3396 3396 - intel_wakeref_t wakeref; 3367 3367 + struct ref_tracker *wakeref; 3397 3368 bool ret = false; 3398 3369 u32 tmp; 3399 3370 ··· 3483 3454 enum transcoder cpu_transcoder) 3484 3455 { 3485 3456 enum intel_display_power_domain power_domain; 3486 3486 - intel_wakeref_t wakeref; 3487 3457 u32 tmp = 0; 3488 3458 3489 3459 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3490 3460 3491 3491 - with_intel_display_power_if_enabled(display, power_domain, wakeref) 3461 3461 + with_intel_display_power_if_enabled(display, power_domain) 3492 3462 tmp = intel_de_read(display, 3493 3463 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3494 3464 ··· 3509 3481 joiner_pipes(display)) { 3510 3482 enum intel_display_power_domain power_domain; 3511 3483 enum pipe pipe = crtc->pipe; 3512 3512 - intel_wakeref_t wakeref; 3513 3484 3514 3485 power_domain = POWER_DOMAIN_PIPE(pipe); 3515 3515 - with_intel_display_power_if_enabled(display, power_domain, wakeref) { 3486 3486 + with_intel_display_power_if_enabled(display, power_domain) { 3516 3487 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3517 3488 3518 3489 if (tmp & UNCOMPRESSED_JOINER_PRIMARY) ··· 3537 3510 joiner_pipes(display)) { 3538 3511 enum intel_display_power_domain power_domain; 3539 3512 enum pipe pipe = crtc->pipe; 3540 3540 - intel_wakeref_t wakeref; 3541 3513 3542 3514 power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); 3543 3543 - with_intel_display_power_if_enabled(display, power_domain, wakeref) { 3515 3515 + with_intel_display_power_if_enabled(display, power_domain) { 3544 3516 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3545 3517 3546 3518 if (!(tmp & BIG_JOINER_ENABLE)) ··· 3606 3580 joiner_pipes(display)) { 3607 3581 enum intel_display_power_domain power_domain; 3608 3582 enum pipe pipe = crtc->pipe; 3609 3609 - intel_wakeref_t wakeref; 3610 3583 3611 3584 power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); 3612 3612 - with_intel_display_power_if_enabled(display, power_domain, wakeref) { 3585 3585 + with_intel_display_power_if_enabled(display, power_domain) { 3613 3586 u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); 3614 3587 3615 3588 if (!(tmp & ULTRA_JOINER_ENABLE)) ··· 3766 3741 for_each_cpu_transcoder_masked(display, cpu_transcoder, 3767 3742 panel_transcoder_mask) { 3768 3743 enum intel_display_power_domain power_domain; 3769 3769 - intel_wakeref_t wakeref; 3770 3744 enum pipe trans_pipe; 3771 3745 u32 tmp = 0; 3772 3746 3773 3747 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 3774 3774 - with_intel_display_power_if_enabled(display, power_domain, wakeref) 3748 3748 + with_intel_display_power_if_enabled(display, power_domain) 3775 3749 tmp = intel_de_read(display, 3776 3750 TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); 3777 3751 ··· 5001 4977 intel_dpll_dump_hw_state(display, p, b); 5002 4978 } 5003 4979 5004 5004 - static void 5005 5005 - pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset, 5006 5006 - const struct intel_crtc *crtc, 5007 5007 - const char *name, 5008 5008 - const struct intel_cx0pll_state *a, 5009 5009 - const struct intel_cx0pll_state *b) 5010 5010 - { 5011 5011 - struct intel_display *display = to_intel_display(crtc); 5012 5012 - char *chipname = a->use_c10 ? "C10" : "C20"; 5013 5013 - 5014 5014 - pipe_config_mismatch(p, fastset, crtc, name, chipname); 5015 5015 - 5016 5016 - drm_printf(p, "expected:\n"); 5017 5017 - intel_cx0pll_dump_hw_state(display, a); 5018 5018 - drm_printf(p, "found:\n"); 5019 5019 - intel_cx0pll_dump_hw_state(display, b); 5020 5020 - } 5021 5021 - 5022 4980 static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state) 5023 4981 { 5024 4982 struct intel_display *display = to_intel_display(old_crtc_state); ··· 5148 5142 pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \ 5149 5143 &current_config->name, \ 5150 5144 &pipe_config->name); \ 5151 5151 - ret = false; \ 5152 5152 - } \ 5153 5153 - } while (0) 5154 5154 - 5155 5155 - #define PIPE_CONF_CHECK_PLL_CX0(name) do { \ 5156 5156 - if (!intel_cx0pll_compare_hw_state(&current_config->name, \ 5157 5157 - &pipe_config->name)) { \ 5158 5158 - pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \ 5159 5159 - &current_config->name, \ 5160 5160 - &pipe_config->name); \ 5161 5145 ret = false; \ 5162 5146 } \ 5163 5147 } while (0) ··· 5391 5395 /* FIXME convert MTL+ platforms over to dpll_mgr */ 5392 5396 if (HAS_LT_PHY(display)) 5393 5397 PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll); 5394 5394 - else if (DISPLAY_VER(display) >= 14) 5395 5395 - PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll); 5396 5398 5397 5399 PIPE_CONF_CHECK_X(dsi_pll.ctrl); 5398 5400 PIPE_CONF_CHECK_X(dsi_pll.div); ··· 6026 6032 return -EINVAL; 6027 6033 } 6028 6034 6029 6029 - /* FIXME: selective fetch should be disabled for async flips */ 6030 6030 - if (new_crtc_state->enable_psr2_sel_fetch) { 6031 6031 - drm_dbg_kms(display->drm, 6032 6032 - "[CRTC:%d:%s] async flip disallowed with PSR2 selective fetch\n", 6033 6033 - crtc->base.base.id, crtc->base.name); 6034 6034 - return -EINVAL; 6035 6035 - } 6036 6036 - 6037 6035 for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, 6038 6036 new_plane_state, i) { 6039 6037 if (plane->pipe != crtc->pipe) ··· 6116 6130 if (!plane->async_flip) 6117 6131 continue; 6118 6132 6119 6119 - if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format->format, 6133 6133 + if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format, 6120 6134 new_plane_state->hw.fb->modifier)) { 6121 6135 drm_dbg_kms(display->drm, 6122 6136 "[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip\n", ··· 7385 7399 struct intel_crtc_state *new_crtc_state, *old_crtc_state; 7386 7400 struct intel_crtc *crtc; 7387 7401 struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; 7388 7388 - intel_wakeref_t wakeref = NULL; 7402 7402 + struct ref_tracker *wakeref = NULL; 7389 7403 int i; 7390 7404 7391 7405 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)

+1

drivers/gpu/drm/i915/display/intel_display.h

reviewed

··· 451 451 bool intel_phy_is_tc(struct intel_display *display, enum phy phy); 452 452 bool intel_phy_is_snps(struct intel_display *display, enum phy phy); 453 453 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port); 454 454 + enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port); 454 455 455 456 enum phy intel_encoder_to_phy(struct intel_encoder *encoder); 456 457 bool intel_encoder_is_combo(struct intel_encoder *encoder);

+16 -2

drivers/gpu/drm/i915/display/intel_display_core.h

reviewed

··· 386 386 387 387 struct { 388 388 struct intel_dmc *dmc; 389 389 - intel_wakeref_t wakeref; 389 389 + struct ref_tracker *wakeref; 390 390 } dmc; 391 391 392 392 struct { 393 393 /* VLV/CHV/BXT/GLK DSI MMIO register base address */ 394 394 u32 mmio_base; 395 395 } dsi; 396 396 + 397 397 + struct { 398 398 + const struct dram_info *info; 399 399 + } dram; 400 400 + 401 401 + struct { 402 402 + struct intel_fbc *instances[I915_MAX_FBCS]; 403 403 + 404 404 + /* xe3p_lpd+: FBC instance utilizing the system cache */ 405 405 + struct sys_cache_cfg { 406 406 + /* Protect concurrecnt access to system cache configuration */ 407 407 + struct mutex lock; 408 408 + enum intel_fbc_id id; 409 409 + } sys_cache; 410 410 + } fbc; 396 411 397 412 struct { 398 413 /* list of fbdev register on this device */ ··· 626 611 struct drm_dp_tunnel_mgr *dp_tunnel_mgr; 627 612 struct intel_audio audio; 628 613 struct intel_dpll_global dpll; 629 629 - struct intel_fbc *fbc[I915_MAX_FBCS]; 630 614 struct intel_frontbuffer_tracking fb_tracking; 631 615 struct intel_hotplug hotplug; 632 616 struct intel_opregion *opregion;

+1 -1

drivers/gpu/drm/i915/display/intel_display_debugfs.c

reviewed

··· 86 86 static int i915_sr_status(struct seq_file *m, void *unused) 87 87 { 88 88 struct intel_display *display = node_to_intel_display(m->private); 89 89 - intel_wakeref_t wakeref; 89 89 + struct ref_tracker *wakeref; 90 90 bool sr_enabled = false; 91 91 92 92 wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);

+5

drivers/gpu/drm/i915/display/intel_display_device.c

reviewed

··· 1420 1420 } 1421 1421 }; 1422 1422 1423 1423 + static const struct platform_desc nvl_desc = { 1424 1424 + PLATFORM(novalake), 1425 1425 + }; 1426 1426 + 1423 1427 __diag_pop(); 1424 1428 1425 1429 /* ··· 1499 1495 INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc), 1500 1496 INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc), 1501 1497 INTEL_WCL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc), 1498 1498 + INTEL_NVLS_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc), 1502 1499 }; 1503 1500 1504 1501 static const struct {

+7 -2

drivers/gpu/drm/i915/display/intel_display_device.h

reviewed

··· 103 103 func(battlemage) \ 104 104 /* Display ver 30 (based on GMD ID) */ \ 105 105 func(pantherlake) \ 106 106 - func(pantherlake_wildcatlake) 106 106 + func(pantherlake_wildcatlake) \ 107 107 + /* Display ver 35 (based on GMD ID) */ \ 108 108 + func(novalake) 107 109 108 110 109 111 #define __MEMBER(name) unsigned long name:1; ··· 149 147 #define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) 150 148 #define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5) 151 149 #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13) 152 152 - #define HAS_AUX_CCS(__display) (IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake) 150 150 + #define HAS_AUX_DIST(__display) (IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake) 153 151 #define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display)) 154 152 #define HAS_CASF(__display) (DISPLAY_VER(__display) >= 20) 155 153 #define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl) ··· 175 173 #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) 176 174 #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) 177 175 #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30) 176 176 + #define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx) 178 177 #define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg) 179 178 #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3) 180 179 #define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake) ··· 188 185 #define HAS_IPS(__display) ((__display)->platform.haswell_ult || (__display)->platform.broadwell) 189 186 #define HAS_LRR(__display) (DISPLAY_VER(__display) >= 12) 190 187 #define HAS_LSPCON(__display) (IS_DISPLAY_VER(__display, 9, 10)) 188 188 + #define HAS_LT_PHY(__display) ((__display)->platform.novalake) 191 189 #define HAS_MBUS_JOINING(__display) ((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14) 192 190 #define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12) 193 191 #define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay) ··· 201 197 #define HAS_TRANSCODER(__display, trans) ((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \ 202 198 BIT(trans)) != 0) 203 199 #define HAS_UNCOMPRESSED_JOINER(__display) (DISPLAY_VER(__display) >= 13) 200 200 + #define HAS_UNDERRUN_DBG_INFO(__display) (DISPLAY_VER(__display) >= 35) 204 201 #define HAS_ULTRAJOINER(__display) (((__display)->platform.dgfx && \ 205 202 DISPLAY_VER(__display) == 14) && HAS_DSC(__display)) 206 203 #define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11)

+4 -14

drivers/gpu/drm/i915/display/intel_display_driver.c

reviewed

··· 199 199 /* part #1: call before irq install */ 200 200 int intel_display_driver_probe_noirq(struct intel_display *display) 201 201 { 202 202 - struct drm_i915_private *i915 = to_i915(display->drm); 203 202 int ret; 204 204 - 205 205 - if (i915_inject_probe_failure(i915)) 206 206 - return -ENODEV; 207 203 208 204 if (HAS_DISPLAY(display)) { 209 205 ret = drm_vblank_init(display->drm, ··· 313 317 314 318 return ret; 315 319 } 320 320 + ALLOW_ERROR_INJECTION(intel_display_driver_probe_noirq, ERRNO); 316 321 317 322 static void set_display_access(struct intel_display *display, 318 323 bool any_task_allowed, ··· 449 452 /* part #2: call after irq install, but before gem init */ 450 453 int intel_display_driver_probe_nogem(struct intel_display *display) 451 454 { 452 452 - enum pipe pipe; 453 455 int ret; 454 456 455 457 if (!HAS_DISPLAY(display)) ··· 462 466 463 467 intel_gmbus_setup(display); 464 468 465 465 - drm_dbg_kms(display->drm, "%d display pipe%s available.\n", 466 466 - INTEL_NUM_PIPES(display), 467 467 - INTEL_NUM_PIPES(display) > 1 ? "s" : ""); 468 468 - 469 469 - for_each_pipe(display, pipe) { 470 470 - ret = intel_crtc_init(display, pipe); 471 471 - if (ret) 472 472 - goto err_mode_config; 473 473 - } 469 469 + ret = intel_crtc_init(display); 470 470 + if (ret) 471 471 + goto err_mode_config; 474 472 475 473 intel_plane_possible_crtcs_init(display); 476 474 intel_dpll_init(display);

+108 -95

drivers/gpu/drm/i915/display/intel_display_irq.c

reviewed

··· 6 6 #include <drm/drm_print.h> 7 7 #include <drm/drm_vblank.h> 8 8 9 9 - #include "i915_drv.h" 10 10 - #include "i915_irq.h" 11 9 #include "i915_reg.h" 12 10 #include "icl_dsi_regs.h" 13 11 #include "intel_crtc.h" ··· 17 19 #include "intel_display_trace.h" 18 20 #include "intel_display_types.h" 19 21 #include "intel_dmc.h" 20 20 - #include "intel_dmc_wl.h" 21 22 #include "intel_dp_aux.h" 22 23 #include "intel_dsb.h" 23 24 #include "intel_fdi_regs.h" 24 25 #include "intel_fifo_underrun.h" 25 26 #include "intel_gmbus.h" 26 27 #include "intel_hotplug_irq.h" 28 28 + #include "intel_parent.h" 27 29 #include "intel_pipe_crc_regs.h" 28 30 #include "intel_plane.h" 29 31 #include "intel_pmdemand.h" 30 32 #include "intel_psr.h" 31 33 #include "intel_psr_regs.h" 32 32 - #include "intel_uncore.h" 33 34 34 34 - static void 35 35 - intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs regs, 36 36 - u32 imr_val, u32 ier_val) 35 35 + static void irq_reset(struct intel_display *display, struct i915_irq_regs regs) 37 36 { 38 38 - intel_dmc_wl_get(display, regs.imr); 39 39 - intel_dmc_wl_get(display, regs.ier); 40 40 - intel_dmc_wl_get(display, regs.iir); 37 37 + intel_de_write(display, regs.imr, 0xffffffff); 38 38 + intel_de_posting_read(display, regs.imr); 41 39 42 42 - gen2_irq_init(to_intel_uncore(display->drm), regs, imr_val, ier_val); 40 40 + intel_de_write(display, regs.ier, 0); 43 41 44 44 - intel_dmc_wl_put(display, regs.iir); 45 45 - intel_dmc_wl_put(display, regs.ier); 46 46 - intel_dmc_wl_put(display, regs.imr); 42 42 + /* IIR can theoretically queue up two events. Be paranoid. */ 43 43 + intel_de_write(display, regs.iir, 0xffffffff); 44 44 + intel_de_posting_read(display, regs.iir); 45 45 + intel_de_write(display, regs.iir, 0xffffffff); 46 46 + intel_de_posting_read(display, regs.iir); 47 47 } 48 48 49 49 - static void 50 50 - intel_display_irq_regs_reset(struct intel_display *display, struct i915_irq_regs regs) 49 49 + /* 50 50 + * We should clear IMR at preinstall/uninstall, and just check at postinstall. 51 51 + */ 52 52 + static void assert_iir_is_zero(struct intel_display *display, i915_reg_t reg) 51 53 { 52 52 - intel_dmc_wl_get(display, regs.imr); 53 53 - intel_dmc_wl_get(display, regs.ier); 54 54 - intel_dmc_wl_get(display, regs.iir); 54 54 + u32 val = intel_de_read(display, reg); 55 55 56 56 - gen2_irq_reset(to_intel_uncore(display->drm), regs); 56 56 + if (val == 0) 57 57 + return; 57 58 58 58 - intel_dmc_wl_put(display, regs.iir); 59 59 - intel_dmc_wl_put(display, regs.ier); 60 60 - intel_dmc_wl_put(display, regs.imr); 59 59 + drm_WARN(display->drm, 1, 60 60 + "Interrupt register 0x%x is not zero: 0x%08x\n", 61 61 + i915_mmio_reg_offset(reg), val); 62 62 + intel_de_write(display, reg, 0xffffffff); 63 63 + intel_de_posting_read(display, reg); 64 64 + intel_de_write(display, reg, 0xffffffff); 65 65 + intel_de_posting_read(display, reg); 61 66 } 62 67 63 63 - static void 64 64 - intel_display_irq_regs_assert_irr_is_zero(struct intel_display *display, i915_reg_t reg) 68 68 + static void irq_init(struct intel_display *display, struct i915_irq_regs regs, 69 69 + u32 imr_val, u32 ier_val) 65 70 { 66 66 - intel_dmc_wl_get(display, reg); 71 71 + assert_iir_is_zero(display, regs.iir); 67 72 68 68 - gen2_assert_iir_is_zero(to_intel_uncore(display->drm), reg); 73 73 + intel_de_write(display, regs.ier, ier_val); 74 74 + intel_de_write(display, regs.imr, imr_val); 75 75 + intel_de_posting_read(display, regs.imr); 76 76 + } 69 77 70 70 - intel_dmc_wl_put(display, reg); 78 78 + static void error_reset(struct intel_display *display, struct i915_error_regs regs) 79 79 + { 80 80 + intel_de_write(display, regs.emr, 0xffffffff); 81 81 + intel_de_posting_read(display, regs.emr); 82 82 + 83 83 + intel_de_write(display, regs.eir, 0xffffffff); 84 84 + intel_de_posting_read(display, regs.eir); 85 85 + intel_de_write(display, regs.eir, 0xffffffff); 86 86 + intel_de_posting_read(display, regs.eir); 87 87 + } 88 88 + 89 89 + static void error_init(struct intel_display *display, struct i915_error_regs regs, 90 90 + u32 emr_val) 91 91 + { 92 92 + intel_de_write(display, regs.eir, 0xffffffff); 93 93 + intel_de_posting_read(display, regs.eir); 94 94 + intel_de_write(display, regs.eir, 0xffffffff); 95 95 + intel_de_posting_read(display, regs.eir); 96 96 + 97 97 + intel_de_write(display, regs.emr, emr_val); 98 98 + intel_de_posting_read(display, regs.emr); 71 99 } 72 100 73 101 struct pipe_fault_handler { ··· 159 135 void ilk_update_display_irq(struct intel_display *display, 160 136 u32 interrupt_mask, u32 enabled_irq_mask) 161 137 { 162 162 - struct drm_i915_private *dev_priv = to_i915(display->drm); 163 138 u32 new_val; 164 139 165 140 lockdep_assert_held(&display->irq.lock); ··· 169 146 new_val |= (~enabled_irq_mask & interrupt_mask); 170 147 171 148 if (new_val != display->irq.ilk_de_imr_mask && 172 172 - !drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) { 149 149 + !drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) { 173 150 display->irq.ilk_de_imr_mask = new_val; 174 151 intel_de_write(display, DEIMR, display->irq.ilk_de_imr_mask); 175 152 intel_de_posting_read(display, DEIMR); ··· 195 172 void bdw_update_port_irq(struct intel_display *display, 196 173 u32 interrupt_mask, u32 enabled_irq_mask) 197 174 { 198 198 - struct drm_i915_private *dev_priv = to_i915(display->drm); 199 175 u32 new_val; 200 176 u32 old_val; 201 177 ··· 202 180 203 181 drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); 204 182 205 205 - if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) 183 183 + if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) 206 184 return; 207 185 208 186 old_val = intel_de_read(display, GEN8_DE_PORT_IMR); ··· 228 206 enum pipe pipe, u32 interrupt_mask, 229 207 u32 enabled_irq_mask) 230 208 { 231 231 - struct drm_i915_private *dev_priv = to_i915(display->drm); 232 209 u32 new_val; 233 210 234 211 lockdep_assert_held(&display->irq.lock); 235 212 236 213 drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); 237 214 238 238 - if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) 215 215 + if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) 239 216 return; 240 217 241 218 new_val = display->irq.de_pipe_imr_mask[pipe]; ··· 270 249 u32 interrupt_mask, 271 250 u32 enabled_irq_mask) 272 251 { 273 273 - struct drm_i915_private *dev_priv = to_i915(display->drm); 274 252 u32 sdeimr = intel_de_read(display, SDEIMR); 275 253 276 254 sdeimr &= ~interrupt_mask; ··· 279 259 280 260 lockdep_assert_held(&display->irq.lock); 281 261 282 282 - if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) 262 262 + if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) 283 263 return; 284 264 285 265 intel_de_write(display, SDEIMR, sdeimr); ··· 343 323 void i915_enable_pipestat(struct intel_display *display, 344 324 enum pipe pipe, u32 status_mask) 345 325 { 346 346 - struct drm_i915_private *dev_priv = to_i915(display->drm); 347 326 i915_reg_t reg = PIPESTAT(display, pipe); 348 327 u32 enable_mask; 349 328 ··· 351 332 pipe_name(pipe), status_mask); 352 333 353 334 lockdep_assert_held(&display->irq.lock); 354 354 - drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)); 335 335 + drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display)); 355 336 356 337 if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == status_mask) 357 338 return; ··· 366 347 void i915_disable_pipestat(struct intel_display *display, 367 348 enum pipe pipe, u32 status_mask) 368 349 { 369 369 - struct drm_i915_private *dev_priv = to_i915(display->drm); 370 350 i915_reg_t reg = PIPESTAT(display, pipe); 371 351 u32 enable_mask; 372 352 ··· 374 356 pipe_name(pipe), status_mask); 375 357 376 358 lockdep_assert_held(&display->irq.lock); 377 377 - drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)); 359 359 + drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display)); 378 360 379 361 if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == 0) 380 362 return; ··· 1936 1918 else 1937 1919 intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); 1938 1920 1939 1939 - gen2_error_reset(to_intel_uncore(display->drm), 1940 1940 - VLV_ERROR_REGS); 1921 1921 + error_reset(display, VLV_ERROR_REGS); 1941 1922 1942 1923 i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0); 1943 1924 intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0); 1944 1925 1945 1926 i9xx_pipestat_irq_reset(display); 1946 1927 1947 1947 - intel_display_irq_regs_reset(display, VLV_IRQ_REGS); 1928 1928 + irq_reset(display, VLV_IRQ_REGS); 1948 1929 display->irq.vlv_imr_mask = ~0u; 1949 1930 } 1950 1931 ··· 2031 2014 DPINVGTT_STATUS_MASK_VLV | 2032 2015 DPINVGTT_EN_MASK_VLV); 2033 2016 2034 2034 - gen2_error_init(to_intel_uncore(display->drm), 2035 2035 - VLV_ERROR_REGS, ~vlv_error_mask()); 2017 2017 + error_init(display, VLV_ERROR_REGS, ~vlv_error_mask()); 2036 2018 2037 2019 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; 2038 2020 ··· 2054 2038 2055 2039 display->irq.vlv_imr_mask = ~enable_mask; 2056 2040 2057 2057 - intel_display_irq_regs_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask); 2041 2041 + irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask); 2058 2042 } 2059 2043 2060 2044 void vlv_display_irq_postinstall(struct intel_display *display) ··· 2070 2054 if (HAS_PCH_NOP(display)) 2071 2055 return; 2072 2056 2073 2073 - gen2_irq_reset(to_intel_uncore(display->drm), SDE_IRQ_REGS); 2057 2057 + irq_reset(display, SDE_IRQ_REGS); 2074 2058 2075 2059 if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display)) 2076 2060 intel_de_write(display, SERR_INT, 0xffffffff); ··· 2078 2062 2079 2063 void ilk_display_irq_reset(struct intel_display *display) 2080 2064 { 2081 2081 - struct intel_uncore *uncore = to_intel_uncore(display->drm); 2082 2082 - 2083 2083 - gen2_irq_reset(uncore, DE_IRQ_REGS); 2065 2065 + irq_reset(display, DE_IRQ_REGS); 2084 2066 display->irq.ilk_de_imr_mask = ~0u; 2085 2067 2086 2068 if (DISPLAY_VER(display) == 7) ··· 2105 2091 for_each_pipe(display, pipe) 2106 2092 if (intel_display_power_is_enabled(display, 2107 2093 POWER_DOMAIN_PIPE(pipe))) 2108 2108 - intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2094 2094 + irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2109 2095 2110 2110 - intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); 2111 2111 - intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); 2096 2096 + irq_reset(display, GEN8_DE_PORT_IRQ_REGS); 2097 2097 + irq_reset(display, GEN8_DE_MISC_IRQ_REGS); 2112 2098 2113 2099 if (HAS_PCH_SPLIT(display)) 2114 2100 ibx_display_irq_reset(display); ··· 2150 2136 for_each_pipe(display, pipe) 2151 2137 if (intel_display_power_is_enabled(display, 2152 2138 POWER_DOMAIN_PIPE(pipe))) 2153 2153 - intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2139 2139 + irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2154 2140 2155 2155 - intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); 2156 2156 - intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); 2141 2141 + irq_reset(display, GEN8_DE_PORT_IRQ_REGS); 2142 2142 + irq_reset(display, GEN8_DE_MISC_IRQ_REGS); 2157 2143 2158 2144 if (DISPLAY_VER(display) >= 14) 2159 2159 - intel_display_irq_regs_reset(display, PICAINTERRUPT_IRQ_REGS); 2145 2145 + irq_reset(display, PICAINTERRUPT_IRQ_REGS); 2160 2146 else 2161 2161 - intel_display_irq_regs_reset(display, GEN11_DE_HPD_IRQ_REGS); 2147 2147 + irq_reset(display, GEN11_DE_HPD_IRQ_REGS); 2162 2148 2163 2149 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 2164 2164 - intel_display_irq_regs_reset(display, SDE_IRQ_REGS); 2150 2150 + irq_reset(display, SDE_IRQ_REGS); 2165 2151 } 2166 2152 2167 2153 void gen8_irq_power_well_post_enable(struct intel_display *display, 2168 2154 u8 pipe_mask) 2169 2155 { 2170 2170 - struct drm_i915_private *dev_priv = to_i915(display->drm); 2171 2156 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN | 2172 2157 gen8_de_pipe_flip_done_mask(display); 2173 2158 enum pipe pipe; 2174 2159 2175 2160 spin_lock_irq(&display->irq.lock); 2176 2161 2177 2177 - if (!intel_irqs_enabled(dev_priv)) { 2162 2162 + if (!intel_parent_irq_enabled(display)) { 2178 2163 spin_unlock_irq(&display->irq.lock); 2179 2164 return; 2180 2165 } 2181 2166 2182 2167 for_each_pipe_masked(display, pipe, pipe_mask) 2183 2183 - intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), 2184 2184 - display->irq.de_pipe_imr_mask[pipe], 2185 2185 - ~display->irq.de_pipe_imr_mask[pipe] | extra_ier); 2168 2168 + irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), 2169 2169 + display->irq.de_pipe_imr_mask[pipe], 2170 2170 + ~display->irq.de_pipe_imr_mask[pipe] | extra_ier); 2186 2171 2187 2172 spin_unlock_irq(&display->irq.lock); 2188 2173 } ··· 2189 2176 void gen8_irq_power_well_pre_disable(struct intel_display *display, 2190 2177 u8 pipe_mask) 2191 2178 { 2192 2192 - struct drm_i915_private *dev_priv = to_i915(display->drm); 2193 2179 enum pipe pipe; 2194 2180 2195 2181 spin_lock_irq(&display->irq.lock); 2196 2182 2197 2197 - if (!intel_irqs_enabled(dev_priv)) { 2183 2183 + if (!intel_parent_irq_enabled(display)) { 2198 2184 spin_unlock_irq(&display->irq.lock); 2199 2185 return; 2200 2186 } 2201 2187 2202 2188 for_each_pipe_masked(display, pipe, pipe_mask) 2203 2203 - intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2189 2189 + irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); 2204 2190 2205 2191 spin_unlock_irq(&display->irq.lock); 2206 2192 2207 2193 /* make sure we're done processing display irqs */ 2208 2208 - intel_synchronize_irq(dev_priv); 2194 2194 + intel_parent_irq_synchronize(display); 2209 2195 } 2210 2196 2211 2197 /* ··· 2232 2220 else 2233 2221 mask = SDE_GMBUS_CPT; 2234 2222 2235 2235 - intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); 2223 2223 + irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); 2236 2224 } 2237 2225 2238 2226 void valleyview_enable_display_irqs(struct intel_display *display) 2239 2227 { 2240 2240 - struct drm_i915_private *dev_priv = to_i915(display->drm); 2241 2241 - 2242 2228 spin_lock_irq(&display->irq.lock); 2243 2229 2244 2230 if (display->irq.vlv_display_irqs_enabled) ··· 2244 2234 2245 2235 display->irq.vlv_display_irqs_enabled = true; 2246 2236 2247 2247 - if (intel_irqs_enabled(dev_priv)) { 2237 2237 + if (intel_parent_irq_enabled(display)) { 2248 2238 _vlv_display_irq_reset(display); 2249 2239 _vlv_display_irq_postinstall(display); 2250 2240 } ··· 2255 2245 2256 2246 void valleyview_disable_display_irqs(struct intel_display *display) 2257 2247 { 2258 2258 - struct drm_i915_private *dev_priv = to_i915(display->drm); 2259 2259 - 2260 2248 spin_lock_irq(&display->irq.lock); 2261 2249 2262 2250 if (!display->irq.vlv_display_irqs_enabled) ··· 2262 2254 2263 2255 display->irq.vlv_display_irqs_enabled = false; 2264 2256 2265 2265 - if (intel_irqs_enabled(dev_priv)) 2257 2257 + if (intel_parent_irq_enabled(display)) 2266 2258 _vlv_display_irq_reset(display); 2267 2259 out: 2268 2260 spin_unlock_irq(&display->irq.lock); ··· 2294 2286 } 2295 2287 2296 2288 if (display->platform.haswell) { 2297 2297 - intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR); 2289 2289 + assert_iir_is_zero(display, EDP_PSR_IIR); 2298 2290 display_mask |= DE_EDP_PSR_INT_HSW; 2299 2291 } 2300 2292 ··· 2305 2297 2306 2298 ibx_irq_postinstall(display); 2307 2299 2308 2308 - intel_display_irq_regs_init(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask, 2309 2309 - display_mask | extra_mask); 2300 2300 + irq_init(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask, 2301 2301 + display_mask | extra_mask); 2310 2302 } 2311 2303 2312 2304 static void mtp_irq_postinstall(struct intel_display *display); ··· 2382 2374 if (!intel_display_power_is_enabled(display, domain)) 2383 2375 continue; 2384 2376 2385 2385 - intel_display_irq_regs_assert_irr_is_zero(display, 2386 2386 - TRANS_PSR_IIR(display, trans)); 2377 2377 + assert_iir_is_zero(display, TRANS_PSR_IIR(display, trans)); 2387 2378 } 2388 2379 } else { 2389 2389 - intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR); 2380 2380 + assert_iir_is_zero(display, EDP_PSR_IIR); 2390 2381 } 2391 2382 2392 2383 for_each_pipe(display, pipe) { ··· 2393 2386 2394 2387 if (intel_display_power_is_enabled(display, 2395 2388 POWER_DOMAIN_PIPE(pipe))) 2396 2396 - intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), 2397 2397 - display->irq.de_pipe_imr_mask[pipe], 2398 2398 - de_pipe_enables); 2389 2389 + irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), 2390 2390 + display->irq.de_pipe_imr_mask[pipe], 2391 2391 + de_pipe_enables); 2399 2392 } 2400 2393 2401 2401 - intel_display_irq_regs_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, 2402 2402 - de_port_enables); 2403 2403 - intel_display_irq_regs_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, 2404 2404 - de_misc_masked); 2394 2394 + irq_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables); 2395 2395 + irq_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked); 2405 2396 2406 2397 if (IS_DISPLAY_VER(display, 11, 13)) { 2407 2398 u32 de_hpd_masked = 0; 2408 2399 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | 2409 2400 GEN11_DE_TBT_HOTPLUG_MASK; 2410 2401 2411 2411 - intel_display_irq_regs_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, 2412 2412 - de_hpd_enables); 2402 2402 + irq_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, de_hpd_enables); 2413 2403 } 2404 2404 + } 2405 2405 + 2406 2406 + u32 xelpdp_pica_aux_mask(struct intel_display *display) 2407 2407 + { 2408 2408 + u32 mask = XELPDP_AUX_TC_MASK; 2409 2409 + 2410 2410 + if (DISPLAY_VER(display) >= 20) 2411 2411 + mask |= XE2LPD_AUX_DDI_MASK; 2412 2412 + 2413 2413 + return mask; 2414 2414 } 2415 2415 2416 2416 static void mtp_irq_postinstall(struct intel_display *display) 2417 2417 { 2418 2418 u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT; 2419 2419 - u32 de_hpd_mask = XELPDP_AUX_TC_MASK; 2419 2419 + u32 de_hpd_mask = xelpdp_pica_aux_mask(display); 2420 2420 u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK | 2421 2421 XELPDP_TBT_HOTPLUG_MASK; 2422 2422 2423 2423 - intel_display_irq_regs_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, 2424 2424 - de_hpd_enables); 2423 2423 + irq_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, de_hpd_enables); 2425 2424 2426 2426 - intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff); 2425 2425 + irq_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff); 2427 2426 } 2428 2427 2429 2428 static void icp_irq_postinstall(struct intel_display *display) 2430 2429 { 2431 2430 u32 mask = SDE_GMBUS_ICP; 2432 2431 2433 2433 - intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); 2432 2432 + irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); 2434 2433 } 2435 2434 2436 2435 void gen11_de_irq_postinstall(struct intel_display *display)

+2

drivers/gpu/drm/i915/display/intel_display_irq.h

reviewed

··· 16 16 struct intel_display; 17 17 struct intel_display_irq_snapshot; 18 18 19 19 + u32 xelpdp_pica_aux_mask(struct intel_display *display); 20 20 + 19 21 void valleyview_enable_display_irqs(struct intel_display *display); 20 22 void valleyview_disable_display_irqs(struct intel_display *display); 21 23

+22 -26

drivers/gpu/drm/i915/display/intel_display_power.c

reviewed

··· 8 8 9 9 #include <drm/drm_print.h> 10 10 11 11 - #include "soc/intel_dram.h" 12 12 - 13 11 #include "i915_drv.h" 14 14 - #include "i915_irq.h" 15 12 #include "i915_reg.h" 16 13 #include "intel_backlight_regs.h" 17 14 #include "intel_cdclk.h" ··· 23 26 #include "intel_display_types.h" 24 27 #include "intel_display_utils.h" 25 28 #include "intel_dmc.h" 29 29 + #include "intel_dram.h" 26 30 #include "intel_mchbar_regs.h" 31 31 + #include "intel_parent.h" 27 32 #include "intel_pch_refclk.h" 28 33 #include "intel_pcode.h" 29 34 #include "intel_pmdemand.h" ··· 544 545 * Any power domain reference obtained by this function must have a symmetric 545 546 * call to intel_display_power_put() to release the reference again. 546 547 */ 547 547 - intel_wakeref_t intel_display_power_get(struct intel_display *display, 548 548 - enum intel_display_power_domain domain) 548 548 + struct ref_tracker *intel_display_power_get(struct intel_display *display, 549 549 + enum intel_display_power_domain domain) 549 550 { 550 551 struct i915_power_domains *power_domains = &display->power.domains; 551 552 struct ref_tracker *wakeref; ··· 571 572 * Any power domain reference obtained by this function must have a symmetric 572 573 * call to intel_display_power_put() to release the reference again. 573 574 */ 574 574 - intel_wakeref_t 575 575 + struct ref_tracker * 575 576 intel_display_power_get_if_enabled(struct intel_display *display, 576 577 enum intel_display_power_domain domain) 577 578 { ··· 638 639 639 640 static void 640 641 queue_async_put_domains_work(struct i915_power_domains *power_domains, 641 641 - intel_wakeref_t wakeref, 642 642 + struct ref_tracker *wakeref, 642 643 int delay_ms) 643 644 { 644 645 struct intel_display *display = container_of(power_domains, ··· 740 741 */ 741 742 void __intel_display_power_put_async(struct intel_display *display, 742 743 enum intel_display_power_domain domain, 743 743 - intel_wakeref_t wakeref, 744 744 + struct ref_tracker *wakeref, 744 745 int delay_ms) 745 746 { 746 747 struct i915_power_domains *power_domains = &display->power.domains; ··· 799 800 { 800 801 struct i915_power_domains *power_domains = &display->power.domains; 801 802 struct intel_power_domain_mask async_put_mask; 802 802 - intel_wakeref_t work_wakeref; 803 803 + struct ref_tracker *work_wakeref; 803 804 804 805 mutex_lock(&power_domains->lock); 805 806 ··· 853 854 */ 854 855 void intel_display_power_put(struct intel_display *display, 855 856 enum intel_display_power_domain domain, 856 856 - intel_wakeref_t wakeref) 857 857 + struct ref_tracker *wakeref) 857 858 { 858 859 __intel_display_power_put(display, domain); 859 860 intel_display_rpm_put(display, wakeref); ··· 885 886 struct intel_display_power_domain_set *power_domain_set, 886 887 enum intel_display_power_domain domain) 887 888 { 888 888 - intel_wakeref_t __maybe_unused wf; 889 889 + struct ref_tracker *__maybe_unused wf; 889 890 890 891 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); 891 892 ··· 901 902 struct intel_display_power_domain_set *power_domain_set, 902 903 enum intel_display_power_domain domain) 903 904 { 904 904 - intel_wakeref_t wf; 905 905 + struct ref_tracker *wf; 905 906 906 907 drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); 907 908 ··· 928 929 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM)); 929 930 930 931 for_each_power_domain(domain, mask) { 931 931 - intel_wakeref_t __maybe_unused wf = INTEL_WAKEREF_DEF; 932 932 + struct ref_tracker *__maybe_unused wf = INTEL_WAKEREF_DEF; 932 933 933 934 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 934 935 wf = fetch_and_zero(&power_domain_set->wakerefs[domain]); ··· 1201 1202 1202 1203 static void assert_can_disable_lcpll(struct intel_display *display) 1203 1204 { 1204 1204 - struct drm_i915_private *dev_priv = to_i915(display->drm); 1205 1205 struct intel_crtc *crtc; 1206 1206 1207 1207 for_each_intel_crtc(display->drm, crtc) ··· 1245 1247 * gen-specific and since we only disable LCPLL after we fully disable 1246 1248 * the interrupts, the check below should be enough. 1247 1249 */ 1248 1248 - INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv), 1250 1250 + INTEL_DISPLAY_STATE_WARN(display, intel_parent_irq_enabled(display), 1249 1251 "IRQs enabled\n"); 1250 1252 } 1251 1253 ··· 1339 1341 return; 1340 1342 1341 1343 /* 1342 1342 - * Make sure we're not on PC8 state before disabling PC8, otherwise 1343 1343 - * we'll hang the machine. To prevent PC8 state, just enable force_wake. 1344 1344 + * Make sure we're not on PC8 state before disabling 1345 1345 + * PC8, otherwise we'll hang the machine. 1344 1346 */ 1345 1345 - intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); 1347 1347 + intel_parent_pc8_block(display); 1346 1348 1347 1349 if (val & LCPLL_POWER_DOWN_ALLOW) { 1348 1350 val &= ~LCPLL_POWER_DOWN_ALLOW; ··· 1372 1374 "Switching back to LCPLL failed\n"); 1373 1375 } 1374 1376 1375 1375 - intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); 1377 1377 + intel_parent_pc8_unblock(display); 1376 1378 1377 1379 intel_update_cdclk(display); 1378 1380 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); ··· 1415 1417 1416 1418 static void hsw_disable_pc8(struct intel_display *display) 1417 1419 { 1418 1418 - struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); 1419 1419 - 1420 1420 drm_dbg_kms(display->drm, "Disabling package C8+\n"); 1421 1421 1422 1422 hsw_restore_lcpll(display); ··· 1422 1426 1423 1427 /* Many display registers don't survive PC8+ */ 1424 1428 #ifdef I915 /* FIXME */ 1425 1425 - intel_clock_gating_init(dev_priv); 1429 1429 + intel_clock_gating_init(display->drm); 1426 1430 #endif 1427 1431 } 1428 1432 ··· 1614 1618 1615 1619 static void tgl_bw_buddy_init(struct intel_display *display) 1616 1620 { 1617 1617 - const struct dram_info *dram_info = intel_dram_info(display->drm); 1621 1621 + const struct dram_info *dram_info = intel_dram_info(display); 1618 1622 const struct buddy_page_mask *table; 1619 1623 unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; 1620 1624 int config, i; ··· 2002 2006 */ 2003 2007 void intel_power_domains_driver_remove(struct intel_display *display) 2004 2008 { 2005 2005 - intel_wakeref_t wakeref __maybe_unused = 2009 2009 + struct ref_tracker *wakeref __maybe_unused = 2006 2010 fetch_and_zero(&display->power.domains.init_wakeref); 2007 2011 2008 2012 /* Remove the refcount we took to keep power well support disabled. */ ··· 2063 2067 */ 2064 2068 void intel_power_domains_enable(struct intel_display *display) 2065 2069 { 2066 2066 - intel_wakeref_t wakeref __maybe_unused = 2070 2070 + struct ref_tracker *wakeref __maybe_unused = 2067 2071 fetch_and_zero(&display->power.domains.init_wakeref); 2068 2072 2069 2073 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); ··· 2102 2106 void intel_power_domains_suspend(struct intel_display *display, bool s2idle) 2103 2107 { 2104 2108 struct i915_power_domains *power_domains = &display->power.domains; 2105 2105 - intel_wakeref_t wakeref __maybe_unused = 2109 2109 + struct ref_tracker *wakeref __maybe_unused = 2106 2110 fetch_and_zero(&power_domains->init_wakeref); 2107 2111 2108 2112 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

+28 -20

drivers/gpu/drm/i915/display/intel_display_power.h

reviewed

··· 9 9 #include <linux/mutex.h> 10 10 #include <linux/workqueue.h> 11 11 12 12 - #include "intel_wakeref.h" 13 13 - 14 12 enum aux_ch; 15 13 enum port; 16 14 struct i915_power_well; 17 15 struct intel_display; 18 16 struct intel_encoder; 17 17 + struct ref_tracker; 19 18 struct seq_file; 19 19 + 20 20 + /* -ENOENT means we got the ref, but there's no tracking */ 21 21 + #define INTEL_WAKEREF_DEF ERR_PTR(-ENOENT) 20 22 21 23 /* 22 24 * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances ··· 144 142 u32 target_dc_state; 145 143 u32 allowed_dc_mask; 146 144 147 147 - intel_wakeref_t init_wakeref; 148 148 - intel_wakeref_t disable_wakeref; 145 145 + struct ref_tracker *init_wakeref; 146 146 + struct ref_tracker *disable_wakeref; 149 147 150 148 struct mutex lock; 151 149 int domain_use_count[POWER_DOMAIN_NUM]; 152 150 153 151 struct delayed_work async_put_work; 154 154 - intel_wakeref_t async_put_wakeref; 152 152 + struct ref_tracker *async_put_wakeref; 155 153 struct intel_power_domain_mask async_put_domains[2]; 156 154 int async_put_next_delay; 157 155 ··· 161 159 struct intel_display_power_domain_set { 162 160 struct intel_power_domain_mask mask; 163 161 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM 164 164 - intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; 162 162 + struct ref_tracker *wakerefs[POWER_DOMAIN_NUM]; 165 163 #endif 166 164 }; 167 165 ··· 189 187 190 188 bool intel_display_power_is_enabled(struct intel_display *display, 191 189 enum intel_display_power_domain domain); 192 192 - intel_wakeref_t intel_display_power_get(struct intel_display *display, 193 193 - enum intel_display_power_domain domain); 194 194 - intel_wakeref_t 190 190 + struct ref_tracker *intel_display_power_get(struct intel_display *display, 191 191 + enum intel_display_power_domain domain); 192 192 + struct ref_tracker * 195 193 intel_display_power_get_if_enabled(struct intel_display *display, 196 194 enum intel_display_power_domain domain); 197 195 void __intel_display_power_put_async(struct intel_display *display, 198 196 enum intel_display_power_domain domain, 199 199 - intel_wakeref_t wakeref, 197 197 + struct ref_tracker *wakeref, 200 198 int delay_ms); 201 199 void intel_display_power_flush_work(struct intel_display *display); 202 200 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 203 201 void intel_display_power_put(struct intel_display *display, 204 202 enum intel_display_power_domain domain, 205 205 - intel_wakeref_t wakeref); 203 203 + struct ref_tracker *wakeref); 206 204 static inline void 207 205 intel_display_power_put_async(struct intel_display *display, 208 206 enum intel_display_power_domain domain, 209 209 - intel_wakeref_t wakeref) 207 207 + struct ref_tracker *wakeref) 210 208 { 211 209 __intel_display_power_put_async(display, domain, wakeref, -1); 212 210 } ··· 214 212 static inline void 215 213 intel_display_power_put_async_delay(struct intel_display *display, 216 214 enum intel_display_power_domain domain, 217 217 - intel_wakeref_t wakeref, 215 215 + struct ref_tracker *wakeref, 218 216 int delay_ms) 219 217 { 220 218 __intel_display_power_put_async(display, domain, wakeref, delay_ms); ··· 226 224 static inline void 227 225 intel_display_power_put(struct intel_display *display, 228 226 enum intel_display_power_domain domain, 229 229 - intel_wakeref_t wakeref) 227 227 + struct ref_tracker *wakeref) 230 228 { 231 229 intel_display_power_put_unchecked(display, domain); 232 230 } ··· 234 232 static inline void 235 233 intel_display_power_put_async(struct intel_display *display, 236 234 enum intel_display_power_domain domain, 237 237 - intel_wakeref_t wakeref) 235 235 + struct ref_tracker *wakeref) 238 236 { 239 237 __intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, -1); 240 238 } ··· 242 240 static inline void 243 241 intel_display_power_put_async_delay(struct intel_display *display, 244 242 enum intel_display_power_domain domain, 245 245 - intel_wakeref_t wakeref, 243 243 + struct ref_tracker *wakeref, 246 244 int delay_ms) 247 245 { 248 246 __intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, delay_ms); ··· 299 297 void gen9_dbuf_slices_update(struct intel_display *display, 300 298 u8 req_slices); 301 299 302 302 - #define with_intel_display_power(display, domain, wf) \ 303 303 - for ((wf) = intel_display_power_get((display), (domain)); (wf); \ 300 300 + #define __with_intel_display_power(display, domain, wf) \ 301 301 + for (struct ref_tracker *(wf) = intel_display_power_get((display), (domain)); (wf); \ 304 302 intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL) 305 303 306 306 - #define with_intel_display_power_if_enabled(display, domain, wf) \ 307 307 - for ((wf) = intel_display_power_get_if_enabled((display), (domain)); (wf); \ 304 304 + #define with_intel_display_power(display, domain) \ 305 305 + __with_intel_display_power(display, domain, __UNIQUE_ID(wakeref)) 306 306 + 307 307 + #define __with_intel_display_power_if_enabled(display, domain, wf) \ 308 308 + for (struct ref_tracker *(wf) = intel_display_power_get_if_enabled((display), (domain)); (wf); \ 308 309 intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL) 310 310 + 311 311 + #define with_intel_display_power_if_enabled(display, domain) \ 312 312 + __with_intel_display_power_if_enabled(display, domain, __UNIQUE_ID(wakeref)) 309 313 310 314 #endif /* __INTEL_DISPLAY_POWER_H__ */

+35 -29

drivers/gpu/drm/i915/display/intel_display_power_well.c

reviewed

··· 7 7 8 8 #include <drm/drm_print.h> 9 9 10 10 - #include "i915_drv.h" 11 11 - #include "i915_irq.h" 12 10 #include "i915_reg.h" 13 11 #include "intel_backlight_regs.h" 14 12 #include "intel_combo_phy.h" ··· 26 28 #include "intel_dpio_phy.h" 27 29 #include "intel_dpll.h" 28 30 #include "intel_hotplug.h" 31 31 + #include "intel_parent.h" 29 32 #include "intel_pcode.h" 30 33 #include "intel_pps.h" 31 34 #include "intel_psr.h" ··· 257 258 return NULL; 258 259 } 259 260 260 260 - static enum phy icl_aux_pw_to_phy(struct intel_display *display, 261 261 - const struct i915_power_well *power_well) 261 261 + static struct intel_encoder * 262 262 + icl_aux_pw_to_encoder(struct intel_display *display, 263 263 + const struct i915_power_well *power_well) 262 264 { 263 265 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 264 266 struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); ··· 271 271 * as HDMI-only and routed to a combo PHY, the encoder either won't be 272 272 * present at all or it will not have an aux_ch assigned. 273 273 */ 274 274 - return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE; 274 274 + return dig_port ? &dig_port->base : NULL; 275 275 + } 276 276 + 277 277 + static enum phy icl_aux_pw_to_phy(struct intel_display *display, 278 278 + const struct i915_power_well *power_well) 279 279 + { 280 280 + struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well); 281 281 + 282 282 + return encoder ? intel_encoder_to_phy(encoder) : PHY_NONE; 283 283 + } 284 284 + 285 285 + static bool icl_aux_pw_is_tc_phy(struct intel_display *display, 286 286 + const struct i915_power_well *power_well) 287 287 + { 288 288 + struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well); 289 289 + 290 290 + return encoder && intel_encoder_is_tc(encoder); 275 291 } 276 292 277 293 static void hsw_wait_for_power_well_enable(struct intel_display *display, ··· 586 570 icl_aux_power_well_enable(struct intel_display *display, 587 571 struct i915_power_well *power_well) 588 572 { 589 589 - enum phy phy = icl_aux_pw_to_phy(display, power_well); 590 590 - 591 591 - if (intel_phy_is_tc(display, phy)) 573 573 + if (icl_aux_pw_is_tc_phy(display, power_well)) 592 574 return icl_tc_phy_aux_power_well_enable(display, power_well); 593 575 else if (display->platform.icelake) 594 576 return icl_combo_phy_aux_power_well_enable(display, ··· 599 585 icl_aux_power_well_disable(struct intel_display *display, 600 586 struct i915_power_well *power_well) 601 587 { 602 602 - enum phy phy = icl_aux_pw_to_phy(display, power_well); 603 603 - 604 604 - if (intel_phy_is_tc(display, phy)) 588 588 + if (icl_aux_pw_is_tc_phy(display, power_well)) 605 589 return hsw_power_well_disable(display, power_well); 606 590 else if (display->platform.icelake) 607 591 return icl_combo_phy_aux_power_well_disable(display, ··· 640 628 641 629 static void assert_can_enable_dc9(struct intel_display *display) 642 630 { 643 643 - struct drm_i915_private *dev_priv = to_i915(display->drm); 644 644 - 645 631 drm_WARN_ONCE(display->drm, 646 632 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), 647 633 "DC9 already programmed to be enabled.\n"); ··· 651 641 intel_de_read(display, HSW_PWR_WELL_CTL2) & 652 642 HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), 653 643 "Power well 2 on.\n"); 654 654 - drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), 644 644 + drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display), 655 645 "Interrupts not disabled yet.\n"); 656 646 657 647 /* ··· 665 655 666 656 static void assert_can_disable_dc9(struct intel_display *display) 667 657 { 668 668 - struct drm_i915_private *dev_priv = to_i915(display->drm); 669 669 - 670 670 - drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), 658 658 + drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display), 671 659 "Interrupts not disabled yet.\n"); 672 660 drm_WARN_ONCE(display->drm, 673 661 intel_de_read(display, DC_STATE_EN) & ··· 1289 1281 1290 1282 static void vlv_display_power_well_deinit(struct intel_display *display) 1291 1283 { 1292 1292 - struct drm_i915_private *dev_priv = to_i915(display->drm); 1293 1293 - 1294 1284 valleyview_disable_display_irqs(display); 1295 1285 1296 1286 /* make sure we're done processing display irqs */ 1297 1297 - intel_synchronize_irq(dev_priv); 1287 1287 + intel_parent_irq_synchronize(display); 1298 1288 1299 1289 vlv_pps_reset_all(display); 1300 1290 ··· 1858 1852 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1859 1853 enum phy phy = icl_aux_pw_to_phy(display, power_well); 1860 1854 1861 1861 - if (intel_phy_is_tc(display, phy)) 1855 1855 + if (icl_aux_pw_is_tc_phy(display, power_well)) 1862 1856 icl_tc_port_assert_ref_held(display, power_well, 1863 1857 aux_ch_to_digital_port(display, aux_ch)); 1864 1858 ··· 1866 1860 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1867 1861 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); 1868 1862 1869 1869 - /* 1870 1870 - * The power status flag cannot be used to determine whether aux 1871 1871 - * power wells have finished powering up. Instead we're 1872 1872 - * expected to just wait a fixed 600us after raising the request 1873 1873 - * bit. 1874 1874 - */ 1875 1875 - if (DISPLAY_VER(display) >= 35) { 1863 1863 + if (HAS_LT_PHY(display)) { 1876 1864 if (intel_de_wait_for_set_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1877 1865 XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2)) 1878 1866 drm_warn(display->drm, 1879 1867 "Timeout waiting for PHY %c AUX channel power to be up\n", 1880 1868 phy_name(phy)); 1881 1869 } else { 1870 1870 + /* 1871 1871 + * The power status flag cannot be used to determine whether aux 1872 1872 + * power wells have finished powering up. Instead we're 1873 1873 + * expected to just wait a fixed 600us after raising the request 1874 1874 + * bit. 1875 1875 + */ 1882 1876 usleep_range(600, 1200); 1883 1877 } 1884 1878 } ··· 1893 1887 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1894 1888 0); 1895 1889 1896 1896 - if (DISPLAY_VER(display) >= 35) { 1890 1890 + if (HAS_LT_PHY(display)) { 1897 1891 if (intel_de_wait_for_clear_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1898 1892 XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1)) 1899 1893 drm_warn(display->drm,

+22 -1

drivers/gpu/drm/i915/display/intel_display_regs.h

reviewed

··· 882 882 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */ 883 883 #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id)) 884 884 885 885 + #define _UNDERRUN_DBG1_A 0x70064 886 886 + #define _UNDERRUN_DBG1_B 0x71064 887 887 + #define UNDERRUN_DBG1(pipe) _MMIO_PIPE(pipe, _UNDERRUN_DBG1_A, _UNDERRUN_DBG1_B) 888 888 + #define UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK REG_GENMASK(29, 24) 889 889 + #define UNDERRUN_DDB_EMPTY_MASK REG_GENMASK(21, 16) 890 890 + #define UNDERRUN_DBUF_NOT_FILLED_MASK REG_GENMASK(13, 8) 891 891 + #define UNDERRUN_BELOW_WM0_MASK REG_GENMASK(5, 0) 892 892 + 893 893 + #define _UNDERRUN_DBG2_A 0x70068 894 894 + #define _UNDERRUN_DBG2_B 0x71068 895 895 + #define UNDERRUN_DBG2(pipe) _MMIO_PIPE(pipe, _UNDERRUN_DBG2_A, _UNDERRUN_DBG2_B) 896 896 + #define UNDERRUN_FRAME_LINE_COUNTERS_FROZEN REG_BIT(31) 897 897 + #define UNDERRUN_PIPE_FRAME_COUNT_MASK REG_GENMASK(30, 20) 898 898 + #define UNDERRUN_LINE_COUNT_MASK REG_GENMASK(19, 0) 899 899 + 885 900 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 886 901 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) 887 902 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) ··· 1431 1416 1432 1417 #define GEN12_DCPR_STATUS_1 _MMIO(0x46440) 1433 1418 #define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26) 1419 1419 + #define XE3P_UNDERRUN_PKGC REG_BIT(21) 1434 1420 1435 1421 #define FUSE_STRAP _MMIO(0x42014) 1436 1422 #define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31) ··· 2365 2349 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) 2366 2350 #define DDI_A_4_LANES REG_BIT(4) 2367 2351 #define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) 2352 2352 + #define DDI_PORT_WIDTH_ENCODE(width) ((width) == 3 ? 4 : (width) - 1) 2353 2353 + #define DDI_PORT_WIDTH_DECODE(regval) ((regval) == 4 ? 3 : (regval) + 1) 2368 2354 #define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \ 2369 2369 - ((width) == 3 ? 4 : (width) - 1)) 2355 2355 + DDI_PORT_WIDTH_ENCODE(width)) 2356 2356 + #define DDI_PORT_WIDTH_GET(regval) DDI_PORT_WIDTH_DECODE(REG_FIELD_GET(DDI_PORT_WIDTH_MASK, \ 2357 2357 + (regval))) 2358 2358 + 2370 2359 #define DDI_PORT_WIDTH_SHIFT 1 2371 2360 #define DDI_INIT_DISPLAY_DETECTED REG_BIT(0) 2372 2361

+2 -3

drivers/gpu/drm/i915/display/intel_display_reset.c

reviewed

··· 6 6 #include <drm/drm_atomic_helper.h> 7 7 #include <drm/drm_print.h> 8 8 9 9 - #include "i915_drv.h" 10 9 #include "intel_clock_gating.h" 11 10 #include "intel_cx0_phy.h" 12 11 #include "intel_display_core.h" 13 12 #include "intel_display_driver.h" 14 13 #include "intel_display_reset.h" 15 14 #include "intel_display_types.h" 15 15 + #include "intel_display_utils.h" 16 16 #include "intel_hotplug.h" 17 17 #include "intel_pps.h" 18 18 ··· 79 79 80 80 void intel_display_reset_finish(struct intel_display *display, bool test_only) 81 81 { 82 82 - struct drm_i915_private *i915 = to_i915(display->drm); 83 82 struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx; 84 83 struct drm_atomic_state *state; 85 84 int ret; ··· 106 107 */ 107 108 intel_pps_unlock_regs_wa(display); 108 109 intel_display_driver_init_hw(display); 109 109 - intel_clock_gating_init(i915); 110 110 + intel_clock_gating_init(display->drm); 110 111 intel_cx0_pll_power_save_wa(display); 111 112 intel_hpd_init(display); 112 113

+16 -15

drivers/gpu/drm/i915/display/intel_display_rps.c

reviewed

··· 3 3 * Copyright © 2023 Intel Corporation 4 4 */ 5 5 6 6 + #include <linux/dma-fence.h> 7 7 + 6 8 #include <drm/drm_crtc.h> 7 9 #include <drm/drm_vblank.h> 8 10 9 9 - #include "gt/intel_rps.h" 10 10 - #include "i915_drv.h" 11 11 #include "i915_reg.h" 12 12 #include "intel_display_core.h" 13 13 #include "intel_display_irq.h" 14 14 #include "intel_display_rps.h" 15 15 #include "intel_display_types.h" 16 16 + #include "intel_parent.h" 16 17 17 18 struct wait_rps_boost { 18 19 struct wait_queue_entry wait; 19 20 20 21 struct drm_crtc *crtc; 21 21 - struct i915_request *request; 22 22 + struct dma_fence *fence; 22 23 }; 23 24 24 25 static int do_rps_boost(struct wait_queue_entry *_wait, 25 26 unsigned mode, int sync, void *key) 26 27 { 27 28 struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait); 28 28 - struct i915_request *rq = wait->request; 29 29 + struct intel_display *display = to_intel_display(wait->crtc->dev); 29 30 30 31 /* 31 32 * If we missed the vblank, but the request is already running it 32 33 * is reasonable to assume that it will complete before the next 33 33 - * vblank without our intervention, so leave RPS alone. 34 34 + * vblank without our intervention, so leave RPS alone if not started. 34 35 */ 35 35 - if (!i915_request_started(rq)) 36 36 - intel_rps_boost(rq); 37 37 - i915_request_put(rq); 36 36 + intel_parent_rps_boost_if_not_started(display, wait->fence); 37 37 + 38 38 + dma_fence_put(wait->fence); 38 39 39 40 drm_crtc_vblank_put(wait->crtc); 40 41 ··· 50 49 struct intel_display *display = to_intel_display(crtc->dev); 51 50 struct wait_rps_boost *wait; 52 51 53 53 - if (!dma_fence_is_i915(fence)) 52 52 + if (!intel_parent_rps_available(display)) 54 53 return; 55 54 56 55 if (DISPLAY_VER(display) < 6) ··· 65 64 return; 66 65 } 67 66 68 68 - wait->request = to_request(dma_fence_get(fence)); 67 67 + wait->fence = dma_fence_get(fence); 69 68 wait->crtc = crtc; 70 69 71 70 wait->wait.func = do_rps_boost; ··· 78 77 struct intel_atomic_state *state, 79 78 bool interactive) 80 79 { 81 81 - struct drm_i915_private *i915 = to_i915(display->drm); 80 80 + if (!intel_parent_rps_available(display)) 81 81 + return; 82 82 83 83 if (state->rps_interactive == interactive) 84 84 return; 85 85 86 86 - intel_rps_mark_interactive(&to_gt(i915)->rps, interactive); 86 86 + intel_parent_rps_mark_interactive(display, interactive); 87 87 + 87 88 state->rps_interactive = interactive; 88 89 } 89 90 ··· 105 102 106 103 void ilk_display_rps_irq_handler(struct intel_display *display) 107 104 { 108 108 - struct drm_i915_private *i915 = to_i915(display->drm); 109 109 - 110 110 - gen5_rps_irq_handler(&to_gt(i915)->rps); 105 105 + intel_parent_rps_ilk_irq_handler(display); 111 106 }

-21

drivers/gpu/drm/i915/display/intel_display_rps.h

reviewed

··· 13 13 struct intel_atomic_state; 14 14 struct intel_display; 15 15 16 16 - #ifdef I915 17 16 void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc, 18 17 struct dma_fence *fence); 19 18 void intel_display_rps_mark_interactive(struct intel_display *display, ··· 21 22 void ilk_display_rps_enable(struct intel_display *display); 22 23 void ilk_display_rps_disable(struct intel_display *display); 23 24 void ilk_display_rps_irq_handler(struct intel_display *display); 24 24 - #else 25 25 - static inline void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc, 26 26 - struct dma_fence *fence) 27 27 - { 28 28 - } 29 29 - static inline void intel_display_rps_mark_interactive(struct intel_display *display, 30 30 - struct intel_atomic_state *state, 31 31 - bool interactive) 32 32 - { 33 33 - } 34 34 - static inline void ilk_display_rps_enable(struct intel_display *display) 35 35 - { 36 36 - } 37 37 - static inline void ilk_display_rps_disable(struct intel_display *display) 38 38 - { 39 39 - } 40 40 - static inline void ilk_display_rps_irq_handler(struct intel_display *display) 41 41 - { 42 42 - } 43 43 - #endif 44 25 45 26 #endif /* __INTEL_DISPLAY_RPS_H__ */

+36 -16

drivers/gpu/drm/i915/display/intel_display_types.h

reviewed

··· 509 509 bool force_hdcp14; 510 510 }; 511 511 512 512 + enum intel_panel_replay_dsc_support { 513 513 + INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED, 514 514 + INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY, 515 515 + INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE, 516 516 + }; 517 517 + 512 518 struct intel_connector { 513 519 struct drm_connector base; 514 520 /* ··· 567 561 } overall_throughput; 568 562 int max_line_width; 569 563 } dsc_branch_caps; 564 564 + 565 565 + struct { 566 566 + u8 dpcd[DP_PANEL_REPLAY_CAP_SIZE]; 567 567 + #define INTEL_PR_DPCD_INDEX(pr_dpcd_register) ((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT) 568 568 + 569 569 + bool support; 570 570 + bool su_support; 571 571 + enum intel_panel_replay_dsc_support dsc_support; 572 572 + 573 573 + u16 su_w_granularity; 574 574 + u16 su_y_granularity; 575 575 + } panel_replay_caps; 576 576 + 577 577 + struct { 578 578 + u8 dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 579 579 + 580 580 + bool support; 581 581 + bool su_support; 582 582 + 583 583 + u16 su_w_granularity; 584 584 + u16 su_y_granularity; 585 585 + 586 586 + u8 sync_latency; 587 587 + } psr_caps; 570 588 } dp; 571 589 572 590 struct { ··· 985 955 u16 postoff[3]; 986 956 }; 987 957 988 988 - enum intel_panel_replay_dsc_support { 989 989 - INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED, 990 990 - INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY, 991 991 - INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE, 992 992 - }; 993 993 - 994 958 struct scaler_filter_coeff { 995 959 u16 sign; 996 960 u16 exp; ··· 1176 1152 bool enable_psr2_su_region_et; 1177 1153 bool req_psr2_sdp_prior_scanline; 1178 1154 bool has_panel_replay; 1155 1155 + bool link_off_after_as_sdp_when_pr_active; 1156 1156 + bool disable_as_sdp_when_pr_active; 1179 1157 bool wm_level_disabled; 1180 1158 bool pkg_c_latency_used; 1181 1159 /* Only used for state verification. */ ··· 1688 1662 unsigned long last_power_on; 1689 1663 unsigned long last_backlight_off; 1690 1664 ktime_t panel_power_off_time; 1691 1691 - intel_wakeref_t vdd_wakeref; 1665 1665 + struct ref_tracker *vdd_wakeref; 1692 1666 1693 1667 union { 1694 1668 /* ··· 1742 1716 bool active; 1743 1717 struct work_struct work; 1744 1718 unsigned int busy_frontbuffer_bits; 1745 1745 - bool sink_psr2_support; 1746 1719 bool link_standby; 1747 1720 bool sel_update_enabled; 1748 1721 bool psr2_sel_fetch_enabled; 1749 1722 bool psr2_sel_fetch_cff_enabled; 1750 1723 bool su_region_et_enabled; 1751 1724 bool req_psr2_sdp_prior_scanline; 1752 1752 - u8 sink_sync_latency; 1753 1725 ktime_t last_entry_attempt; 1754 1726 ktime_t last_exit; 1755 1727 bool sink_not_reliable; ··· 1756 1732 u16 su_y_granularity; 1757 1733 bool source_panel_replay_support; 1758 1734 bool sink_panel_replay_support; 1759 1759 - bool sink_panel_replay_su_support; 1760 1760 - enum intel_panel_replay_dsc_support sink_panel_replay_dsc_support; 1761 1735 bool panel_replay_enabled; 1762 1736 u32 dc3co_exitline; 1763 1737 u32 dc3co_exit_delay; ··· 1782 1760 bool needs_modeset_retry; 1783 1761 bool use_max_params; 1784 1762 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 1785 1785 - u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 1786 1786 - u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE]; 1787 1787 - #define INTEL_PR_DPCD_INDEX(pr_dpcd_register) ((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT) 1788 1763 1789 1764 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 1790 1765 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; ··· 1959 1940 bool lane_reversal; 1960 1941 bool ddi_a_4_lanes; 1961 1942 bool release_cl2_override; 1943 1943 + bool dedicated_external; 1962 1944 u8 max_lanes; 1963 1945 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ 1964 1946 enum aux_ch aux_ch; 1965 1947 enum intel_display_power_domain ddi_io_power_domain; 1966 1966 - intel_wakeref_t ddi_io_wakeref; 1967 1967 - intel_wakeref_t aux_wakeref; 1948 1948 + struct ref_tracker *ddi_io_wakeref; 1949 1949 + struct ref_tracker *aux_wakeref; 1968 1950 1969 1951 struct intel_tc_port *tc; 1970 1952

+4

drivers/gpu/drm/i915/display/intel_display_wa.c

reviewed

··· 70 70 return DISPLAY_VER(display) == 13; 71 71 case INTEL_DISPLAY_WA_22014263786: 72 72 return IS_DISPLAY_VERx100(display, 1100, 1400); 73 73 + case INTEL_DISPLAY_WA_15018326506: 74 74 + return display->platform.battlemage; 75 75 + case INTEL_DISPLAY_WA_14025769978: 76 76 + return DISPLAY_VER(display) == 35; 73 77 default: 74 78 drm_WARN(display->drm, 1, "Missing Wa number: %s\n", name); 75 79 break;

+2

drivers/gpu/drm/i915/display/intel_display_wa.h

reviewed

··· 26 26 INTEL_DISPLAY_WA_16025573575, 27 27 INTEL_DISPLAY_WA_14011503117, 28 28 INTEL_DISPLAY_WA_22014263786, 29 29 + INTEL_DISPLAY_WA_15018326506, 30 30 + INTEL_DISPLAY_WA_14025769978, 29 31 }; 30 32 31 33 bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name);

+1 -1

drivers/gpu/drm/i915/display/intel_dmc.c

reviewed

··· 1322 1322 1323 1323 static void intel_dmc_runtime_pm_put(struct intel_display *display) 1324 1324 { 1325 1325 - intel_wakeref_t wakeref __maybe_unused = 1325 1325 + struct ref_tracker *wakeref __maybe_unused = 1326 1326 fetch_and_zero(&display->dmc.wakeref); 1327 1327 1328 1328 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

+157 -77

drivers/gpu/drm/i915/display/intel_dp.c

reviewed

··· 424 424 return 1; 425 425 } 426 426 427 427 + int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, 428 428 + int dsc_slice_count, int bpp_x16, unsigned long flags) 429 429 + { 430 430 + int overhead; 431 431 + 432 432 + WARN_ON(flags & ~(DRM_DP_BW_OVERHEAD_MST | DRM_DP_BW_OVERHEAD_SSC_REF_CLK | 433 433 + DRM_DP_BW_OVERHEAD_FEC)); 434 434 + 435 435 + if (drm_dp_is_uhbr_rate(link_clock)) 436 436 + flags |= DRM_DP_BW_OVERHEAD_UHBR; 437 437 + 438 438 + if (dsc_slice_count) 439 439 + flags |= DRM_DP_BW_OVERHEAD_DSC; 440 440 + 441 441 + overhead = drm_dp_bw_overhead(lane_count, hdisplay, 442 442 + dsc_slice_count, 443 443 + bpp_x16, 444 444 + flags); 445 445 + 446 446 + /* 447 447 + * TODO: clarify whether a minimum required by the fixed FEC overhead 448 448 + * in the bspec audio programming sequence is required here. 449 449 + */ 450 450 + return max(overhead, intel_dp_bw_fec_overhead(flags & DRM_DP_BW_OVERHEAD_FEC)); 451 451 + } 452 452 + 427 453 /* 428 454 * The required data bandwidth for a mode with given pixel clock and bpp. This 429 455 * is the required net bandwidth independent of the data bandwidth efficiency. 430 430 - * 431 431 - * TODO: check if callers of this functions should use 432 432 - * intel_dp_effective_data_rate() instead. 433 456 */ 434 434 - int 435 435 - intel_dp_link_required(int pixel_clock, int bpp) 457 457 + int intel_dp_link_required(int link_clock, int lane_count, 458 458 + int mode_clock, int mode_hdisplay, 459 459 + int link_bpp_x16, unsigned long bw_overhead_flags) 436 460 { 437 437 - /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 438 438 - return DIV_ROUND_UP(pixel_clock * bpp, 8); 461 461 + int bw_overhead = intel_dp_link_bw_overhead(link_clock, lane_count, mode_hdisplay, 462 462 + 0, link_bpp_x16, bw_overhead_flags); 463 463 + 464 464 + return intel_dp_effective_data_rate(mode_clock, link_bpp_x16, bw_overhead); 439 465 } 440 466 441 467 /** ··· 546 520 struct intel_display *display = to_intel_display(intel_dp); 547 521 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 548 522 549 549 - if (intel_encoder_is_c10phy(encoder)) 523 523 + if (intel_encoder_is_c10phy(encoder) || 524 524 + display->platform.pantherlake_wildcatlake) 550 525 return 810000; 551 526 552 527 if (DISPLAY_VERx100(display) == 1401) ··· 1040 1013 int num_joined_pipes) 1041 1014 { 1042 1015 struct intel_display *display = to_intel_display(connector); 1016 1016 + u32 sink_slice_count_mask = 1017 1017 + drm_dp_dsc_sink_slice_count_mask(connector->dp.dsc_dpcd, false); 1043 1018 u8 min_slice_count, i; 1044 1019 int max_slice_width; 1045 1020 int tp_rgb_yuv444; ··· 1113 1084 (!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4)) 1114 1085 continue; 1115 1086 1116 1116 - if (test_slice_count > 1117 1117 - drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) 1118 1118 - break; 1087 1087 + if (!(drm_dp_dsc_slice_count_to_mask(test_slice_count) & 1088 1088 + sink_slice_count_mask)) 1089 1089 + continue; 1119 1090 1120 1091 /* 1121 1092 * Bigjoiner needs small joiner to be enabled. ··· 1132 1103 return test_slice_count; 1133 1104 } 1134 1105 1135 1135 - drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n", 1136 1136 - min_slice_count); 1106 1106 + /* Print slice count 1,2,4,..24 if bit#0,1,3,..23 is set in the mask. */ 1107 1107 + sink_slice_count_mask <<= 1; 1108 1108 + drm_dbg_kms(display->drm, 1109 1109 + "[CONNECTOR:%d:%s] Unsupported slice count (min: %d, sink supported: %*pbl)\n", 1110 1110 + connector->base.base.id, connector->base.name, 1111 1111 + min_slice_count, 1112 1112 + (int)BITS_PER_TYPE(sink_slice_count_mask), &sink_slice_count_mask); 1113 1113 + 1137 1114 return 0; 1138 1115 } 1139 1116 ··· 1261 1226 return 8 * 3; 1262 1227 } 1263 1228 1264 1264 - int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) 1229 1229 + int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format, int pipe_bpp) 1265 1230 { 1266 1231 /* 1267 1232 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output ··· 1269 1234 * of bytes of RGB pixel. 1270 1235 */ 1271 1236 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1272 1272 - bpp /= 2; 1237 1237 + pipe_bpp /= 2; 1273 1238 1274 1274 - return bpp; 1239 1239 + return fxp_q4_from_int(pipe_bpp); 1275 1240 } 1276 1241 1277 1242 static enum intel_output_format ··· 1287 1252 } 1288 1253 1289 1254 static int 1290 1290 - intel_dp_mode_min_output_bpp(struct intel_connector *connector, 1291 1291 - const struct drm_display_mode *mode) 1255 1255 + intel_dp_mode_min_link_bpp_x16(struct intel_connector *connector, 1256 1256 + const struct drm_display_mode *mode) 1292 1257 { 1293 1258 enum intel_output_format output_format, sink_format; 1294 1259 ··· 1296 1261 1297 1262 output_format = intel_dp_output_format(connector, sink_format); 1298 1263 1299 1299 - return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); 1264 1264 + return intel_dp_output_format_link_bpp_x16(output_format, 1265 1265 + intel_dp_min_bpp(output_format)); 1300 1266 } 1301 1267 1302 1268 static bool intel_dp_hdisplay_bad(struct intel_display *display, ··· 1369 1333 1370 1334 /* If PCON supports FRL MODE, check FRL bandwidth constraints */ 1371 1335 if (intel_dp->dfp.pcon_max_frl_bw) { 1336 1336 + int link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode); 1372 1337 int target_bw; 1373 1338 int max_frl_bw; 1374 1374 - int bpp = intel_dp_mode_min_output_bpp(connector, mode); 1375 1339 1376 1376 - target_bw = bpp * target_clock; 1340 1340 + target_bw = fxp_q4_to_int_roundup(link_bpp_x16) * target_clock; 1377 1341 1378 1342 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 1379 1343 ··· 1488 1452 enum drm_mode_status status; 1489 1453 bool dsc = false; 1490 1454 int num_joined_pipes; 1455 1455 + int link_bpp_x16; 1491 1456 1492 1457 status = intel_cpu_transcoder_mode_valid(display, mode); 1493 1458 if (status != MODE_OK) ··· 1531 1494 1532 1495 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); 1533 1496 1534 1534 - mode_rate = intel_dp_link_required(target_clock, 1535 1535 - intel_dp_mode_min_output_bpp(connector, mode)); 1497 1497 + link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode); 1498 1498 + mode_rate = intel_dp_link_required(max_link_clock, max_lanes, 1499 1499 + target_clock, mode->hdisplay, 1500 1500 + link_bpp_x16, 0); 1536 1501 1537 1502 if (intel_dp_has_dsc(connector)) { 1538 1503 int pipe_bpp; ··· 1841 1802 const struct link_config_limits *limits) 1842 1803 { 1843 1804 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); 1844 1844 - int mode_rate, link_rate, link_avail; 1805 1805 + int link_rate, link_avail; 1845 1806 1846 1807 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); 1847 1808 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16); 1848 1809 bpp -= 2 * 3) { 1849 1849 - int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); 1850 1850 - 1851 1851 - mode_rate = intel_dp_link_required(clock, link_bpp); 1810 1810 + int link_bpp_x16 = 1811 1811 + intel_dp_output_format_link_bpp_x16(pipe_config->output_format, bpp); 1852 1812 1853 1813 for (i = 0; i < intel_dp->num_common_rates; i++) { 1854 1814 link_rate = intel_dp_common_rate(intel_dp, i); ··· 1858 1820 for (lane_count = limits->min_lane_count; 1859 1821 lane_count <= limits->max_lane_count; 1860 1822 lane_count <<= 1) { 1823 1823 + const struct drm_display_mode *adjusted_mode = 1824 1824 + &pipe_config->hw.adjusted_mode; 1825 1825 + int mode_rate = 1826 1826 + intel_dp_link_required(link_rate, lane_count, 1827 1827 + clock, adjusted_mode->hdisplay, 1828 1828 + link_bpp_x16, 0); 1829 1829 + 1861 1830 link_avail = intel_dp_max_link_data_rate(intel_dp, 1862 1831 link_rate, 1863 1832 lane_count); 1864 1864 - 1865 1833 1866 1834 if (mode_rate <= link_avail) { 1867 1835 pipe_config->lane_count = lane_count; ··· 2026 1982 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); 2027 1983 } 2028 1984 2029 2029 - static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock, 2030 2030 - u32 lane_count, u32 mode_clock, 2031 2031 - enum intel_output_format output_format, 2032 2032 - int timeslots) 1985 1985 + static bool is_bw_sufficient_for_dsc_config(struct intel_dp *intel_dp, 1986 1986 + int link_clock, int lane_count, 1987 1987 + int mode_clock, int mode_hdisplay, 1988 1988 + int dsc_slice_count, int link_bpp_x16, 1989 1989 + unsigned long bw_overhead_flags) 2033 1990 { 2034 2034 - u32 available_bw, required_bw; 1991 1991 + int available_bw; 1992 1992 + int required_bw; 2035 1993 2036 2036 - available_bw = (link_clock * lane_count * timeslots * 16) / 8; 2037 2037 - required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock)); 1994 1994 + available_bw = intel_dp_max_link_data_rate(intel_dp, link_clock, lane_count); 1995 1995 + required_bw = intel_dp_link_required(link_clock, lane_count, 1996 1996 + mode_clock, mode_hdisplay, 1997 1997 + link_bpp_x16, bw_overhead_flags); 2038 1998 2039 2039 - return available_bw > required_bw; 1999 1999 + return available_bw >= required_bw; 2040 2000 } 2041 2001 2042 2002 static int dsc_compute_link_config(struct intel_dp *intel_dp, ··· 2086 2038 if (ret) 2087 2039 continue; 2088 2040 } else { 2089 2089 - if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate, 2090 2090 - lane_count, adjusted_mode->clock, 2091 2091 - pipe_config->output_format, 2092 2092 - timeslots)) 2041 2041 + unsigned long bw_overhead_flags = 2042 2042 + pipe_config->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; 2043 2043 + 2044 2044 + if (!is_bw_sufficient_for_dsc_config(intel_dp, 2045 2045 + link_rate, lane_count, 2046 2046 + adjusted_mode->crtc_clock, 2047 2047 + adjusted_mode->hdisplay, 2048 2048 + pipe_config->dsc.slice_count, 2049 2049 + dsc_bpp_x16, 2050 2050 + bw_overhead_flags)) 2093 2051 continue; 2094 2052 } 2095 2053 ··· 2246 2192 { 2247 2193 struct intel_display *display = to_intel_display(intel_dp); 2248 2194 const struct intel_connector *connector = to_intel_connector(conn_state->connector); 2249 2249 - const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2250 2250 - int output_bpp; 2251 2195 int min_bpp_x16, max_bpp_x16, bpp_step_x16; 2252 2252 - int dsc_joiner_max_bpp; 2253 2253 - int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); 2196 2196 + int link_bpp_x16; 2254 2197 int bpp_x16; 2255 2198 int ret; 2256 2199 2257 2257 - dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock, 2258 2258 - adjusted_mode->hdisplay, 2259 2259 - num_joined_pipes); 2260 2260 - max_bpp_x16 = min(fxp_q4_from_int(dsc_joiner_max_bpp), limits->link.max_bpp_x16); 2261 2261 - 2200 2200 + max_bpp_x16 = limits->link.max_bpp_x16; 2262 2201 bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); 2263 2202 2264 2203 /* Compressed BPP should be less than the Input DSC bpp */ 2265 2265 - output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); 2266 2266 - max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16); 2204 2204 + link_bpp_x16 = intel_dp_output_format_link_bpp_x16(pipe_config->output_format, pipe_bpp); 2205 2205 + max_bpp_x16 = min(max_bpp_x16, link_bpp_x16 - bpp_step_x16); 2267 2206 2268 2207 drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16)); 2269 2208 min_bpp_x16 = round_up(limits->link.min_bpp_x16, bpp_step_x16); ··· 2607 2560 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; 2608 2561 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; 2609 2562 int throughput_max_bpp_x16; 2563 2563 + int joiner_max_bpp; 2610 2564 2611 2565 dsc_src_min_bpp = intel_dp_dsc_min_src_compressed_bpp(); 2612 2566 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state); ··· 2615 2567 limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); 2616 2568 2617 2569 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); 2570 2570 + joiner_max_bpp = 2571 2571 + get_max_compressed_bpp_with_joiner(display, 2572 2572 + adjusted_mode->crtc_clock, 2573 2573 + adjusted_mode->hdisplay, 2574 2574 + intel_crtc_num_joined_pipes(crtc_state)); 2618 2575 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, 2619 2576 crtc_state, 2620 2577 limits->pipe.max_bpp / 3); 2621 2621 - dsc_max_bpp = dsc_sink_max_bpp ? 2622 2622 - min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; 2578 2578 + dsc_max_bpp = min(dsc_sink_max_bpp, dsc_src_max_bpp); 2579 2579 + dsc_max_bpp = min(dsc_max_bpp, joiner_max_bpp); 2623 2580 2624 2581 max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp)); 2625 2582 2626 2583 throughput_max_bpp_x16 = dsc_throughput_quirk_max_bpp_x16(connector, crtc_state); 2627 2627 - throughput_max_bpp_x16 = clamp(throughput_max_bpp_x16, 2628 2628 - limits->link.min_bpp_x16, max_link_bpp_x16); 2629 2584 if (throughput_max_bpp_x16 < max_link_bpp_x16) { 2630 2585 max_link_bpp_x16 = throughput_max_bpp_x16; 2631 2586 ··· 2643 2592 limits->link.max_bpp_x16 = max_link_bpp_x16; 2644 2593 2645 2594 drm_dbg_kms(display->drm, 2646 2646 - "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n", 2595 2595 + "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d min link_bpp " FXP_Q4_FMT " max link_bpp " FXP_Q4_FMT "\n", 2647 2596 encoder->base.base.id, encoder->base.name, 2648 2597 crtc->base.base.id, crtc->base.name, 2649 2598 adjusted_mode->crtc_clock, ··· 2651 2600 limits->max_lane_count, 2652 2601 limits->max_rate, 2653 2602 limits->pipe.max_bpp, 2603 2603 + FXP_Q4_ARGS(limits->link.min_bpp_x16), 2654 2604 FXP_Q4_ARGS(limits->link.max_bpp_x16)); 2605 2605 + 2606 2606 + if (limits->link.min_bpp_x16 <= 0 || 2607 2607 + limits->link.min_bpp_x16 > limits->link.max_bpp_x16) 2608 2608 + return false; 2655 2609 2656 2610 return true; 2657 2611 } 2658 2612 2659 2659 - static void 2660 2660 - intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp *intel_dp, 2613 2613 + static bool 2614 2614 + intel_dp_dsc_compute_pipe_bpp_limits(struct intel_connector *connector, 2661 2615 struct link_config_limits *limits) 2662 2616 { 2663 2663 - struct intel_display *display = to_intel_display(intel_dp); 2617 2617 + struct intel_display *display = to_intel_display(connector); 2618 2618 + const struct link_config_limits orig_limits = *limits; 2664 2619 int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(); 2665 2620 int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); 2666 2621 2667 2667 - limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3); 2668 2668 - limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3); 2622 2622 + limits->pipe.min_bpp = max(limits->pipe.min_bpp, dsc_min_bpc * 3); 2623 2623 + limits->pipe.max_bpp = min(limits->pipe.max_bpp, dsc_max_bpc * 3); 2624 2624 + 2625 2625 + if (limits->pipe.min_bpp <= 0 || 2626 2626 + limits->pipe.min_bpp > limits->pipe.max_bpp) { 2627 2627 + drm_dbg_kms(display->drm, 2628 2628 + "[CONNECTOR:%d:%s] Invalid DSC src/sink input BPP (src:%d-%d pipe:%d-%d)\n", 2629 2629 + connector->base.base.id, connector->base.name, 2630 2630 + dsc_min_bpc * 3, dsc_max_bpc * 3, 2631 2631 + orig_limits.pipe.min_bpp, orig_limits.pipe.max_bpp); 2632 2632 + 2633 2633 + return false; 2634 2634 + } 2635 2635 + 2636 2636 + return true; 2669 2637 } 2670 2638 2671 2639 bool ··· 2724 2654 respect_downstream_limits); 2725 2655 } 2726 2656 2727 2727 - if (dsc) 2728 2728 - intel_dp_dsc_compute_pipe_bpp_limits(intel_dp, limits); 2657 2657 + if (dsc && !intel_dp_dsc_compute_pipe_bpp_limits(connector, limits)) 2658 2658 + return false; 2729 2659 2730 2660 if (is_mst || intel_dp->use_max_params) { 2731 2661 /* ··· 2756 2686 { 2757 2687 const struct drm_display_mode *adjusted_mode = 2758 2688 &crtc_state->hw.adjusted_mode; 2759 2759 - int bpp = crtc_state->dsc.compression_enable ? 2760 2760 - fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) : 2761 2761 - crtc_state->pipe_bpp; 2689 2689 + int link_bpp_x16 = crtc_state->dsc.compression_enable ? 2690 2690 + crtc_state->dsc.compressed_bpp_x16 : 2691 2691 + fxp_q4_from_int(crtc_state->pipe_bpp); 2762 2692 2763 2763 - return intel_dp_link_required(adjusted_mode->crtc_clock, bpp); 2693 2693 + return intel_dp_link_required(crtc_state->port_clock, crtc_state->lane_count, 2694 2694 + adjusted_mode->crtc_clock, adjusted_mode->hdisplay, 2695 2695 + link_bpp_x16, 0); 2764 2696 } 2765 2697 2766 2698 bool intel_dp_joiner_needs_dsc(struct intel_display *display, ··· 3331 3259 if (crtc_state->dsc.compression_enable) 3332 3260 link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16; 3333 3261 else 3334 3334 - link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, 3335 3335 - crtc_state->pipe_bpp)); 3262 3262 + link_bpp_x16 = intel_dp_output_format_link_bpp_x16(crtc_state->output_format, 3263 3263 + crtc_state->pipe_bpp); 3336 3264 3337 3265 /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */ 3338 3266 hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count, ··· 3442 3370 if (pipe_config->dsc.compression_enable) 3443 3371 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; 3444 3372 else 3445 3445 - link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format, 3446 3446 - pipe_config->pipe_bpp)); 3373 3373 + link_bpp_x16 = intel_dp_output_format_link_bpp_x16(pipe_config->output_format, 3374 3374 + pipe_config->pipe_bpp); 3447 3375 3448 3376 if (intel_dp->mso_link_count) { 3449 3377 int n = intel_dp->mso_link_count; ··· 4634 4562 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks 4635 4563 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] 4636 4564 */ 4637 4637 - intel_psr_init_dpcd(intel_dp); 4565 4565 + intel_psr_init_dpcd(intel_dp, connector); 4638 4566 4639 4567 intel_edp_set_sink_rates(intel_dp); 4640 4568 intel_dp_set_max_sink_lane_count(intel_dp); ··· 5863 5791 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 5864 5792 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port); 5865 5793 bool is_connected = false; 5866 5866 - intel_wakeref_t wakeref; 5867 5794 5868 5868 - with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { 5795 5795 + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) { 5869 5796 poll_timeout_us(is_connected = dig_port->connected(encoder), 5870 5797 is_connected || is_glitch_free, 5871 5798 30, 4000, false); ··· 6120 6049 6121 6050 if (status == connector_status_disconnected) { 6122 6051 intel_dp_test_reset(intel_dp); 6052 6052 + /* 6053 6053 + * FIXME: Resetting these caps here cause 6054 6054 + * state computation fail if the connector need to be 6055 6055 + * modeset after sink disconnect. Move resetting them 6056 6056 + * to where new sink is connected. 6057 6057 + */ 6123 6058 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); 6059 6059 + memset(connector->dp.panel_replay_caps.dpcd, 0, 6060 6060 + sizeof(connector->dp.panel_replay_caps.dpcd)); 6124 6061 intel_dp->psr.sink_panel_replay_support = false; 6125 6125 - intel_dp->psr.sink_panel_replay_su_support = false; 6126 6126 - intel_dp->psr.sink_panel_replay_dsc_support = 6062 6062 + connector->dp.panel_replay_caps.support = false; 6063 6063 + connector->dp.panel_replay_caps.su_support = false; 6064 6064 + connector->dp.panel_replay_caps.dsc_support = 6127 6065 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED; 6128 6066 6129 6067 intel_dp_mst_disconnect(intel_dp); ··· 6155 6075 connector->base.epoch_counter++; 6156 6076 6157 6077 if (!intel_dp_is_edp(intel_dp)) 6158 6158 - intel_psr_init_dpcd(intel_dp); 6078 6078 + intel_psr_init_dpcd(intel_dp, connector); 6159 6079 6160 6080 intel_dp_detect_dsc_caps(intel_dp, connector); 6161 6081

+7 -2

drivers/gpu/drm/i915/display/intel_dp.h

reviewed

··· 117 117 bool intel_dp_source_supports_tps3(struct intel_display *display); 118 118 bool intel_dp_source_supports_tps4(struct intel_display *display); 119 119 120 120 - int intel_dp_link_required(int pixel_clock, int bpp); 120 120 + int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, 121 121 + int dsc_slice_count, int bpp_x16, unsigned long flags); 122 122 + int intel_dp_link_required(int link_clock, int lane_count, 123 123 + int mode_clock, int mode_hdisplay, 124 124 + int link_bpp_x16, unsigned long bw_overhead_flags); 121 125 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, 122 126 int bw_overhead); 123 127 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, ··· 197 193 198 194 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp); 199 195 void intel_dp_wait_source_oui(struct intel_dp *intel_dp); 200 200 - int intel_dp_output_bpp(enum intel_output_format output_format, int bpp); 196 196 + int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format, 197 197 + int pipe_bpp); 201 198 202 199 bool intel_dp_compute_config_limits(struct intel_dp *intel_dp, 203 200 struct drm_connector_state *conn_state,

+9 -7

drivers/gpu/drm/i915/display/intel_dp_aux.c

reviewed

··· 6 6 #include <drm/drm_print.h> 7 7 8 8 #include "intel_de.h" 9 9 + #include "intel_display_jiffies.h" 9 10 #include "intel_display_types.h" 10 11 #include "intel_display_utils.h" 11 12 #include "intel_dp.h" ··· 61 60 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 62 61 const unsigned int timeout_ms = 10; 63 62 u32 status; 64 64 - int ret; 63 63 + bool done; 65 64 66 66 - ret = intel_de_wait_ms(display, ch_ctl, 67 67 - DP_AUX_CH_CTL_SEND_BUSY, 0, 68 68 - timeout_ms, &status); 65 65 + #define C (((status = intel_de_read_notrace(display, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 66 66 + done = wait_event_timeout(display->gmbus.wait_queue, C, 67 67 + msecs_to_jiffies_timeout(timeout_ms)); 69 68 70 70 - if (ret == -ETIMEDOUT) 69 69 + if (!done) 71 70 drm_err(display->drm, 72 71 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 73 72 intel_dp->aux.name, timeout_ms, status); 73 73 + #undef C 74 74 75 75 return status; 76 76 } ··· 247 245 i915_reg_t ch_ctl, ch_data[5]; 248 246 u32 aux_clock_divider; 249 247 enum intel_display_power_domain aux_domain; 250 250 - intel_wakeref_t aux_wakeref; 251 251 - intel_wakeref_t pps_wakeref = NULL; 248 248 + struct ref_tracker *aux_wakeref; 249 249 + struct ref_tracker *pps_wakeref = NULL; 252 250 int i, ret, recv_bytes; 253 251 int try, clock = 0; 254 252 u32 status;

+3 -1

drivers/gpu/drm/i915/display/intel_dp_link_training.c

reviewed

··· 1195 1195 intel_panel_preferred_fixed_mode(intel_dp->attached_connector); 1196 1196 int mode_rate, max_rate; 1197 1197 1198 1198 - mode_rate = intel_dp_link_required(fixed_mode->clock, 18); 1198 1198 + mode_rate = intel_dp_link_required(link_rate, lane_count, 1199 1199 + fixed_mode->clock, fixed_mode->hdisplay, 1200 1200 + fxp_q4_from_int(18), 0); 1199 1201 max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); 1200 1202 if (mode_rate > max_rate) 1201 1203 return false;

+14 -19

drivers/gpu/drm/i915/display/intel_dp_mst.c

reviewed

··· 180 180 const struct drm_display_mode *adjusted_mode = 181 181 &crtc_state->hw.adjusted_mode; 182 182 unsigned long flags = DRM_DP_BW_OVERHEAD_MST; 183 183 - int overhead; 184 183 185 185 - flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0; 186 184 flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0; 187 185 flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; 188 186 189 189 - if (dsc_slice_count) 190 190 - flags |= DRM_DP_BW_OVERHEAD_DSC; 191 191 - 192 192 - overhead = drm_dp_bw_overhead(crtc_state->lane_count, 193 193 - adjusted_mode->hdisplay, 194 194 - dsc_slice_count, 195 195 - bpp_x16, 196 196 - flags); 197 197 - 198 198 - /* 199 199 - * TODO: clarify whether a minimum required by the fixed FEC overhead 200 200 - * in the bspec audio programming sequence is required here. 201 201 - */ 202 202 - return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable)); 187 187 + return intel_dp_link_bw_overhead(crtc_state->port_clock, 188 188 + crtc_state->lane_count, 189 189 + adjusted_mode->hdisplay, 190 190 + dsc_slice_count, 191 191 + bpp_x16, 192 192 + flags); 203 193 } 204 194 205 195 static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, ··· 334 344 } 335 345 336 346 link_bpp_x16 = dsc ? bpp_x16 : 337 337 - fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, 338 338 - fxp_q4_to_int(bpp_x16))); 347 347 + intel_dp_output_format_link_bpp_x16(crtc_state->output_format, 348 348 + fxp_q4_to_int(bpp_x16)); 339 349 340 350 local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, 341 351 false, dsc_slice_count, link_bpp_x16); ··· 1458 1468 const int min_bpp = 18; 1459 1469 int max_dotclk = display->cdclk.max_dotclk_freq; 1460 1470 int max_rate, mode_rate, max_lanes, max_link_clock; 1471 1471 + unsigned long bw_overhead_flags = 1472 1472 + DRM_DP_BW_OVERHEAD_MST | DRM_DP_BW_OVERHEAD_SSC_REF_CLK; 1461 1473 int ret; 1462 1474 bool dsc = false; 1463 1475 u16 dsc_max_compressed_bpp = 0; ··· 1491 1499 1492 1500 max_rate = intel_dp_max_link_data_rate(intel_dp, 1493 1501 max_link_clock, max_lanes); 1494 1494 - mode_rate = intel_dp_link_required(mode->clock, min_bpp); 1502 1502 + mode_rate = intel_dp_link_required(max_link_clock, max_lanes, 1503 1503 + mode->clock, mode->hdisplay, 1504 1504 + fxp_q4_from_int(min_bpp), 1505 1505 + bw_overhead_flags); 1495 1506 1496 1507 /* 1497 1508 * TODO:

+2 -22

drivers/gpu/drm/i915/display/intel_dpll.c

reviewed

··· 1212 1212 return 0; 1213 1213 } 1214 1214 1215 1215 - static int mtl_crtc_compute_clock(struct intel_atomic_state *state, 1216 1216 - struct intel_crtc *crtc) 1217 1217 - { 1218 1218 - struct intel_crtc_state *crtc_state = 1219 1219 - intel_atomic_get_new_crtc_state(state, crtc); 1220 1220 - struct intel_encoder *encoder = 1221 1221 - intel_get_crtc_new_encoder(state, crtc_state); 1222 1222 - int ret; 1223 1223 - 1224 1224 - ret = intel_cx0pll_calc_state(crtc_state, encoder); 1225 1225 - if (ret) 1226 1226 - return ret; 1227 1227 - 1228 1228 - /* TODO: Do the readback via intel_dpll_compute() */ 1229 1229 - crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); 1230 1230 - 1231 1231 - crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1232 1232 - 1233 1233 - return 0; 1234 1234 - } 1235 1235 - 1236 1215 static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state, 1237 1216 struct intel_crtc *crtc) 1238 1217 { ··· 1698 1719 }; 1699 1720 1700 1721 static const struct intel_dpll_global_funcs mtl_dpll_funcs = { 1701 1701 - .crtc_compute_clock = mtl_crtc_compute_clock, 1722 1722 + .crtc_compute_clock = hsw_crtc_compute_clock, 1723 1723 + .crtc_get_dpll = hsw_crtc_get_dpll, 1702 1724 }; 1703 1725 1704 1726 static const struct intel_dpll_global_funcs dg2_dpll_funcs = {

+305 -31

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

reviewed

··· 203 203 return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1; 204 204 } 205 205 206 206 + enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port) 207 207 + { 208 208 + if (port >= PORT_TC1) 209 209 + return icl_tc_port_to_pll_id(intel_port_to_tc(display, port)); 210 210 + 211 211 + switch (port) { 212 212 + case PORT_A: 213 213 + return DPLL_ID_ICL_DPLL0; 214 214 + case PORT_B: 215 215 + return DPLL_ID_ICL_DPLL1; 216 216 + default: 217 217 + MISSING_CASE(port); 218 218 + return DPLL_ID_ICL_DPLL0; 219 219 + } 220 220 + } 221 221 + 206 222 static i915_reg_t 207 223 intel_combo_pll_enable_reg(struct intel_display *display, 208 224 struct intel_dpll *pll) ··· 547 531 { 548 532 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; 549 533 const enum intel_dpll_id id = pll->info->id; 550 550 - intel_wakeref_t wakeref; 534 534 + struct ref_tracker *wakeref; 551 535 u32 val; 552 536 553 537 wakeref = intel_display_power_get_if_enabled(display, ··· 768 752 { 769 753 struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; 770 754 const enum intel_dpll_id id = pll->info->id; 771 771 - intel_wakeref_t wakeref; 755 755 + struct ref_tracker *wakeref; 772 756 u32 val; 773 757 774 758 wakeref = intel_display_power_get_if_enabled(display, ··· 789 773 struct intel_dpll_hw_state *dpll_hw_state) 790 774 { 791 775 struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; 792 792 - intel_wakeref_t wakeref; 776 776 + struct ref_tracker *wakeref; 793 777 u32 val; 794 778 795 779 wakeref = intel_display_power_get_if_enabled(display, ··· 1447 1431 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; 1448 1432 const struct skl_dpll_regs *regs = skl_dpll_regs; 1449 1433 const enum intel_dpll_id id = pll->info->id; 1450 1450 - intel_wakeref_t wakeref; 1434 1434 + struct ref_tracker *wakeref; 1451 1435 bool ret; 1452 1436 u32 val; 1453 1437 ··· 1485 1469 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; 1486 1470 const struct skl_dpll_regs *regs = skl_dpll_regs; 1487 1471 const enum intel_dpll_id id = pll->info->id; 1488 1488 - intel_wakeref_t wakeref; 1472 1472 + struct ref_tracker *wakeref; 1489 1473 u32 val; 1490 1474 bool ret; 1491 1475 ··· 2188 2172 { 2189 2173 struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; 2190 2174 enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ 2191 2191 - intel_wakeref_t wakeref; 2175 2175 + struct ref_tracker *wakeref; 2192 2176 enum dpio_phy phy; 2193 2177 enum dpio_channel ch; 2194 2178 u32 val; ··· 3506 3490 return ret; 3507 3491 } 3508 3492 3493 3493 + /* 3494 3494 + * Get the PLL for either a port using a C10 PHY PLL, or for a port using a 3495 3495 + * C20 PHY PLL in the cases of: 3496 3496 + * - BMG port A/B 3497 3497 + * - PTL port B eDP over TypeC PHY 3498 3498 + */ 3499 3499 + static int mtl_get_non_tc_phy_dpll(struct intel_atomic_state *state, 3500 3500 + struct intel_crtc *crtc, 3501 3501 + struct intel_encoder *encoder) 3502 3502 + { 3503 3503 + struct intel_display *display = to_intel_display(crtc); 3504 3504 + struct intel_crtc_state *crtc_state = 3505 3505 + intel_atomic_get_new_crtc_state(state, crtc); 3506 3506 + struct icl_port_dpll *port_dpll = 3507 3507 + &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; 3508 3508 + enum intel_dpll_id pll_id = mtl_port_to_pll_id(display, encoder->port); 3509 3509 + 3510 3510 + port_dpll->pll = intel_find_dpll(state, crtc, 3511 3511 + &port_dpll->hw_state, 3512 3512 + BIT(pll_id)); 3513 3513 + if (!port_dpll->pll) 3514 3514 + return -EINVAL; 3515 3515 + 3516 3516 + intel_reference_dpll(state, crtc, 3517 3517 + port_dpll->pll, &port_dpll->hw_state); 3518 3518 + 3519 3519 + icl_update_active_dpll(state, crtc, encoder); 3520 3520 + 3521 3521 + return 0; 3522 3522 + } 3523 3523 + 3509 3524 static int icl_compute_dplls(struct intel_atomic_state *state, 3510 3525 struct intel_crtc *crtc, 3511 3526 struct intel_encoder *encoder) ··· 3598 3551 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; 3599 3552 const enum intel_dpll_id id = pll->info->id; 3600 3553 enum tc_port tc_port = icl_pll_id_to_tc_port(id); 3601 3601 - intel_wakeref_t wakeref; 3554 3554 + struct ref_tracker *wakeref; 3602 3555 bool ret = false; 3603 3556 u32 val; 3604 3557 ··· 3665 3618 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; 3666 3619 const enum intel_dpll_id id = pll->info->id; 3667 3620 enum tc_port tc_port = icl_pll_id_to_tc_port(id); 3668 3668 - intel_wakeref_t wakeref; 3621 3621 + struct ref_tracker *wakeref; 3669 3622 bool ret = false; 3670 3623 u32 val; 3671 3624 ··· 3737 3690 { 3738 3691 struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; 3739 3692 const enum intel_dpll_id id = pll->info->id; 3740 3740 - intel_wakeref_t wakeref; 3693 3693 + struct ref_tracker *wakeref; 3741 3694 bool ret = false; 3742 3695 u32 val; 3743 3696 ··· 3800 3753 return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg); 3801 3754 } 3802 3755 3803 3803 - static bool tbt_pll_get_hw_state(struct intel_display *display, 3804 3804 - struct intel_dpll *pll, 3805 3805 - struct intel_dpll_hw_state *dpll_hw_state) 3756 3756 + static bool icl_tbt_pll_get_hw_state(struct intel_display *display, 3757 3757 + struct intel_dpll *pll, 3758 3758 + struct intel_dpll_hw_state *dpll_hw_state) 3806 3759 { 3807 3760 return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE); 3808 3761 } ··· 4031 3984 /* DVFS post sequence would be here. See the comment above. */ 4032 3985 } 4033 3986 4034 4034 - static void tbt_pll_enable(struct intel_display *display, 4035 4035 - struct intel_dpll *pll, 4036 4036 - const struct intel_dpll_hw_state *dpll_hw_state) 3987 3987 + static void icl_tbt_pll_enable(struct intel_display *display, 3988 3988 + struct intel_dpll *pll, 3989 3989 + const struct intel_dpll_hw_state *dpll_hw_state) 4037 3990 { 4038 3991 const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; 4039 3992 ··· 4116 4069 icl_pll_disable(display, pll, enable_reg); 4117 4070 } 4118 4071 4119 4119 - static void tbt_pll_disable(struct intel_display *display, 4120 4120 - struct intel_dpll *pll) 4072 4072 + static void icl_tbt_pll_disable(struct intel_display *display, 4073 4073 + struct intel_dpll *pll) 4121 4074 { 4122 4075 icl_pll_disable(display, pll, TBT_PLL_ENABLE); 4123 4076 } ··· 4189 4142 .get_freq = icl_ddi_combo_pll_get_freq, 4190 4143 }; 4191 4144 4192 4192 - static const struct intel_dpll_funcs tbt_pll_funcs = { 4193 4193 - .enable = tbt_pll_enable, 4194 4194 - .disable = tbt_pll_disable, 4195 4195 - .get_hw_state = tbt_pll_get_hw_state, 4145 4145 + static const struct intel_dpll_funcs icl_tbt_pll_funcs = { 4146 4146 + .enable = icl_tbt_pll_enable, 4147 4147 + .disable = icl_tbt_pll_disable, 4148 4148 + .get_hw_state = icl_tbt_pll_get_hw_state, 4196 4149 .get_freq = icl_ddi_tbt_pll_get_freq, 4197 4150 }; 4198 4151 ··· 4206 4159 static const struct dpll_info icl_plls[] = { 4207 4160 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, 4208 4161 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, 4209 4209 - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, 4162 4162 + { .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, 4210 4163 .is_alt_port_dpll = true, }, 4211 4164 { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, 4212 4165 { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, ··· 4254 4207 static const struct dpll_info tgl_plls[] = { 4255 4208 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, 4256 4209 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, 4257 4257 - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, 4210 4210 + { .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, 4258 4211 .is_alt_port_dpll = true, }, 4259 4212 { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, 4260 4213 { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, ··· 4332 4285 static const struct dpll_info adlp_plls[] = { 4333 4286 { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, 4334 4287 { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, 4335 4335 - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, 4288 4288 + { .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, 4336 4289 .is_alt_port_dpll = true, }, 4337 4290 { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, 4338 4291 { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, ··· 4352 4305 .compare_hw_state = icl_compare_hw_state, 4353 4306 }; 4354 4307 4308 4308 + static struct intel_encoder *get_intel_encoder(struct intel_display *display, 4309 4309 + const struct intel_dpll *pll) 4310 4310 + { 4311 4311 + struct intel_encoder *encoder; 4312 4312 + enum intel_dpll_id mtl_id; 4313 4313 + 4314 4314 + for_each_intel_encoder(display->drm, encoder) { 4315 4315 + mtl_id = mtl_port_to_pll_id(display, encoder->port); 4316 4316 + 4317 4317 + if (mtl_id == pll->info->id) 4318 4318 + return encoder; 4319 4319 + } 4320 4320 + 4321 4321 + return NULL; 4322 4322 + } 4323 4323 + 4324 4324 + static bool mtl_pll_get_hw_state(struct intel_display *display, 4325 4325 + struct intel_dpll *pll, 4326 4326 + struct intel_dpll_hw_state *dpll_hw_state) 4327 4327 + { 4328 4328 + struct intel_encoder *encoder = get_intel_encoder(display, pll); 4329 4329 + 4330 4330 + if (!encoder) 4331 4331 + return false; 4332 4332 + 4333 4333 + return intel_cx0pll_readout_hw_state(encoder, &dpll_hw_state->cx0pll); 4334 4334 + } 4335 4335 + 4336 4336 + static int mtl_pll_get_freq(struct intel_display *display, 4337 4337 + const struct intel_dpll *pll, 4338 4338 + const struct intel_dpll_hw_state *dpll_hw_state) 4339 4339 + { 4340 4340 + struct intel_encoder *encoder = get_intel_encoder(display, pll); 4341 4341 + 4342 4342 + if (drm_WARN_ON(display->drm, !encoder)) 4343 4343 + return -EINVAL; 4344 4344 + 4345 4345 + return intel_cx0pll_calc_port_clock(encoder, &dpll_hw_state->cx0pll); 4346 4346 + } 4347 4347 + 4348 4348 + static void mtl_pll_enable(struct intel_display *display, 4349 4349 + struct intel_dpll *pll, 4350 4350 + const struct intel_dpll_hw_state *dpll_hw_state) 4351 4351 + { 4352 4352 + struct intel_encoder *encoder = get_intel_encoder(display, pll); 4353 4353 + 4354 4354 + if (drm_WARN_ON(display->drm, !encoder)) 4355 4355 + return; 4356 4356 + 4357 4357 + intel_mtl_pll_enable(encoder, pll, dpll_hw_state); 4358 4358 + } 4359 4359 + 4360 4360 + static void mtl_pll_disable(struct intel_display *display, 4361 4361 + struct intel_dpll *pll) 4362 4362 + { 4363 4363 + struct intel_encoder *encoder = get_intel_encoder(display, pll); 4364 4364 + 4365 4365 + if (drm_WARN_ON(display->drm, !encoder)) 4366 4366 + return; 4367 4367 + 4368 4368 + intel_mtl_pll_disable(encoder); 4369 4369 + } 4370 4370 + 4371 4371 + static const struct intel_dpll_funcs mtl_pll_funcs = { 4372 4372 + .enable = mtl_pll_enable, 4373 4373 + .disable = mtl_pll_disable, 4374 4374 + .get_hw_state = mtl_pll_get_hw_state, 4375 4375 + .get_freq = mtl_pll_get_freq, 4376 4376 + }; 4377 4377 + 4378 4378 + static void mtl_tbt_pll_enable(struct intel_display *display, 4379 4379 + struct intel_dpll *pll, 4380 4380 + const struct intel_dpll_hw_state *hw_state) 4381 4381 + { 4382 4382 + } 4383 4383 + 4384 4384 + static void mtl_tbt_pll_disable(struct intel_display *display, 4385 4385 + struct intel_dpll *pll) 4386 4386 + { 4387 4387 + } 4388 4388 + 4389 4389 + static int mtl_tbt_pll_get_freq(struct intel_display *display, 4390 4390 + const struct intel_dpll *pll, 4391 4391 + const struct intel_dpll_hw_state *dpll_hw_state) 4392 4392 + { 4393 4393 + /* 4394 4394 + * The PLL outputs multiple frequencies at the same time, selection is 4395 4395 + * made at DDI clock mux level. 4396 4396 + */ 4397 4397 + drm_WARN_ON(display->drm, 1); 4398 4398 + 4399 4399 + return 0; 4400 4400 + } 4401 4401 + 4402 4402 + static const struct intel_dpll_funcs mtl_tbt_pll_funcs = { 4403 4403 + .enable = mtl_tbt_pll_enable, 4404 4404 + .disable = mtl_tbt_pll_disable, 4405 4405 + .get_hw_state = intel_mtl_tbt_pll_readout_hw_state, 4406 4406 + .get_freq = mtl_tbt_pll_get_freq, 4407 4407 + }; 4408 4408 + 4409 4409 + static const struct dpll_info mtl_plls[] = { 4410 4410 + { .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, 4411 4411 + { .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, 4412 4412 + { .name = "TBT PLL", .funcs = &mtl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, 4413 4413 + .is_alt_port_dpll = true, .always_on = true }, 4414 4414 + { .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, 4415 4415 + { .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, 4416 4416 + { .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, }, 4417 4417 + { .name = "TC PLL 4", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, }, 4418 4418 + {} 4419 4419 + }; 4420 4420 + 4421 4421 + /* 4422 4422 + * Compute the state for either a C10 PHY PLL, or in the case of the PTL port B, 4423 4423 + * eDP on TypeC PHY case for a C20 PHY PLL. 4424 4424 + */ 4425 4425 + static int mtl_compute_non_tc_phy_dpll(struct intel_atomic_state *state, 4426 4426 + struct intel_crtc *crtc, 4427 4427 + struct intel_encoder *encoder) 4428 4428 + { 4429 4429 + struct intel_crtc_state *crtc_state = 4430 4430 + intel_atomic_get_new_crtc_state(state, crtc); 4431 4431 + struct icl_port_dpll *port_dpll = 4432 4432 + &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; 4433 4433 + int ret; 4434 4434 + 4435 4435 + ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state); 4436 4436 + if (ret) 4437 4437 + return ret; 4438 4438 + 4439 4439 + /* this is mainly for the fastset check */ 4440 4440 + icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); 4441 4441 + 4442 4442 + crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, 4443 4443 + &port_dpll->hw_state.cx0pll); 4444 4444 + 4445 4445 + return 0; 4446 4446 + } 4447 4447 + 4448 4448 + static int mtl_compute_tc_phy_dplls(struct intel_atomic_state *state, 4449 4449 + struct intel_crtc *crtc, 4450 4450 + struct intel_encoder *encoder) 4451 4451 + { 4452 4452 + struct intel_crtc_state *crtc_state = 4453 4453 + intel_atomic_get_new_crtc_state(state, crtc); 4454 4454 + const struct intel_crtc_state *old_crtc_state = 4455 4455 + intel_atomic_get_old_crtc_state(state, crtc); 4456 4456 + struct icl_port_dpll *port_dpll; 4457 4457 + int ret; 4458 4458 + 4459 4459 + port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; 4460 4460 + intel_mtl_tbt_pll_calc_state(&port_dpll->hw_state); 4461 4461 + 4462 4462 + port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; 4463 4463 + ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state); 4464 4464 + if (ret) 4465 4465 + return ret; 4466 4466 + 4467 4467 + /* this is mainly for the fastset check */ 4468 4468 + if (old_crtc_state->intel_dpll && 4469 4469 + old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL) 4470 4470 + icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); 4471 4471 + else 4472 4472 + icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY); 4473 4473 + 4474 4474 + crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, 4475 4475 + &port_dpll->hw_state.cx0pll); 4476 4476 + 4477 4477 + return 0; 4478 4478 + } 4479 4479 + 4480 4480 + static int mtl_compute_dplls(struct intel_atomic_state *state, 4481 4481 + struct intel_crtc *crtc, 4482 4482 + struct intel_encoder *encoder) 4483 4483 + { 4484 4484 + if (intel_encoder_is_tc(encoder)) 4485 4485 + return mtl_compute_tc_phy_dplls(state, crtc, encoder); 4486 4486 + else 4487 4487 + return mtl_compute_non_tc_phy_dpll(state, crtc, encoder); 4488 4488 + } 4489 4489 + 4490 4490 + static int mtl_get_dplls(struct intel_atomic_state *state, 4491 4491 + struct intel_crtc *crtc, 4492 4492 + struct intel_encoder *encoder) 4493 4493 + { 4494 4494 + if (intel_encoder_is_tc(encoder)) 4495 4495 + return icl_get_tc_phy_dplls(state, crtc, encoder); 4496 4496 + else 4497 4497 + return mtl_get_non_tc_phy_dpll(state, crtc, encoder); 4498 4498 + } 4499 4499 + 4500 4500 + static void mtl_dump_hw_state(struct drm_printer *p, 4501 4501 + const struct intel_dpll_hw_state *dpll_hw_state) 4502 4502 + { 4503 4503 + intel_cx0pll_dump_hw_state(p, &dpll_hw_state->cx0pll); 4504 4504 + } 4505 4505 + 4506 4506 + static bool mtl_compare_hw_state(const struct intel_dpll_hw_state *_a, 4507 4507 + const struct intel_dpll_hw_state *_b) 4508 4508 + { 4509 4509 + const struct intel_cx0pll_state *a = &_a->cx0pll; 4510 4510 + const struct intel_cx0pll_state *b = &_b->cx0pll; 4511 4511 + 4512 4512 + return intel_cx0pll_compare_hw_state(a, b); 4513 4513 + } 4514 4514 + 4515 4515 + static const struct intel_dpll_mgr mtl_pll_mgr = { 4516 4516 + .dpll_info = mtl_plls, 4517 4517 + .compute_dplls = mtl_compute_dplls, 4518 4518 + .get_dplls = mtl_get_dplls, 4519 4519 + .put_dplls = icl_put_dplls, 4520 4520 + .update_active_dpll = icl_update_active_dpll, 4521 4521 + .update_ref_clks = icl_update_dpll_ref_clks, 4522 4522 + .dump_hw_state = mtl_dump_hw_state, 4523 4523 + .compare_hw_state = mtl_compare_hw_state, 4524 4524 + }; 4525 4525 + 4355 4526 /** 4356 4527 * intel_dpll_init - Initialize DPLLs 4357 4528 * @display: intel_display device ··· 4584 4319 4585 4320 mutex_init(&display->dpll.lock); 4586 4321 4587 4587 - if (DISPLAY_VER(display) >= 14 || display->platform.dg2) 4588 4588 - /* No shared DPLLs on DG2; port PLLs are part of the PHY */ 4322 4322 + if (DISPLAY_VER(display) >= 35 || display->platform.dg2) 4323 4323 + /* No shared DPLLs on NVL or DG2; port PLLs are part of the PHY */ 4589 4324 dpll_mgr = NULL; 4325 4325 + else if (DISPLAY_VER(display) >= 14) 4326 4326 + dpll_mgr = &mtl_pll_mgr; 4590 4327 else if (display->platform.alderlake_p) 4591 4328 dpll_mgr = &adlp_pll_mgr; 4592 4329 else if (display->platform.alderlake_s) ··· 4942 4675 "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", 4943 4676 pll->info->name, pipe_mask, pll->state.pipe_mask); 4944 4677 4945 4945 - INTEL_DISPLAY_STATE_WARN(display, 4946 4946 - pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, 4947 4947 - sizeof(dpll_hw_state)), 4948 4948 - "%s: pll hw state mismatch\n", 4949 4949 - pll->info->name); 4678 4678 + if (INTEL_DISPLAY_STATE_WARN(display, 4679 4679 + pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, 4680 4680 + sizeof(dpll_hw_state)), 4681 4681 + "%s: pll hw state mismatch\n", 4682 4682 + pll->info->name)) { 4683 4683 + struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL); 4684 4684 + 4685 4685 + drm_printf(&p, "PLL %s HW state:\n", pll->info->name); 4686 4686 + intel_dpll_dump_hw_state(display, &p, &dpll_hw_state); 4687 4687 + drm_printf(&p, "PLL %s SW state:\n", pll->info->name); 4688 4688 + intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state); 4689 4689 + } 4950 4690 } 4951 4691 4952 4692 static bool has_alt_port_dpll(const struct intel_dpll *old_pll,

+9 -2

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

reviewed

··· 28 28 #include <linux/types.h> 29 29 30 30 #include "intel_display_power.h" 31 31 - #include "intel_wakeref.h" 32 31 33 32 #define for_each_dpll(__display, __pll, __i) \ 34 33 for ((__i) = 0; (__i) < (__display)->dpll.num_dpll && \ ··· 41 42 struct intel_dpll_funcs; 42 43 struct intel_encoder; 43 44 struct intel_shared_dpll; 45 45 + struct ref_tracker; 44 46 45 47 /** 46 48 * enum intel_dpll_id - possible DPLL ids ··· 255 255 u16 mplla[10]; 256 256 u16 mpllb[11]; 257 257 }; 258 258 + struct intel_c20pll_vdr_state { 259 259 + u8 custom_width; 260 260 + u8 serdes_rate; 261 261 + u8 hdmi_rate; 262 262 + } vdr; 258 263 }; 259 264 260 265 struct intel_cx0pll_state { ··· 267 262 struct intel_c10pll_state c10; 268 263 struct intel_c20pll_state c20; 269 264 }; 265 265 + int lane_count; 270 266 bool ssc_enabled; 271 267 bool use_c10; 272 268 bool tbt_mode; ··· 396 390 * @wakeref: In some platforms a device-level runtime pm reference may 397 391 * need to be grabbed to disable DC states while this DPLL is enabled 398 392 */ 399 399 - intel_wakeref_t wakeref; 393 393 + struct ref_tracker *wakeref; 400 394 }; 401 395 402 396 #define SKL_DPLL0 0 ··· 450 444 const struct intel_dpll_hw_state *a, 451 445 const struct intel_dpll_hw_state *b); 452 446 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); 447 447 + enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port); 453 448 bool intel_dpll_is_combophy(enum intel_dpll_id id); 454 449 455 450 void intel_dpll_state_verify(struct intel_atomic_state *state,

+23 -19

drivers/gpu/drm/i915/display/intel_dsb.c

reviewed

··· 26 26 struct intel_dsb { 27 27 enum intel_dsb_id id; 28 28 29 29 - struct intel_dsb_buffer dsb_buf; 29 29 + struct intel_dsb_buffer *dsb_buf; 30 30 struct intel_crtc *crtc; 31 31 32 32 /* ··· 211 211 for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4) 212 212 drm_dbg_kms(display->drm, 213 213 " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", i * 4, 214 214 - intel_dsb_buffer_read(&dsb->dsb_buf, i), 215 215 - intel_dsb_buffer_read(&dsb->dsb_buf, i + 1), 216 216 - intel_dsb_buffer_read(&dsb->dsb_buf, i + 2), 217 217 - intel_dsb_buffer_read(&dsb->dsb_buf, i + 3)); 214 214 + intel_dsb_buffer_read(dsb->dsb_buf, i), 215 215 + intel_dsb_buffer_read(dsb->dsb_buf, i + 1), 216 216 + intel_dsb_buffer_read(dsb->dsb_buf, i + 2), 217 217 + intel_dsb_buffer_read(dsb->dsb_buf, i + 3)); 218 218 drm_dbg_kms(display->drm, "}\n"); 219 219 } 220 220 ··· 231 231 232 232 unsigned int intel_dsb_head(struct intel_dsb *dsb) 233 233 { 234 234 - return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); 234 234 + return intel_dsb_buffer_ggtt_offset(dsb->dsb_buf); 235 235 } 236 236 237 237 static unsigned int intel_dsb_tail(struct intel_dsb *dsb) 238 238 { 239 239 - return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + intel_dsb_size(dsb); 239 239 + return intel_dsb_buffer_ggtt_offset(dsb->dsb_buf) + intel_dsb_size(dsb); 240 240 } 241 241 242 242 static void intel_dsb_ins_align(struct intel_dsb *dsb) ··· 263 263 dsb->ins[0] = ldw; 264 264 dsb->ins[1] = udw; 265 265 266 266 - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, dsb->ins[0]); 267 267 - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, dsb->ins[1]); 266 266 + intel_dsb_buffer_write(dsb->dsb_buf, dsb->free_pos++, dsb->ins[0]); 267 267 + intel_dsb_buffer_write(dsb->dsb_buf, dsb->free_pos++, dsb->ins[1]); 268 268 } 269 269 270 270 static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, ··· 335 335 336 336 /* Update the count */ 337 337 dsb->ins[0]++; 338 338 - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 0, 338 338 + intel_dsb_buffer_write(dsb->dsb_buf, dsb->ins_start_offset + 0, 339 339 dsb->ins[0]); 340 340 341 341 - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, val); 341 341 + intel_dsb_buffer_write(dsb->dsb_buf, dsb->free_pos++, val); 342 342 /* if number of data words is odd, then the last dword should be 0.*/ 343 343 if (dsb->free_pos & 0x1) 344 344 - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos, 0); 344 344 + intel_dsb_buffer_write(dsb->dsb_buf, dsb->free_pos, 0); 345 345 } 346 346 347 347 void intel_dsb_reg_write(struct intel_dsb *dsb, ··· 521 521 aligned_tail = ALIGN(tail, CACHELINE_BYTES); 522 522 523 523 if (aligned_tail > tail) 524 524 - intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0, 524 524 + intel_dsb_buffer_memset(dsb->dsb_buf, dsb->free_pos, 0, 525 525 aligned_tail - tail); 526 526 527 527 dsb->free_pos = aligned_tail / 4; ··· 541 541 * "Ensure GOSUB is not placed in cacheline QW slot 6 or 7 (numbered 0-7)" 542 542 */ 543 543 if (aligned_tail - tail <= 2 * 8) 544 544 - intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0, 544 544 + intel_dsb_buffer_memset(dsb->dsb_buf, dsb->free_pos, 0, 545 545 aligned_tail - tail); 546 546 547 547 dsb->free_pos = aligned_tail / 4; ··· 606 606 */ 607 607 intel_dsb_noop(dsb, 8); 608 608 609 609 - intel_dsb_buffer_flush_map(&dsb->dsb_buf); 609 609 + intel_dsb_buffer_flush_map(dsb->dsb_buf); 610 610 } 611 611 612 612 void intel_dsb_finish(struct intel_dsb *dsb) 613 613 { 614 614 intel_dsb_align_tail(dsb); 615 615 616 616 - intel_dsb_buffer_flush_map(&dsb->dsb_buf); 616 616 + intel_dsb_buffer_flush_map(dsb->dsb_buf); 617 617 } 618 618 619 619 static u32 dsb_error_int_status(struct intel_display *display) ··· 888 888 !is_busy, 889 889 100, 1000, false); 890 890 if (ret) { 891 891 - u32 offset = intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); 891 891 + u32 offset = intel_dsb_buffer_ggtt_offset(dsb->dsb_buf); 892 892 893 893 intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 894 894 DSB_ENABLE | DSB_HALT); ··· 934 934 unsigned int max_cmds) 935 935 { 936 936 struct intel_display *display = to_intel_display(state); 937 937 + struct intel_dsb_buffer *dsb_buf; 937 938 struct ref_tracker *wakeref; 938 939 struct intel_dsb *dsb; 939 940 unsigned int size; ··· 954 953 /* ~1 qword per instruction, full cachelines */ 955 954 size = ALIGN(max_cmds * 8, CACHELINE_BYTES); 956 955 957 957 - if (!intel_dsb_buffer_create(crtc, &dsb->dsb_buf, size)) 956 956 + dsb_buf = intel_dsb_buffer_create(display->drm, size); 957 957 + if (IS_ERR(dsb_buf)) 958 958 goto out_put_rpm; 959 959 + 960 960 + dsb->dsb_buf = dsb_buf; 959 961 960 962 intel_display_rpm_put(display, wakeref); 961 963 ··· 992 988 */ 993 989 void intel_dsb_cleanup(struct intel_dsb *dsb) 994 990 { 995 995 - intel_dsb_buffer_cleanup(&dsb->dsb_buf); 991 991 + intel_dsb_buffer_cleanup(dsb->dsb_buf); 996 992 kfree(dsb); 997 993 } 998 994

+33 -10

drivers/gpu/drm/i915/display/intel_dsb_buffer.c

reviewed

··· 7 7 #include "gem/i915_gem_lmem.h" 8 8 #include "i915_drv.h" 9 9 #include "i915_vma.h" 10 10 - #include "intel_display_types.h" 11 10 #include "intel_dsb_buffer.h" 11 11 + 12 12 + struct intel_dsb_buffer { 13 13 + u32 *cmd_buf; 14 14 + struct i915_vma *vma; 15 15 + size_t buf_size; 16 16 + }; 12 17 13 18 u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf) 14 19 { ··· 37 32 memset(&dsb_buf->cmd_buf[idx], val, size); 38 33 } 39 34 40 40 - bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size) 35 35 + struct intel_dsb_buffer *intel_dsb_buffer_create(struct drm_device *drm, size_t size) 41 36 { 42 42 - struct drm_i915_private *i915 = to_i915(crtc->base.dev); 37 37 + struct drm_i915_private *i915 = to_i915(drm); 38 38 + struct intel_dsb_buffer *dsb_buf; 43 39 struct drm_i915_gem_object *obj; 44 40 struct i915_vma *vma; 45 41 u32 *buf; 42 42 + int ret; 43 43 + 44 44 + dsb_buf = kzalloc(sizeof(*dsb_buf), GFP_KERNEL); 45 45 + if (!dsb_buf) 46 46 + return ERR_PTR(-ENOMEM); 46 47 47 48 if (HAS_LMEM(i915)) { 48 49 obj = i915_gem_object_create_lmem(i915, PAGE_ALIGN(size), 49 50 I915_BO_ALLOC_CONTIGUOUS); 50 50 - if (IS_ERR(obj)) 51 51 - return false; 51 51 + if (IS_ERR(obj)) { 52 52 + ret = PTR_ERR(obj); 53 53 + goto err; 54 54 + } 52 55 } else { 53 56 obj = i915_gem_object_create_internal(i915, PAGE_ALIGN(size)); 54 54 - if (IS_ERR(obj)) 55 55 - return false; 57 57 + if (IS_ERR(obj)) { 58 58 + ret = PTR_ERR(obj); 59 59 + goto err; 60 60 + } 56 61 57 62 i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE); 58 63 } 59 64 60 65 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); 61 66 if (IS_ERR(vma)) { 67 67 + ret = PTR_ERR(vma); 62 68 i915_gem_object_put(obj); 63 63 - return false; 69 69 + goto err; 64 70 } 65 71 66 72 buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC); 67 73 if (IS_ERR(buf)) { 74 74 + ret = PTR_ERR(buf); 68 75 i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP); 69 69 - return false; 76 76 + goto err; 70 77 } 71 78 72 79 dsb_buf->vma = vma; 73 80 dsb_buf->cmd_buf = buf; 74 81 dsb_buf->buf_size = size; 75 82 76 76 - return true; 83 83 + return dsb_buf; 84 84 + 85 85 + err: 86 86 + kfree(dsb_buf); 87 87 + 88 88 + return ERR_PTR(ret); 77 89 } 78 90 79 91 void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf) 80 92 { 81 93 i915_vma_unpin_and_release(&dsb_buf->vma, I915_VMA_RELEASE_MAP); 94 94 + kfree(dsb_buf); 82 95 } 83 96 84 97 void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)

+3 -10

drivers/gpu/drm/i915/display/intel_dsb_buffer.h

reviewed

··· 8 8 9 9 #include <linux/types.h> 10 10 11 11 - struct intel_crtc; 12 12 - struct i915_vma; 13 13 - 14 14 - struct intel_dsb_buffer { 15 15 - u32 *cmd_buf; 16 16 - struct i915_vma *vma; 17 17 - size_t buf_size; 18 18 - }; 11 11 + struct drm_device; 12 12 + struct intel_dsb_buffer; 19 13 20 14 u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf); 21 15 void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val); 22 16 u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx); 23 17 void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size); 24 24 - bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, 25 25 - size_t size); 18 18 + struct intel_dsb_buffer *intel_dsb_buffer_create(struct drm_device *drm, size_t size); 26 19 void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf); 27 20 void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf); 28 21

+4 -3

drivers/gpu/drm/i915/display/intel_dsi.h

reviewed

··· 29 29 30 30 #include "intel_display_types.h" 31 31 32 32 + struct intel_dsi_host; 33 33 + struct ref_tracker; 34 34 + 32 35 #define INTEL_DSI_VIDEO_MODE 0 33 36 #define INTEL_DSI_COMMAND_MODE 1 34 37 ··· 40 37 #define DSI_DUAL_LINK_FRONT_BACK 1 41 38 #define DSI_DUAL_LINK_PIXEL_ALT 2 42 39 43 43 - struct intel_dsi_host; 44 44 - 45 40 struct intel_dsi { 46 41 struct intel_encoder base; 47 42 48 43 struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS]; 49 49 - intel_wakeref_t io_wakeref[I915_MAX_PORTS]; 44 44 + struct ref_tracker *io_wakeref[I915_MAX_PORTS]; 50 45 51 46 /* GPIO Desc for panel and backlight control */ 52 47 struct gpio_desc *gpio_panel;

+3 -3

drivers/gpu/drm/i915/display/intel_fb.c

reviewed

··· 20 20 #include "intel_fb.h" 21 21 #include "intel_fb_bo.h" 22 22 #include "intel_frontbuffer.h" 23 23 - #include "intel_panic.h" 23 23 + #include "intel_parent.h" 24 24 #include "intel_plane.h" 25 25 26 26 #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a)) ··· 558 558 * where supported. 559 559 */ 560 560 if (intel_fb_is_ccs_modifier(md->modifier) && 561 561 - HAS_AUX_CCS(display) != !!md->ccs.packed_aux_planes) 561 561 + intel_parent_has_auxccs(display) != !!md->ccs.packed_aux_planes) 562 562 return false; 563 563 564 564 if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS && ··· 2216 2216 int ret; 2217 2217 int i; 2218 2218 2219 2219 - intel_fb->panic = intel_panic_alloc(); 2219 2219 + intel_fb->panic = intel_parent_panic_alloc(display); 2220 2220 if (!intel_fb->panic) 2221 2221 return -ENOMEM; 2222 2222

+203 -63

drivers/gpu/drm/i915/display/intel_fbc.c

reviewed

··· 45 45 #include <drm/drm_fourcc.h> 46 46 #include <drm/drm_print.h> 47 47 48 48 - #include "gem/i915_gem_stolen.h" 49 49 - 50 50 - #include "gt/intel_gt_types.h" 51 51 - 52 52 - #include "i915_drv.h" 53 53 - #include "i915_vgpu.h" 54 48 #include "i915_vma.h" 55 49 #include "i9xx_plane_regs.h" 56 50 #include "intel_de.h" ··· 58 64 #include "intel_fbc.h" 59 65 #include "intel_fbc_regs.h" 60 66 #include "intel_frontbuffer.h" 67 67 + #include "intel_parent.h" 68 68 + #include "intel_step.h" 61 69 62 70 #define for_each_fbc_id(__display, __fbc_id) \ 63 71 for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \ ··· 67 71 68 72 #define for_each_intel_fbc(__display, __fbc, __fbc_id) \ 69 73 for_each_fbc_id((__display), (__fbc_id)) \ 70 70 - for_each_if((__fbc) = (__display)->fbc[(__fbc_id)]) 74 74 + for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)]) 75 75 + 76 76 + #define FBC_SYS_CACHE_ID_NONE I915_MAX_FBCS 71 77 72 78 struct intel_fbc_funcs { 73 79 void (*activate)(struct intel_fbc *fbc); ··· 126 128 struct intel_fbc_state state; 127 129 const char *no_fbc_reason; 128 130 }; 131 131 + 132 132 + static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe) 133 133 + { 134 134 + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 135 135 + struct intel_plane *primary = NULL; 136 136 + 137 137 + primary = to_intel_plane(crtc->base.primary); 138 138 + 139 139 + if (drm_WARN_ON(display->drm, !primary)) 140 140 + return NULL; 141 141 + 142 142 + return primary->fbc; 143 143 + } 129 144 130 145 /* plane stride in pixels */ 131 146 static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state) ··· 215 204 216 205 static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state) 217 206 { 218 218 - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 207 207 + struct intel_display *display = to_intel_display(plane_state); 219 208 unsigned int stride = intel_fbc_plane_cfb_stride(plane_state); 220 209 unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16; 221 210 unsigned int cpp = intel_fbc_cfb_cpp(plane_state); ··· 246 235 247 236 static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state) 248 237 { 249 249 - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 238 238 + struct intel_display *display = to_intel_display(plane_state); 250 239 unsigned int height = drm_rect_height(&plane_state->uapi.src) >> 16; 251 240 252 241 return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state)); ··· 254 243 255 244 static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state) 256 245 { 257 257 - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 246 246 + struct intel_display *display = to_intel_display(plane_state); 258 247 unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state); 259 248 unsigned int stride = intel_fbc_plane_cfb_stride(plane_state); 260 249 const struct drm_framebuffer *fb = plane_state->hw.fb; ··· 278 267 279 268 static bool intel_fbc_has_fences(struct intel_display *display) 280 269 { 281 281 - struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm); 282 282 - 283 283 - return intel_gt_support_legacy_fencing(to_gt(i915)); 270 270 + return intel_parent_has_fenced_regions(display); 284 271 } 285 272 286 273 static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) ··· 391 382 struct intel_display *display = fbc->display; 392 383 393 384 drm_WARN_ON(display->drm, 394 394 - range_end_overflows_t(u64, i915_gem_stolen_area_address(display->drm), 395 395 - i915_gem_stolen_node_offset(fbc->compressed_fb), 385 385 + range_end_overflows_t(u64, intel_parent_stolen_area_address(display), 386 386 + intel_parent_stolen_node_offset(display, fbc->compressed_fb), 396 387 U32_MAX)); 397 388 drm_WARN_ON(display->drm, 398 398 - range_end_overflows_t(u64, i915_gem_stolen_area_address(display->drm), 399 399 - i915_gem_stolen_node_offset(fbc->compressed_llb), 389 389 + range_end_overflows_t(u64, intel_parent_stolen_area_address(display), 390 390 + intel_parent_stolen_node_offset(display, fbc->compressed_llb), 400 391 U32_MAX)); 401 392 intel_de_write(display, FBC_CFB_BASE, 402 402 - i915_gem_stolen_node_address(fbc->compressed_fb)); 393 393 + intel_parent_stolen_node_address(display, fbc->compressed_fb)); 403 394 intel_de_write(display, FBC_LL_BASE, 404 404 - i915_gem_stolen_node_address(fbc->compressed_llb)); 395 395 + intel_parent_stolen_node_address(display, fbc->compressed_llb)); 405 396 } 406 397 407 398 static const struct intel_fbc_funcs i8xx_fbc_funcs = { ··· 509 500 struct intel_display *display = fbc->display; 510 501 511 502 intel_de_write(display, DPFC_CB_BASE, 512 512 - i915_gem_stolen_node_offset(fbc->compressed_fb)); 503 503 + intel_parent_stolen_node_offset(display, fbc->compressed_fb)); 513 504 } 514 505 515 506 static const struct intel_fbc_funcs g4x_fbc_funcs = { ··· 578 569 struct intel_display *display = fbc->display; 579 570 580 571 intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id), 581 581 - i915_gem_stolen_node_offset(fbc->compressed_fb)); 572 572 + intel_parent_stolen_node_offset(display, fbc->compressed_fb)); 582 573 } 583 574 584 575 static const struct intel_fbc_funcs ilk_fbc_funcs = { ··· 817 808 * underruns, even if that range is not reserved by the BIOS. */ 818 809 if (display->platform.broadwell || 819 810 (DISPLAY_VER(display) == 9 && !display->platform.broxton)) 820 820 - end = i915_gem_stolen_area_size(display->drm) - 8 * 1024 * 1024; 811 811 + end = intel_parent_stolen_area_size(display) - 8 * 1024 * 1024; 821 812 else 822 813 end = U64_MAX; 823 814 ··· 852 843 size /= limit; 853 844 854 845 /* Try to over-allocate to reduce reallocations and fragmentation. */ 855 855 - ret = i915_gem_stolen_insert_node_in_range(fbc->compressed_fb, 856 856 - size <<= 1, 4096, 0, end); 846 846 + ret = intel_parent_stolen_insert_node_in_range(display, fbc->compressed_fb, 847 847 + size <<= 1, 4096, 0, end); 857 848 if (ret == 0) 858 849 return limit; 859 850 860 851 for (; limit <= intel_fbc_max_limit(display); limit <<= 1) { 861 861 - ret = i915_gem_stolen_insert_node_in_range(fbc->compressed_fb, 862 862 - size >>= 1, 4096, 0, end); 852 852 + ret = intel_parent_stolen_insert_node_in_range(display, fbc->compressed_fb, 853 853 + size >>= 1, 4096, 0, end); 863 854 if (ret == 0) 864 855 return limit; 865 856 } ··· 874 865 int ret; 875 866 876 867 drm_WARN_ON(display->drm, 877 877 - i915_gem_stolen_node_allocated(fbc->compressed_fb)); 868 868 + intel_parent_stolen_node_allocated(display, fbc->compressed_fb)); 878 869 drm_WARN_ON(display->drm, 879 879 - i915_gem_stolen_node_allocated(fbc->compressed_llb)); 870 870 + intel_parent_stolen_node_allocated(display, fbc->compressed_llb)); 880 871 881 872 if (DISPLAY_VER(display) < 5 && !display->platform.g4x) { 882 882 - ret = i915_gem_stolen_insert_node(fbc->compressed_llb, 4096, 4096); 873 873 + ret = intel_parent_stolen_insert_node(display, fbc->compressed_llb, 4096, 4096); 883 874 if (ret) 884 875 goto err; 885 876 } ··· 895 886 896 887 drm_dbg_kms(display->drm, 897 888 "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n", 898 898 - i915_gem_stolen_node_size(fbc->compressed_fb), fbc->limit); 889 889 + intel_parent_stolen_node_size(display, fbc->compressed_fb), fbc->limit); 899 890 return 0; 900 891 901 892 err_llb: 902 902 - if (i915_gem_stolen_node_allocated(fbc->compressed_llb)) 903 903 - i915_gem_stolen_remove_node(fbc->compressed_llb); 893 893 + if (intel_parent_stolen_node_allocated(display, fbc->compressed_llb)) 894 894 + intel_parent_stolen_remove_node(display, fbc->compressed_llb); 904 895 err: 905 905 - if (i915_gem_stolen_initialized(display->drm)) 896 896 + if (intel_parent_stolen_initialized(display)) 906 897 drm_info_once(display->drm, 907 898 "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); 908 899 return -ENOSPC; ··· 954 945 fbc_compressor_clkgate_disable_wa(fbc, true); 955 946 } 956 947 948 948 + static void fbc_sys_cache_update_config(struct intel_display *display, u32 reg, 949 949 + enum intel_fbc_id id) 950 950 + { 951 951 + if (!HAS_FBC_SYS_CACHE(display)) 952 952 + return; 953 953 + 954 954 + lockdep_assert_held(&display->fbc.sys_cache.lock); 955 955 + 956 956 + /* 957 957 + * Wa_14025769978: 958 958 + * Fixes: SoC hardware issue in read caching 959 959 + * Workaround: disable cache read setting which is enabled by default. 960 960 + */ 961 961 + if (!intel_display_wa(display, 14025769978)) 962 962 + /* Cache read enable is set by default */ 963 963 + reg |= FBC_SYS_CACHE_READ_ENABLE; 964 964 + 965 965 + intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg); 966 966 + 967 967 + display->fbc.sys_cache.id = id; 968 968 + } 969 969 + 970 970 + static void fbc_sys_cache_disable(const struct intel_fbc *fbc) 971 971 + { 972 972 + struct intel_display *display = fbc->display; 973 973 + struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache; 974 974 + 975 975 + mutex_lock(&sys_cache->lock); 976 976 + /* clear only if "fbc" reserved the cache */ 977 977 + if (sys_cache->id == fbc->id) 978 978 + fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE); 979 979 + mutex_unlock(&sys_cache->lock); 980 980 + } 981 981 + 982 982 + static int fbc_sys_cache_limit(struct intel_display *display) 983 983 + { 984 984 + if (DISPLAY_VER(display) == 35) 985 985 + return 2 * 1024 * 1024; 986 986 + 987 987 + return 0; 988 988 + } 989 989 + 990 990 + static void fbc_sys_cache_enable(const struct intel_fbc *fbc) 991 991 + { 992 992 + struct intel_display *display = fbc->display; 993 993 + struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache; 994 994 + int range, offset; 995 995 + u32 cfg; 996 996 + 997 997 + if (!HAS_FBC_SYS_CACHE(display)) 998 998 + return; 999 999 + 1000 1000 + range = fbc_sys_cache_limit(display) / (64 * 1024); 1001 1001 + 1002 1002 + offset = intel_parent_stolen_node_offset(display, fbc->compressed_fb) / (4 * 1024); 1003 1003 + 1004 1004 + cfg = FBC_SYS_CACHE_TAG_USE_RES_SPACE | FBC_SYS_CACHEABLE_RANGE(range) | 1005 1005 + FBC_SYS_CACHE_START_BASE(offset); 1006 1006 + 1007 1007 + mutex_lock(&sys_cache->lock); 1008 1008 + /* update sys cache config only if sys cache is unassigned */ 1009 1009 + if (sys_cache->id == FBC_SYS_CACHE_ID_NONE) 1010 1010 + fbc_sys_cache_update_config(display, cfg, fbc->id); 1011 1011 + mutex_unlock(&sys_cache->lock); 1012 1012 + } 1013 1013 + 957 1014 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc) 958 1015 { 1016 1016 + struct intel_display *display = fbc->display; 1017 1017 + 959 1018 if (WARN_ON(intel_fbc_hw_is_active(fbc))) 960 1019 return; 961 1020 962 962 - if (i915_gem_stolen_node_allocated(fbc->compressed_llb)) 963 963 - i915_gem_stolen_remove_node(fbc->compressed_llb); 964 964 - if (i915_gem_stolen_node_allocated(fbc->compressed_fb)) 965 965 - i915_gem_stolen_remove_node(fbc->compressed_fb); 1021 1021 + if (intel_parent_stolen_node_allocated(display, fbc->compressed_llb)) 1022 1022 + intel_parent_stolen_remove_node(display, fbc->compressed_llb); 1023 1023 + if (intel_parent_stolen_node_allocated(display, fbc->compressed_fb)) 1024 1024 + intel_parent_stolen_remove_node(display, fbc->compressed_fb); 966 1025 } 967 1026 968 1027 void intel_fbc_cleanup(struct intel_display *display) ··· 1043 966 __intel_fbc_cleanup_cfb(fbc); 1044 967 mutex_unlock(&fbc->lock); 1045 968 1046 1046 - i915_gem_stolen_node_free(fbc->compressed_fb); 1047 1047 - i915_gem_stolen_node_free(fbc->compressed_llb); 969 969 + intel_parent_stolen_node_free(display, fbc->compressed_fb); 970 970 + intel_parent_stolen_node_free(display, fbc->compressed_llb); 1048 971 1049 972 kfree(fbc); 1050 973 } 974 974 + 975 975 + mutex_lock(&display->fbc.sys_cache.lock); 976 976 + drm_WARN_ON(display->drm, 977 977 + display->fbc.sys_cache.id != FBC_SYS_CACHE_ID_NONE); 978 978 + mutex_unlock(&display->fbc.sys_cache.lock); 1051 979 } 1052 980 1053 981 static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state) ··· 1098 1016 1099 1017 static bool stride_is_valid(const struct intel_plane_state *plane_state) 1100 1018 { 1101 1101 - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1019 1019 + struct intel_display *display = to_intel_display(plane_state); 1102 1020 1103 1021 if (DISPLAY_VER(display) >= 11) 1104 1022 return icl_fbc_stride_is_valid(plane_state); ··· 1114 1032 1115 1033 static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) 1116 1034 { 1117 1117 - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1035 1035 + struct intel_display *display = to_intel_display(plane_state); 1118 1036 const struct drm_framebuffer *fb = plane_state->hw.fb; 1119 1037 1120 1038 switch (fb->format->format) { ··· 1134 1052 1135 1053 static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) 1136 1054 { 1137 1137 - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1055 1055 + struct intel_display *display = to_intel_display(plane_state); 1138 1056 const struct drm_framebuffer *fb = plane_state->hw.fb; 1139 1057 1140 1058 switch (fb->format->format) { ··· 1213 1131 1214 1132 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) 1215 1133 { 1216 1216 - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1134 1134 + struct intel_display *display = to_intel_display(plane_state); 1217 1135 1218 1136 if (DISPLAY_VER(display) >= 35) 1219 1137 return xe3p_lpd_fbc_pixel_format_is_valid(plane_state); ··· 1249 1167 1250 1168 static bool rotation_is_valid(const struct intel_plane_state *plane_state) 1251 1169 { 1252 1252 - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1170 1170 + struct intel_display *display = to_intel_display(plane_state); 1253 1171 1254 1172 if (DISPLAY_VER(display) >= 9) 1255 1173 return skl_fbc_rotation_is_valid(plane_state); ··· 1288 1206 */ 1289 1207 static bool intel_fbc_surface_size_ok(const struct intel_plane_state *plane_state) 1290 1208 { 1291 1291 - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1209 1209 + struct intel_display *display = to_intel_display(plane_state); 1292 1210 unsigned int effective_w, effective_h, max_w, max_h; 1293 1211 1294 1212 intel_fbc_max_surface_size(display, &max_w, &max_h); ··· 1321 1239 1322 1240 static bool intel_fbc_plane_size_valid(const struct intel_plane_state *plane_state) 1323 1241 { 1324 1324 - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1242 1242 + struct intel_display *display = to_intel_display(plane_state); 1325 1243 unsigned int w, h, max_w, max_h; 1326 1244 1327 1245 intel_fbc_max_plane_size(display, &max_w, &max_h); ··· 1346 1264 1347 1265 static bool tiling_is_valid(const struct intel_plane_state *plane_state) 1348 1266 { 1349 1349 - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1267 1267 + struct intel_display *display = to_intel_display(plane_state); 1350 1268 1351 1269 if (DISPLAY_VER(display) >= 9) 1352 1270 return skl_fbc_tiling_valid(plane_state); ··· 1426 1344 struct intel_crtc *crtc, 1427 1345 struct intel_plane *plane) 1428 1346 { 1429 1429 - struct intel_display *display = to_intel_display(state->base.dev); 1347 1347 + struct intel_display *display = to_intel_display(state); 1430 1348 const struct intel_crtc_state *crtc_state = 1431 1349 intel_atomic_get_new_crtc_state(state, crtc); 1432 1350 const struct intel_plane_state *plane_state = ··· 1459 1377 1460 1378 static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state) 1461 1379 { 1462 1462 - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); 1380 1380 + struct intel_display *display = to_intel_display(plane_state); 1463 1381 1464 1382 /* 1465 1383 * The use of a CPU fence is one of two ways to detect writes by the ··· 1480 1398 1481 1399 static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state) 1482 1400 { 1401 1401 + struct intel_display *display = to_intel_display(plane_state); 1483 1402 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1484 1403 struct intel_fbc *fbc = plane->fbc; 1485 1404 1486 1405 return intel_fbc_min_limit(plane_state) <= fbc->limit && 1487 1406 intel_fbc_cfb_size(plane_state) <= fbc->limit * 1488 1488 - i915_gem_stolen_node_size(fbc->compressed_fb); 1407 1407 + intel_parent_stolen_node_size(display, fbc->compressed_fb); 1489 1408 } 1490 1409 1491 1410 static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state) ··· 1567 1484 static int intel_fbc_check_plane(struct intel_atomic_state *state, 1568 1485 struct intel_plane *plane) 1569 1486 { 1570 1570 - struct intel_display *display = to_intel_display(state->base.dev); 1571 1571 - struct drm_i915_private *i915 = to_i915(display->drm); 1487 1487 + struct intel_display *display = to_intel_display(state); 1572 1488 struct intel_plane_state *plane_state = 1573 1489 intel_atomic_get_new_plane_state(state, plane); 1574 1490 const struct drm_framebuffer *fb = plane_state->hw.fb; ··· 1578 1496 if (!fbc) 1579 1497 return 0; 1580 1498 1581 1581 - if (!i915_gem_stolen_initialized(display->drm)) { 1499 1499 + if (!intel_parent_stolen_initialized(display)) { 1582 1500 plane_state->no_fbc_reason = "stolen memory not initialised"; 1583 1501 return 0; 1584 1502 } 1585 1503 1586 1586 - if (intel_vgpu_active(i915)) { 1504 1504 + if (intel_parent_vgpu_active(display)) { 1587 1505 plane_state->no_fbc_reason = "VGPU active"; 1588 1506 return 0; 1589 1507 } ··· 1600 1518 1601 1519 if (intel_display_wa(display, 16023588340)) { 1602 1520 plane_state->no_fbc_reason = "Wa_16023588340"; 1521 1521 + return 0; 1522 1522 + } 1523 1523 + 1524 1524 + /* 1525 1525 + * Wa_15018326506: 1526 1526 + * Fixes: Underrun during media decode 1527 1527 + * Workaround: Do not enable FBC 1528 1528 + */ 1529 1529 + if (intel_display_wa(display, 15018326506)) { 1530 1530 + plane_state->no_fbc_reason = "Wa_15018326506"; 1603 1531 return 0; 1604 1532 } 1605 1533 ··· 1794 1702 struct intel_crtc *crtc, 1795 1703 struct intel_plane *plane) 1796 1704 { 1797 1797 - struct intel_display *display = to_intel_display(state->base.dev); 1705 1705 + struct intel_display *display = to_intel_display(state); 1798 1706 struct intel_fbc *fbc = plane->fbc; 1799 1707 bool need_vblank_wait = false; 1800 1708 ··· 1866 1774 intel_fbc_invalidate_dirty_rect(fbc); 1867 1775 1868 1776 __intel_fbc_cleanup_cfb(fbc); 1777 1777 + 1778 1778 + fbc_sys_cache_disable(fbc); 1869 1779 1870 1780 /* wa_18038517565 Enable DPFC clock gating after FBC disable */ 1871 1781 if (display->platform.dg2 || DISPLAY_VER(display) >= 14) ··· 2009 1915 struct intel_crtc *crtc, 2010 1916 struct intel_plane *plane) 2011 1917 { 2012 2012 - struct intel_display *display = to_intel_display(state->base.dev); 1918 1918 + struct intel_display *display = to_intel_display(state); 2013 1919 const struct intel_plane_state *plane_state = 2014 1920 intel_atomic_get_new_plane_state(state, plane); 2015 1921 struct intel_fbc *fbc = plane->fbc; ··· 2061 1967 2062 1968 intel_fbc_program_workarounds(fbc); 2063 1969 intel_fbc_program_cfb(fbc); 1970 1970 + 1971 1971 + fbc_sys_cache_enable(fbc); 2064 1972 } 2065 1973 2066 1974 /** ··· 2073 1977 */ 2074 1978 void intel_fbc_disable(struct intel_crtc *crtc) 2075 1979 { 2076 2076 - struct intel_display *display = to_intel_display(crtc->base.dev); 1980 1980 + struct intel_display *display = to_intel_display(crtc); 2077 1981 struct intel_plane *plane; 2078 1982 2079 1983 for_each_intel_plane(display->drm, plane) { ··· 2215 2119 __intel_fbc_handle_fifo_underrun_irq(fbc); 2216 2120 } 2217 2121 2122 2122 + /** 2123 2123 + * intel_fbc_read_underrun_dbg_info - Read and log FBC-related FIFO underrun debug info 2124 2124 + * @display: display device instance 2125 2125 + * @pipe: the pipe possibly containing the FBC 2126 2126 + * @log: log the info? 2127 2127 + * 2128 2128 + * If @pipe does not contain an FBC instance, this function bails early. 2129 2129 + * Otherwise, FBC-related FIFO underrun is read and cleared, and then, if @log 2130 2130 + * is true, printed with error level. 2131 2131 + */ 2132 2132 + void intel_fbc_read_underrun_dbg_info(struct intel_display *display, 2133 2133 + enum pipe pipe, bool log) 2134 2134 + { 2135 2135 + struct intel_fbc *fbc = intel_fbc_for_pipe(display, pipe); 2136 2136 + u32 val; 2137 2137 + 2138 2138 + if (!fbc) 2139 2139 + return; 2140 2140 + 2141 2141 + val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id)); 2142 2142 + if (!(val & FBC_UNDERRUN_DECMPR)) 2143 2143 + return; 2144 2144 + 2145 2145 + intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR); 2146 2146 + 2147 2147 + if (log) 2148 2148 + drm_err(display->drm, 2149 2149 + "Pipe %c FIFO underrun info: FBC decompressing\n", 2150 2150 + pipe_name(pipe)); 2151 2151 + } 2152 2152 + 2218 2153 /* 2219 2154 * The DDX driver changes its behavior depending on the value it reads from 2220 2155 * i915.enable_fbc, so sanitize it by translating the default value into either ··· 2283 2156 if (!fbc) 2284 2157 return NULL; 2285 2158 2286 2286 - fbc->compressed_fb = i915_gem_stolen_node_alloc(display->drm); 2159 2159 + fbc->compressed_fb = intel_parent_stolen_node_alloc(display); 2287 2160 if (!fbc->compressed_fb) 2288 2161 goto err; 2289 2289 - fbc->compressed_llb = i915_gem_stolen_node_alloc(display->drm); 2162 2162 + fbc->compressed_llb = intel_parent_stolen_node_alloc(display); 2290 2163 if (!fbc->compressed_llb) 2291 2164 goto err; 2292 2165 ··· 2311 2184 return fbc; 2312 2185 2313 2186 err: 2314 2314 - i915_gem_stolen_node_free(fbc->compressed_llb); 2315 2315 - i915_gem_stolen_node_free(fbc->compressed_fb); 2187 2187 + intel_parent_stolen_node_free(display, fbc->compressed_llb); 2188 2188 + intel_parent_stolen_node_free(display, fbc->compressed_fb); 2316 2189 kfree(fbc); 2317 2190 2318 2191 return NULL; ··· 2333 2206 display->params.enable_fbc); 2334 2207 2335 2208 for_each_fbc_id(display, fbc_id) 2336 2336 - display->fbc[fbc_id] = intel_fbc_create(display, fbc_id); 2209 2209 + display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id); 2210 2210 + 2211 2211 + mutex_init(&display->fbc.sys_cache.lock); 2212 2212 + display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE; 2337 2213 } 2338 2214 2339 2215 /** ··· 2356 2226 if (intel_fbc_hw_is_active(fbc)) 2357 2227 intel_fbc_hw_deactivate(fbc); 2358 2228 } 2229 2229 + 2230 2230 + /* Ensure the sys cache usage config is clear as well */ 2231 2231 + mutex_lock(&display->fbc.sys_cache.lock); 2232 2232 + fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE); 2233 2233 + mutex_unlock(&display->fbc.sys_cache.lock); 2359 2234 } 2360 2235 2361 2236 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused) ··· 2379 2244 seq_puts(m, "FBC enabled\n"); 2380 2245 seq_printf(m, "Compressing: %s\n", 2381 2246 str_yes_no(intel_fbc_is_compressing(fbc))); 2247 2247 + 2248 2248 + mutex_lock(&display->fbc.sys_cache.lock); 2249 2249 + seq_printf(m, "Using system cache: %s\n", 2250 2250 + str_yes_no(display->fbc.sys_cache.id == fbc->id)); 2251 2251 + mutex_unlock(&display->fbc.sys_cache.lock); 2382 2252 } else { 2383 2253 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); 2384 2254 } ··· 2465 2325 { 2466 2326 struct intel_fbc *fbc; 2467 2327 2468 2468 - fbc = display->fbc[INTEL_FBC_A]; 2328 2328 + fbc = display->fbc.instances[INTEL_FBC_A]; 2469 2329 if (fbc) 2470 2330 intel_fbc_debugfs_add(fbc, display->drm->debugfs_root); 2471 2331 }

+3

drivers/gpu/drm/i915/display/intel_fbc.h

reviewed

··· 9 9 #include <linux/types.h> 10 10 11 11 enum fb_op_origin; 12 12 + enum pipe; 12 13 struct intel_atomic_state; 13 14 struct intel_crtc; 14 15 struct intel_crtc_state; ··· 47 46 unsigned int frontbuffer_bits, enum fb_op_origin origin); 48 47 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane); 49 48 void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display); 49 49 + void intel_fbc_read_underrun_dbg_info(struct intel_display *display, 50 50 + enum pipe, bool log); 50 51 void intel_fbc_reset_underrun(struct intel_display *display); 51 52 void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc); 52 53 void intel_fbc_debugfs_register(struct intel_display *display);

+12

drivers/gpu/drm/i915/display/intel_fbc_regs.h

reviewed

··· 88 88 #define DPFC_FENCE_YOFF _MMIO(0x3218) 89 89 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) 90 90 #define DPFC_CHICKEN _MMIO(0x3224) 91 91 + #define FBC_DEBUG_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43220, 0x43260) 92 92 + #define FBC_UNDERRUN_DECMPR REG_BIT(27) 91 93 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) 92 94 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ 93 95 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ ··· 127 125 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) 128 126 #define FBC_REND_NUKE REG_BIT(2) 129 127 #define FBC_REND_CACHE_CLEAN REG_BIT(1) 128 128 + 129 129 + #define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG _MMIO(0x1344E0) 130 130 + #define FBC_SYS_CACHE_START_BASE_MASK REG_GENMASK(31, 16) 131 131 + #define FBC_SYS_CACHE_START_BASE(base) REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base)) 132 132 + #define FBC_SYS_CACHEABLE_RANGE_MASK REG_GENMASK(15, 4) 133 133 + #define FBC_SYS_CACHEABLE_RANGE(range) REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range)) 134 134 + #define FBC_SYS_CACHE_TAG_MASK REG_GENMASK(3, 2) 135 135 + #define FBC_SYS_CACHE_TAG_DONT_CACHE REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0) 136 136 + #define FBC_SYS_CACHE_TAG_USE_RES_SPACE REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3) 137 137 + #define FBC_SYS_CACHE_READ_ENABLE REG_BIT(0) 130 138 131 139 #endif /* __INTEL_FBC_REGS__ */

+109

drivers/gpu/drm/i915/display/intel_fifo_underrun.c

reviewed

··· 25 25 * 26 26 */ 27 27 28 28 + #include <linux/seq_buf.h> 29 29 + 28 30 #include <drm/drm_print.h> 29 31 30 32 #include "i915_reg.h" ··· 58 56 * 59 57 * The code also supports underrun detection on the PCH transcoder. 60 58 */ 59 59 + 60 60 + #define UNDERRUN_DBG1_NUM_PLANES 6 61 61 + 62 62 + static void log_underrun_dbg1(struct intel_display *display, enum pipe pipe, 63 63 + unsigned long plane_mask, const char *info) 64 64 + { 65 65 + DECLARE_SEQ_BUF(planes_desc, 32); 66 66 + unsigned int i; 67 67 + 68 68 + if (!plane_mask) 69 69 + return; 70 70 + 71 71 + for_each_set_bit(i, &plane_mask, UNDERRUN_DBG1_NUM_PLANES) { 72 72 + if (i == 0) 73 73 + seq_buf_puts(&planes_desc, "[C]"); 74 74 + else 75 75 + seq_buf_printf(&planes_desc, "[%d]", i); 76 76 + } 77 77 + 78 78 + drm_err(display->drm, "Pipe %c FIFO underrun info: %s on planes: %s\n", 79 79 + pipe_name(pipe), info, seq_buf_str(&planes_desc)); 80 80 + 81 81 + drm_WARN_ON(display->drm, seq_buf_has_overflowed(&planes_desc)); 82 82 + } 83 83 + 84 84 + static void read_underrun_dbg1(struct intel_display *display, enum pipe pipe, bool log) 85 85 + { 86 86 + u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe)); 87 87 + 88 88 + if (!val) 89 89 + return; 90 90 + 91 91 + intel_de_write(display, UNDERRUN_DBG1(pipe), val); 92 92 + 93 93 + if (!log) 94 94 + return; 95 95 + 96 96 + log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val), 97 97 + "DBUF block not valid"); 98 98 + log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val), 99 99 + "DDB empty"); 100 100 + log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val), 101 101 + "DBUF not completely filled"); 102 102 + log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val), 103 103 + "DBUF below WM0"); 104 104 + } 105 105 + 106 106 + static void read_underrun_dbg2(struct intel_display *display, enum pipe pipe, bool log) 107 107 + { 108 108 + u32 val = intel_de_read(display, UNDERRUN_DBG2(pipe)); 109 109 + 110 110 + if (!(val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN)) 111 111 + return; 112 112 + 113 113 + intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN); 114 114 + 115 115 + if (log) 116 116 + drm_err(display->drm, 117 117 + "Pipe %c FIFO underrun info: frame count: %u, line count: %u\n", 118 118 + pipe_name(pipe), 119 119 + REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, val), 120 120 + REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, val)); 121 121 + } 122 122 + 123 123 + static void read_underrun_dbg_pkgc(struct intel_display *display, bool log) 124 124 + { 125 125 + u32 val = intel_de_read(display, GEN12_DCPR_STATUS_1); 126 126 + 127 127 + if (!(val & XE3P_UNDERRUN_PKGC)) 128 128 + return; 129 129 + 130 130 + /* 131 131 + * Note: If there are multiple pipes enabled, only one of them will see 132 132 + * XE3P_UNDERRUN_PKGC set. 133 133 + */ 134 134 + intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC); 135 135 + 136 136 + if (log) 137 137 + drm_err(display->drm, 138 138 + "General FIFO underrun info: Package C-state blocking memory\n"); 139 139 + } 140 140 + 141 141 + static void read_underrun_dbg_info(struct intel_display *display, 142 142 + enum pipe pipe, 143 143 + bool log) 144 144 + { 145 145 + if (!HAS_UNDERRUN_DBG_INFO(display)) 146 146 + return; 147 147 + 148 148 + read_underrun_dbg1(display, pipe, log); 149 149 + read_underrun_dbg2(display, pipe, log); 150 150 + intel_fbc_read_underrun_dbg_info(display, pipe, log); 151 151 + read_underrun_dbg_pkgc(display, log); 152 152 + } 61 153 62 154 static bool ivb_can_enable_err_int(struct intel_display *display) 63 155 { ··· 358 262 old = !crtc->cpu_fifo_underrun_disabled; 359 263 crtc->cpu_fifo_underrun_disabled = !enable; 360 264 265 265 + /* 266 266 + * The debug bits get latched at the time of the FIFO underrun ISR bit 267 267 + * getting set. That means that any non-zero debug bit that is read when 268 268 + * handling a FIFO underrun interrupt has the potential to belong to 269 269 + * another underrun event (past or future). To alleviate this problem, 270 270 + * let's clear existing bits before enabling the interrupt, so that at 271 271 + * least we don't get information that is too out-of-date. 272 272 + */ 273 273 + if (enable && !old) 274 274 + read_underrun_dbg_info(display, pipe, false); 275 275 + 361 276 if (HAS_GMCH(display)) 362 277 i9xx_set_fifo_underrun_reporting(display, pipe, enable, old); 363 278 else if (display->platform.ironlake || display->platform.sandybridge) ··· 486 379 trace_intel_cpu_fifo_underrun(display, pipe); 487 380 488 381 drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); 382 382 + 383 383 + read_underrun_dbg_info(display, pipe, true); 489 384 } 490 385 491 386 intel_fbc_handle_fifo_underrun_irq(display);

+4 -6

drivers/gpu/drm/i915/display/intel_gmbus.c

reviewed

··· 35 35 #include <drm/drm_print.h> 36 36 #include <drm/display/drm_hdcp_helper.h> 37 37 38 38 - #include "i915_drv.h" 39 39 - #include "i915_irq.h" 40 38 #include "i915_reg.h" 41 39 #include "intel_de.h" 42 40 #include "intel_display_regs.h" ··· 42 44 #include "intel_display_wa.h" 43 45 #include "intel_gmbus.h" 44 46 #include "intel_gmbus_regs.h" 47 47 + #include "intel_parent.h" 45 48 46 49 struct intel_gmbus { 47 50 struct i2c_adapter adapter; ··· 390 391 391 392 static bool has_gmbus_irq(struct intel_display *display) 392 393 { 393 393 - struct drm_i915_private *i915 = to_i915(display->drm); 394 394 /* 395 395 * encoder->shutdown() may want to use GMBUS 396 396 * after irqs have already been disabled. 397 397 */ 398 398 - return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(i915); 398 398 + return HAS_GMBUS_IRQ(display) && intel_parent_irq_enabled(display); 399 399 } 400 400 401 401 static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en) ··· 789 791 { 790 792 struct intel_gmbus *bus = to_intel_gmbus(adapter); 791 793 struct intel_display *display = bus->display; 792 792 - intel_wakeref_t wakeref; 794 794 + struct ref_tracker *wakeref; 793 795 int ret; 794 796 795 797 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); ··· 829 831 .buf = buf, 830 832 } 831 833 }; 832 832 - intel_wakeref_t wakeref; 834 834 + struct ref_tracker *wakeref; 833 835 int ret; 834 836 835 837 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS);

+2 -2

drivers/gpu/drm/i915/display/intel_hdcp.c

reviewed

··· 29 29 #include "intel_display_types.h" 30 30 #include "intel_dp_mst.h" 31 31 #include "intel_hdcp.h" 32 32 - #include "intel_hdcp_gsc.h" 33 32 #include "intel_hdcp_gsc_message.h" 34 33 #include "intel_hdcp_regs.h" 35 34 #include "intel_hdcp_shim.h" 35 35 + #include "intel_parent.h" 36 36 #include "intel_pcode.h" 37 37 #include "intel_step.h" 38 38 ··· 258 258 259 259 /* If MTL+ make sure gsc is loaded and proxy is setup */ 260 260 if (USE_HDCP_GSC(display)) { 261 261 - if (!intel_hdcp_gsc_check_status(display->drm)) 261 261 + if (!intel_parent_hdcp_gsc_check_status(display)) 262 262 return false; 263 263 } 264 264

+15 -7

drivers/gpu/drm/i915/display/intel_hdcp_gsc.c drivers/gpu/drm/i915/i915_hdcp_gsc.c

reviewed

··· 4 4 */ 5 5 6 6 #include <drm/drm_print.h> 7 7 + #include <drm/intel/display_parent_interface.h> 7 8 #include <drm/intel/i915_hdcp_interface.h> 8 9 9 10 #include "gem/i915_gem_region.h" 10 11 #include "gt/intel_gt.h" 11 12 #include "gt/uc/intel_gsc_uc_heci_cmd_submit.h" 12 13 #include "i915_drv.h" 13 13 - #include "intel_hdcp_gsc.h" 14 14 + #include "i915_hdcp_gsc.h" 14 15 15 16 struct intel_hdcp_gsc_context { 16 17 struct drm_i915_private *i915; ··· 20 19 void *hdcp_cmd_out; 21 20 }; 22 21 23 23 - bool intel_hdcp_gsc_check_status(struct drm_device *drm) 22 22 + static bool intel_hdcp_gsc_check_status(struct drm_device *drm) 24 23 { 25 24 struct drm_i915_private *i915 = to_i915(drm); 26 25 struct intel_gt *gt = i915->media_gt; ··· 88 87 return err; 89 88 } 90 89 91 91 - struct intel_hdcp_gsc_context *intel_hdcp_gsc_context_alloc(struct drm_device *drm) 90 90 + static struct intel_hdcp_gsc_context *intel_hdcp_gsc_context_alloc(struct drm_device *drm) 92 91 { 93 92 struct drm_i915_private *i915 = to_i915(drm); 94 93 struct intel_hdcp_gsc_context *gsc_context; ··· 112 111 return gsc_context; 113 112 } 114 113 115 115 - void intel_hdcp_gsc_context_free(struct intel_hdcp_gsc_context *gsc_context) 114 114 + static void intel_hdcp_gsc_context_free(struct intel_hdcp_gsc_context *gsc_context) 116 115 { 117 116 if (!gsc_context) 118 117 return; ··· 169 168 * gsc cs memory header as stated in specs after which the normal HDCP payload 170 169 * will follow 171 170 */ 172 172 - ssize_t intel_hdcp_gsc_msg_send(struct intel_hdcp_gsc_context *gsc_context, 173 173 - void *msg_in, size_t msg_in_len, 174 174 - void *msg_out, size_t msg_out_len) 171 171 + static ssize_t intel_hdcp_gsc_msg_send(struct intel_hdcp_gsc_context *gsc_context, 172 172 + void *msg_in, size_t msg_in_len, 173 173 + void *msg_out, size_t msg_out_len) 175 174 { 176 175 struct drm_i915_private *i915 = gsc_context->i915; 177 176 struct intel_gt *gt = i915->media_gt; ··· 238 237 err: 239 238 return ret; 240 239 } 240 240 + 241 241 + const struct intel_display_hdcp_interface i915_display_hdcp_interface = { 242 242 + .gsc_msg_send = intel_hdcp_gsc_msg_send, 243 243 + .gsc_check_status = intel_hdcp_gsc_check_status, 244 244 + .gsc_context_alloc = intel_hdcp_gsc_context_alloc, 245 245 + .gsc_context_free = intel_hdcp_gsc_context_free, 246 246 + };

-22

drivers/gpu/drm/i915/display/intel_hdcp_gsc.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2023 Intel Corporation 4 4 - */ 5 5 - 6 6 - #ifndef __INTEL_HDCP_GSC_H__ 7 7 - #define __INTEL_HDCP_GSC_H__ 8 8 - 9 9 - #include <linux/types.h> 10 10 - 11 11 - struct drm_device; 12 12 - struct intel_hdcp_gsc_context; 13 13 - 14 14 - ssize_t intel_hdcp_gsc_msg_send(struct intel_hdcp_gsc_context *gsc_context, 15 15 - void *msg_in, size_t msg_in_len, 16 16 - void *msg_out, size_t msg_out_len); 17 17 - bool intel_hdcp_gsc_check_status(struct drm_device *drm); 18 18 - 19 19 - struct intel_hdcp_gsc_context *intel_hdcp_gsc_context_alloc(struct drm_device *drm); 20 20 - void intel_hdcp_gsc_context_free(struct intel_hdcp_gsc_context *gsc_context); 21 21 - 22 22 - #endif /* __INTEL_HDCP_GCS_H__ */

+36 -42

drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c

reviewed

··· 10 10 11 11 #include "intel_display_core.h" 12 12 #include "intel_display_types.h" 13 13 - #include "intel_hdcp_gsc.h" 14 13 #include "intel_hdcp_gsc_message.h" 14 14 + #include "intel_parent.h" 15 15 16 16 static int 17 17 intel_hdcp_gsc_initiate_session(struct device *dev, struct hdcp_port_data *data, ··· 44 44 session_init_in.port.attached_transcoder = (u8)data->hdcp_transcoder; 45 45 session_init_in.protocol = data->protocol; 46 46 47 47 - byte = intel_hdcp_gsc_msg_send(gsc_context, &session_init_in, 48 48 - sizeof(session_init_in), 49 49 - &session_init_out, 50 50 - sizeof(session_init_out)); 47 47 + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, 48 48 + &session_init_in, sizeof(session_init_in), 49 49 + &session_init_out, sizeof(session_init_out)); 51 50 if (byte < 0) { 52 51 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); 53 52 return byte; ··· 105 106 memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, HDCP_2_2_RRX_LEN); 106 107 memcpy(verify_rxcert_in.rx_caps, rx_cert->rx_caps, HDCP_2_2_RXCAPS_LEN); 107 108 108 108 - byte = intel_hdcp_gsc_msg_send(gsc_context, &verify_rxcert_in, 109 109 - sizeof(verify_rxcert_in), 110 110 - &verify_rxcert_out, 111 111 - sizeof(verify_rxcert_out)); 109 109 + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, 110 110 + &verify_rxcert_in, sizeof(verify_rxcert_in), 111 111 + &verify_rxcert_out, sizeof(verify_rxcert_out)); 112 112 if (byte < 0) { 113 113 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed: %zd\n", byte); 114 114 return byte; ··· 167 169 memcpy(send_hprime_in.h_prime, rx_hprime->h_prime, 168 170 HDCP_2_2_H_PRIME_LEN); 169 171 170 170 - byte = intel_hdcp_gsc_msg_send(gsc_context, &send_hprime_in, 171 171 - sizeof(send_hprime_in), 172 172 - &send_hprime_out, 173 173 - sizeof(send_hprime_out)); 172 172 + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, 173 173 + &send_hprime_in, sizeof(send_hprime_in), 174 174 + &send_hprime_out, sizeof(send_hprime_out)); 174 175 if (byte < 0) { 175 176 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); 176 177 return byte; ··· 217 220 memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km, 218 221 HDCP_2_2_E_KH_KM_LEN); 219 222 220 220 - byte = intel_hdcp_gsc_msg_send(gsc_context, &pairing_info_in, 221 221 - sizeof(pairing_info_in), 222 222 - &pairing_info_out, 223 223 - sizeof(pairing_info_out)); 223 223 + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, 224 224 + &pairing_info_in, sizeof(pairing_info_in), 225 225 + &pairing_info_out, sizeof(pairing_info_out)); 224 226 if (byte < 0) { 225 227 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); 226 228 return byte; ··· 265 269 lc_init_in.port.physical_port = (u8)data->hdcp_ddi; 266 270 lc_init_in.port.attached_transcoder = (u8)data->hdcp_transcoder; 267 271 268 268 - byte = intel_hdcp_gsc_msg_send(gsc_context, &lc_init_in, sizeof(lc_init_in), 269 269 - &lc_init_out, sizeof(lc_init_out)); 272 272 + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, 273 273 + &lc_init_in, sizeof(lc_init_in), 274 274 + &lc_init_out, sizeof(lc_init_out)); 270 275 if (byte < 0) { 271 276 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); 272 277 return byte; ··· 318 321 memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime, 319 322 HDCP_2_2_L_PRIME_LEN); 320 323 321 321 - byte = intel_hdcp_gsc_msg_send(gsc_context, &verify_lprime_in, 322 322 - sizeof(verify_lprime_in), 323 323 - &verify_lprime_out, 324 324 - sizeof(verify_lprime_out)); 324 324 + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, 325 325 + &verify_lprime_in, sizeof(verify_lprime_in), 326 326 + &verify_lprime_out, sizeof(verify_lprime_out)); 325 327 if (byte < 0) { 326 328 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); 327 329 return byte; ··· 366 370 get_skey_in.port.physical_port = (u8)data->hdcp_ddi; 367 371 get_skey_in.port.attached_transcoder = (u8)data->hdcp_transcoder; 368 372 369 369 - byte = intel_hdcp_gsc_msg_send(gsc_context, &get_skey_in, sizeof(get_skey_in), 370 370 - &get_skey_out, sizeof(get_skey_out)); 373 373 + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, 374 374 + &get_skey_in, sizeof(get_skey_in), 375 375 + &get_skey_out, sizeof(get_skey_out)); 371 376 if (byte < 0) { 372 377 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); 373 378 return byte; ··· 431 434 memcpy(verify_repeater_in.receiver_ids, rep_topology->receiver_ids, 432 435 HDCP_2_2_RECEIVER_IDS_MAX_LEN); 433 436 434 434 - byte = intel_hdcp_gsc_msg_send(gsc_context, &verify_repeater_in, 435 435 - sizeof(verify_repeater_in), 436 436 - &verify_repeater_out, 437 437 - sizeof(verify_repeater_out)); 437 437 + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, 438 438 + &verify_repeater_in, sizeof(verify_repeater_in), 439 439 + &verify_repeater_out, sizeof(verify_repeater_out)); 438 440 if (byte < 0) { 439 441 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); 440 442 return byte; ··· 500 504 501 505 verify_mprime_in->k = cpu_to_be16(data->k); 502 506 503 503 - byte = intel_hdcp_gsc_msg_send(gsc_context, verify_mprime_in, cmd_size, 504 504 - &verify_mprime_out, 505 505 - sizeof(verify_mprime_out)); 507 507 + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, 508 508 + verify_mprime_in, cmd_size, 509 509 + &verify_mprime_out, sizeof(verify_mprime_out)); 506 510 kfree(verify_mprime_in); 507 511 if (byte < 0) { 508 512 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); ··· 548 552 enable_auth_in.port.attached_transcoder = (u8)data->hdcp_transcoder; 549 553 enable_auth_in.stream_type = data->streams[0].stream_type; 550 554 551 551 - byte = intel_hdcp_gsc_msg_send(gsc_context, &enable_auth_in, 552 552 - sizeof(enable_auth_in), 553 553 - &enable_auth_out, 554 554 - sizeof(enable_auth_out)); 555 555 + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, 556 556 + &enable_auth_in, sizeof(enable_auth_in), 557 557 + &enable_auth_out, sizeof(enable_auth_out)); 555 558 if (byte < 0) { 556 559 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); 557 560 return byte; ··· 594 599 session_close_in.port.physical_port = (u8)data->hdcp_ddi; 595 600 session_close_in.port.attached_transcoder = (u8)data->hdcp_transcoder; 596 601 597 597 - byte = intel_hdcp_gsc_msg_send(gsc_context, &session_close_in, 598 598 - sizeof(session_close_in), 599 599 - &session_close_out, 600 600 - sizeof(session_close_out)); 602 602 + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, 603 603 + &session_close_in, sizeof(session_close_in), 604 604 + &session_close_out, sizeof(session_close_out)); 601 605 if (byte < 0) { 602 606 drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); 603 607 return byte; ··· 639 645 640 646 mutex_lock(&display->hdcp.hdcp_mutex); 641 647 642 642 - gsc_context = intel_hdcp_gsc_context_alloc(display->drm); 648 648 + gsc_context = intel_parent_hdcp_gsc_context_alloc(display); 643 649 if (IS_ERR(gsc_context)) { 644 650 ret = PTR_ERR(gsc_context); 645 651 kfree(arbiter); ··· 659 665 660 666 void intel_hdcp_gsc_fini(struct intel_display *display) 661 667 { 662 662 - intel_hdcp_gsc_context_free(display->hdcp.gsc_context); 668 668 + intel_parent_hdcp_gsc_context_free(display, display->hdcp.gsc_context); 663 669 display->hdcp.gsc_context = NULL; 664 670 kfree(display->hdcp.arbiter); 665 671 display->hdcp.arbiter = NULL;

+2 -2

drivers/gpu/drm/i915/display/intel_hdmi.c

reviewed

··· 2518 2518 struct intel_display *display = to_intel_display(connector); 2519 2519 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2520 2520 struct i2c_adapter *ddc = connector->base.ddc; 2521 2521 - intel_wakeref_t wakeref; 2521 2521 + struct ref_tracker *wakeref; 2522 2522 const struct drm_edid *drm_edid; 2523 2523 bool connected = false; 2524 2524 ··· 2561 2561 enum drm_connector_status status = connector_status_disconnected; 2562 2562 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2563 2563 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2564 2564 - intel_wakeref_t wakeref; 2564 2564 + struct ref_tracker *wakeref; 2565 2565 2566 2566 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2567 2567 connector->base.base.id, connector->base.name);

+3 -5

drivers/gpu/drm/i915/display/intel_hotplug.c

reviewed

··· 27 27 #include <drm/drm_print.h> 28 28 #include <drm/drm_probe_helper.h> 29 29 30 30 - #include "i915_drv.h" 31 31 - #include "i915_irq.h" 32 30 #include "intel_connector.h" 33 31 #include "intel_display_core.h" 34 32 #include "intel_display_power.h" ··· 37 39 #include "intel_hdcp.h" 38 40 #include "intel_hotplug.h" 39 41 #include "intel_hotplug_irq.h" 42 42 + #include "intel_parent.h" 40 43 41 44 /** 42 45 * DOC: Hotplug ··· 785 786 container_of(work, typeof(*display), hotplug.poll_init_work); 786 787 struct drm_connector_list_iter conn_iter; 787 788 struct intel_connector *connector; 788 788 - intel_wakeref_t wakeref; 789 789 + struct ref_tracker *wakeref; 789 790 bool enabled; 790 791 791 792 mutex_lock(&display->drm->mode_config.mutex); ··· 1176 1177 static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) 1177 1178 { 1178 1179 struct intel_display *display = m->private; 1179 1179 - struct drm_i915_private *dev_priv = to_i915(display->drm); 1180 1180 struct intel_hotplug *hotplug = &display->hotplug; 1181 1181 1182 1182 /* Synchronize with everything first in case there's been an HPD 1183 1183 * storm, but we haven't finished handling it in the kernel yet 1184 1184 */ 1185 1185 - intel_synchronize_irq(dev_priv); 1185 1185 + intel_parent_irq_synchronize(display); 1186 1186 flush_work(&display->hotplug.dig_port_work); 1187 1187 flush_delayed_work(&display->hotplug.hotplug_work); 1188 1188

+1 -4

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

reviewed

··· 519 519 { 520 520 enum hpd_pin pin; 521 521 u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK); 522 522 - u32 trigger_aux = iir & XELPDP_AUX_TC_MASK; 522 522 + u32 trigger_aux = iir & xelpdp_pica_aux_mask(display); 523 523 u32 pin_mask = 0, long_mask = 0; 524 524 - 525 525 - if (DISPLAY_VER(display) >= 20) 526 526 - trigger_aux |= iir & XE2LPD_AUX_DDI_MASK; 527 524 528 525 for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) { 529 526 u32 val;

-1

drivers/gpu/drm/i915/display/intel_lpe_audio.c

reviewed

··· 71 71 #include <drm/drm_print.h> 72 72 #include <drm/intel/intel_lpe_audio.h> 73 73 74 74 - #include "i915_irq.h" 75 74 #include "intel_audio_regs.h" 76 75 #include "intel_de.h" 77 76 #include "intel_lpe_audio.h"

+9 -9

drivers/gpu/drm/i915/display/intel_lt_phy.c

reviewed

··· 1324 1324 return true; 1325 1325 } 1326 1326 1327 1327 - static intel_wakeref_t intel_lt_phy_transaction_begin(struct intel_encoder *encoder) 1327 1327 + static struct ref_tracker *intel_lt_phy_transaction_begin(struct intel_encoder *encoder) 1328 1328 { 1329 1329 struct intel_display *display = to_intel_display(encoder); 1330 1330 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1331 1331 - intel_wakeref_t wakeref; 1331 1331 + struct ref_tracker *wakeref; 1332 1332 1333 1333 intel_psr_pause(intel_dp); 1334 1334 wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); ··· 1336 1336 return wakeref; 1337 1337 } 1338 1338 1339 1339 - static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref) 1339 1339 + static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, struct ref_tracker *wakeref) 1340 1340 { 1341 1341 struct intel_display *display = to_intel_display(encoder); 1342 1342 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); ··· 1932 1932 u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); 1933 1933 enum phy phy = intel_encoder_to_phy(encoder); 1934 1934 enum port port = encoder->port; 1935 1935 - intel_wakeref_t wakeref = 0; 1935 1935 + struct ref_tracker *wakeref = 0; 1936 1936 u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES 1937 1937 ? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) | 1938 1938 XE3PLPDP_LANE_PHY_PULSE_STATUS(1)) ··· 2060 2060 struct intel_display *display = to_intel_display(encoder); 2061 2061 enum phy phy = intel_encoder_to_phy(encoder); 2062 2062 enum port port = encoder->port; 2063 2063 - intel_wakeref_t wakeref; 2063 2063 + struct ref_tracker *wakeref; 2064 2064 u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); 2065 2065 u32 lane_pipe_reset = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES 2066 2066 ? (XELPDP_LANE_PIPE_RESET(0) | ··· 2137 2137 struct intel_display *display = to_intel_display(encoder); 2138 2138 const struct intel_ddi_buf_trans *trans; 2139 2139 u8 owned_lane_mask; 2140 2140 - intel_wakeref_t wakeref; 2140 2140 + struct ref_tracker *wakeref; 2141 2141 int n_entries, ln; 2142 2142 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2143 2143 ··· 2222 2222 { 2223 2223 u8 owned_lane_mask; 2224 2224 u8 lane; 2225 2225 - intel_wakeref_t wakeref; 2225 2225 + struct ref_tracker *wakeref; 2226 2226 int i, j, k; 2227 2227 2228 2228 pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); ··· 2310 2310 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2311 2311 2312 2312 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2313 2313 - intel_mtl_tbt_pll_enable(encoder, crtc_state); 2313 2313 + intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock); 2314 2314 else 2315 2315 intel_lt_phy_pll_enable(encoder, crtc_state); 2316 2316 } ··· 2320 2320 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2321 2321 2322 2322 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2323 2323 - intel_mtl_tbt_pll_disable(encoder); 2323 2323 + intel_mtl_tbt_pll_disable_clock(encoder); 2324 2324 else 2325 2325 intel_lt_phy_pll_disable(encoder); 2326 2326

-2

drivers/gpu/drm/i915/display/intel_lt_phy.h

reviewed

··· 42 42 const struct intel_crtc_state *crtc_state); 43 43 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder); 44 44 45 45 - #define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35) 46 46 - 47 45 #endif /* __INTEL_LT_PHY_H__ */

+1 -1

drivers/gpu/drm/i915/display/intel_lvds.c

reviewed

··· 105 105 { 106 106 struct intel_display *display = to_intel_display(encoder); 107 107 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); 108 108 - intel_wakeref_t wakeref; 108 108 + struct ref_tracker *wakeref; 109 109 bool ret; 110 110 111 111 wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain);

+1 -1

drivers/gpu/drm/i915/display/intel_modeset_setup.c

reviewed

··· 940 940 { 941 941 struct intel_encoder *encoder; 942 942 struct intel_crtc *crtc; 943 943 - intel_wakeref_t wakeref; 943 943 + struct ref_tracker *wakeref; 944 944 945 945 wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); 946 946

-1

drivers/gpu/drm/i915/display/intel_modeset_verify.c

reviewed

··· 246 246 verify_crtc_state(state, crtc); 247 247 intel_dpll_state_verify(state, crtc); 248 248 intel_mpllb_state_verify(state, crtc); 249 249 - intel_cx0pll_state_verify(state, crtc); 250 249 intel_lt_phy_pll_state_verify(state, crtc); 251 250 } 252 251

-27

drivers/gpu/drm/i915/display/intel_panic.c

reviewed

··· 1 1 - // SPDX-License-Identifier: MIT 2 2 - /* Copyright © 2025 Intel Corporation */ 3 3 - 4 4 - #include <drm/drm_panic.h> 5 5 - 6 6 - #include "gem/i915_gem_object.h" 7 7 - #include "intel_display_types.h" 8 8 - #include "intel_fb.h" 9 9 - #include "intel_panic.h" 10 10 - 11 11 - struct intel_panic *intel_panic_alloc(void) 12 12 - { 13 13 - return i915_gem_object_alloc_panic(); 14 14 - } 15 15 - 16 16 - int intel_panic_setup(struct intel_panic *panic, struct drm_scanout_buffer *sb) 17 17 - { 18 18 - struct intel_framebuffer *fb = sb->private; 19 19 - struct drm_gem_object *obj = intel_fb_bo(&fb->base); 20 20 - 21 21 - return i915_gem_object_panic_setup(panic, sb, obj, fb->panic_tiling); 22 22 - } 23 23 - 24 24 - void intel_panic_finish(struct intel_panic *panic) 25 25 - { 26 26 - return i915_gem_object_panic_finish(panic); 27 27 - }

-14

drivers/gpu/drm/i915/display/intel_panic.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* Copyright © 2025 Intel Corporation */ 3 3 - 4 4 - #ifndef __INTEL_PANIC_H__ 5 5 - #define __INTEL_PANIC_H__ 6 6 - 7 7 - struct drm_scanout_buffer; 8 8 - struct intel_panic; 9 9 - 10 10 - struct intel_panic *intel_panic_alloc(void); 11 11 - int intel_panic_setup(struct intel_panic *panic, struct drm_scanout_buffer *sb); 12 12 - void intel_panic_finish(struct intel_panic *panic); 13 13 - 14 14 - #endif /* __INTEL_PANIC_H__ */

+214

drivers/gpu/drm/i915/display/intel_parent.c

reviewed

··· 1 1 + // SPDX-License-Identifier: MIT 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + /* 5 5 + * Convenience wrapper functions to call the parent interface functions: 6 6 + * 7 7 + * - display->parent->SUBSTRUCT->FUNCTION() 8 8 + * - display->parent->FUNCTION() 9 9 + * 10 10 + * All functions here should be named accordingly: 11 11 + * 12 12 + * - intel_parent_SUBSTRUCT_FUNCTION() 13 13 + * - intel_parent_FUNCTION() 14 14 + * 15 15 + * These functions may use display driver specific types for parameters and 16 16 + * return values, translating them to and from the generic types used in the 17 17 + * function pointer interface. 18 18 + */ 19 19 + 20 20 + #include <drm/drm_print.h> 21 21 + #include <drm/intel/display_parent_interface.h> 22 22 + 23 23 + #include "intel_display_core.h" 24 24 + #include "intel_parent.h" 25 25 + 26 26 + /* hdcp */ 27 27 + ssize_t intel_parent_hdcp_gsc_msg_send(struct intel_display *display, 28 28 + struct intel_hdcp_gsc_context *gsc_context, 29 29 + void *msg_in, size_t msg_in_len, 30 30 + void *msg_out, size_t msg_out_len) 31 31 + { 32 32 + return display->parent->hdcp->gsc_msg_send(gsc_context, msg_in, msg_in_len, msg_out, msg_out_len); 33 33 + } 34 34 + 35 35 + bool intel_parent_hdcp_gsc_check_status(struct intel_display *display) 36 36 + { 37 37 + return display->parent->hdcp->gsc_check_status(display->drm); 38 38 + } 39 39 + 40 40 + struct intel_hdcp_gsc_context *intel_parent_hdcp_gsc_context_alloc(struct intel_display *display) 41 41 + { 42 42 + return display->parent->hdcp->gsc_context_alloc(display->drm); 43 43 + } 44 44 + 45 45 + void intel_parent_hdcp_gsc_context_free(struct intel_display *display, 46 46 + struct intel_hdcp_gsc_context *gsc_context) 47 47 + { 48 48 + display->parent->hdcp->gsc_context_free(gsc_context); 49 49 + } 50 50 + 51 51 + /* irq */ 52 52 + bool intel_parent_irq_enabled(struct intel_display *display) 53 53 + { 54 54 + return display->parent->irq->enabled(display->drm); 55 55 + } 56 56 + 57 57 + void intel_parent_irq_synchronize(struct intel_display *display) 58 58 + { 59 59 + display->parent->irq->synchronize(display->drm); 60 60 + } 61 61 + 62 62 + /* panic */ 63 63 + struct intel_panic *intel_parent_panic_alloc(struct intel_display *display) 64 64 + { 65 65 + return display->parent->panic->alloc(); 66 66 + } 67 67 + 68 68 + int intel_parent_panic_setup(struct intel_display *display, struct intel_panic *panic, struct drm_scanout_buffer *sb) 69 69 + { 70 70 + return display->parent->panic->setup(panic, sb); 71 71 + } 72 72 + 73 73 + void intel_parent_panic_finish(struct intel_display *display, struct intel_panic *panic) 74 74 + { 75 75 + display->parent->panic->finish(panic); 76 76 + } 77 77 + 78 78 + /* pc8 */ 79 79 + void intel_parent_pc8_block(struct intel_display *display) 80 80 + { 81 81 + if (drm_WARN_ON_ONCE(display->drm, !display->parent->pc8)) 82 82 + return; 83 83 + 84 84 + display->parent->pc8->block(display->drm); 85 85 + } 86 86 + 87 87 + void intel_parent_pc8_unblock(struct intel_display *display) 88 88 + { 89 89 + if (drm_WARN_ON_ONCE(display->drm, !display->parent->pc8)) 90 90 + return; 91 91 + 92 92 + display->parent->pc8->unblock(display->drm); 93 93 + } 94 94 + 95 95 + /* rps */ 96 96 + bool intel_parent_rps_available(struct intel_display *display) 97 97 + { 98 98 + return display->parent->rps; 99 99 + } 100 100 + 101 101 + void intel_parent_rps_boost_if_not_started(struct intel_display *display, struct dma_fence *fence) 102 102 + { 103 103 + if (display->parent->rps) 104 104 + display->parent->rps->boost_if_not_started(fence); 105 105 + } 106 106 + 107 107 + void intel_parent_rps_mark_interactive(struct intel_display *display, bool interactive) 108 108 + { 109 109 + if (display->parent->rps) 110 110 + display->parent->rps->mark_interactive(display->drm, interactive); 111 111 + } 112 112 + 113 113 + void intel_parent_rps_ilk_irq_handler(struct intel_display *display) 114 114 + { 115 115 + if (display->parent->rps) 116 116 + display->parent->rps->ilk_irq_handler(display->drm); 117 117 + } 118 118 + 119 119 + /* stolen */ 120 120 + int intel_parent_stolen_insert_node_in_range(struct intel_display *display, 121 121 + struct intel_stolen_node *node, u64 size, 122 122 + unsigned int align, u64 start, u64 end) 123 123 + { 124 124 + return display->parent->stolen->insert_node_in_range(node, size, align, start, end); 125 125 + } 126 126 + 127 127 + int intel_parent_stolen_insert_node(struct intel_display *display, struct intel_stolen_node *node, u64 size, 128 128 + unsigned int align) 129 129 + { 130 130 + if (drm_WARN_ON_ONCE(display->drm, !display->parent->stolen->insert_node)) 131 131 + return -ENODEV; 132 132 + 133 133 + return display->parent->stolen->insert_node(node, size, align); 134 134 + } 135 135 + 136 136 + void intel_parent_stolen_remove_node(struct intel_display *display, 137 137 + struct intel_stolen_node *node) 138 138 + { 139 139 + display->parent->stolen->remove_node(node); 140 140 + } 141 141 + 142 142 + bool intel_parent_stolen_initialized(struct intel_display *display) 143 143 + { 144 144 + return display->parent->stolen->initialized(display->drm); 145 145 + } 146 146 + 147 147 + bool intel_parent_stolen_node_allocated(struct intel_display *display, 148 148 + const struct intel_stolen_node *node) 149 149 + { 150 150 + return display->parent->stolen->node_allocated(node); 151 151 + } 152 152 + 153 153 + u32 intel_parent_stolen_node_offset(struct intel_display *display, struct intel_stolen_node *node) 154 154 + { 155 155 + return display->parent->stolen->node_offset(node); 156 156 + } 157 157 + 158 158 + u64 intel_parent_stolen_area_address(struct intel_display *display) 159 159 + { 160 160 + if (drm_WARN_ON_ONCE(display->drm, !display->parent->stolen->area_address)) 161 161 + return 0; 162 162 + 163 163 + return display->parent->stolen->area_address(display->drm); 164 164 + } 165 165 + 166 166 + u64 intel_parent_stolen_area_size(struct intel_display *display) 167 167 + { 168 168 + if (drm_WARN_ON_ONCE(display->drm, !display->parent->stolen->area_size)) 169 169 + return 0; 170 170 + 171 171 + return display->parent->stolen->area_size(display->drm); 172 172 + } 173 173 + 174 174 + u64 intel_parent_stolen_node_address(struct intel_display *display, struct intel_stolen_node *node) 175 175 + { 176 176 + return display->parent->stolen->node_address(node); 177 177 + } 178 178 + 179 179 + u64 intel_parent_stolen_node_size(struct intel_display *display, const struct intel_stolen_node *node) 180 180 + { 181 181 + return display->parent->stolen->node_size(node); 182 182 + } 183 183 + 184 184 + struct intel_stolen_node *intel_parent_stolen_node_alloc(struct intel_display *display) 185 185 + { 186 186 + return display->parent->stolen->node_alloc(display->drm); 187 187 + } 188 188 + 189 189 + void intel_parent_stolen_node_free(struct intel_display *display, const struct intel_stolen_node *node) 190 190 + { 191 191 + display->parent->stolen->node_free(node); 192 192 + } 193 193 + 194 194 + /* generic */ 195 195 + void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence) 196 196 + { 197 197 + if (display->parent->fence_priority_display) 198 198 + display->parent->fence_priority_display(fence); 199 199 + } 200 200 + 201 201 + bool intel_parent_has_auxccs(struct intel_display *display) 202 202 + { 203 203 + return display->parent->has_auxccs && display->parent->has_auxccs(display->drm); 204 204 + } 205 205 + 206 206 + bool intel_parent_has_fenced_regions(struct intel_display *display) 207 207 + { 208 208 + return display->parent->has_fenced_regions && display->parent->has_fenced_regions(display->drm); 209 209 + } 210 210 + 211 211 + bool intel_parent_vgpu_active(struct intel_display *display) 212 212 + { 213 213 + return display->parent->vgpu_active && display->parent->vgpu_active(display->drm); 214 214 + }

+70

drivers/gpu/drm/i915/display/intel_parent.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #ifndef __INTEL_PARENT_H__ 5 5 + #define __INTEL_PARENT_H__ 6 6 + 7 7 + #include <linux/types.h> 8 8 + 9 9 + struct dma_fence; 10 10 + struct drm_scanout_buffer; 11 11 + struct intel_display; 12 12 + struct intel_hdcp_gsc_context; 13 13 + struct intel_panic; 14 14 + struct intel_stolen_node; 15 15 + 16 16 + /* hdcp */ 17 17 + ssize_t intel_parent_hdcp_gsc_msg_send(struct intel_display *display, 18 18 + struct intel_hdcp_gsc_context *gsc_context, 19 19 + void *msg_in, size_t msg_in_len, 20 20 + void *msg_out, size_t msg_out_len); 21 21 + bool intel_parent_hdcp_gsc_check_status(struct intel_display *display); 22 22 + struct intel_hdcp_gsc_context *intel_parent_hdcp_gsc_context_alloc(struct intel_display *display); 23 23 + void intel_parent_hdcp_gsc_context_free(struct intel_display *display, 24 24 + struct intel_hdcp_gsc_context *gsc_context); 25 25 + 26 26 + /* irq */ 27 27 + bool intel_parent_irq_enabled(struct intel_display *display); 28 28 + void intel_parent_irq_synchronize(struct intel_display *display); 29 29 + 30 30 + /* panic */ 31 31 + struct intel_panic *intel_parent_panic_alloc(struct intel_display *display); 32 32 + int intel_parent_panic_setup(struct intel_display *display, struct intel_panic *panic, struct drm_scanout_buffer *sb); 33 33 + void intel_parent_panic_finish(struct intel_display *display, struct intel_panic *panic); 34 34 + 35 35 + /* pc8 */ 36 36 + void intel_parent_pc8_block(struct intel_display *display); 37 37 + void intel_parent_pc8_unblock(struct intel_display *display); 38 38 + 39 39 + /* rps */ 40 40 + bool intel_parent_rps_available(struct intel_display *display); 41 41 + void intel_parent_rps_boost_if_not_started(struct intel_display *display, struct dma_fence *fence); 42 42 + void intel_parent_rps_mark_interactive(struct intel_display *display, bool interactive); 43 43 + void intel_parent_rps_ilk_irq_handler(struct intel_display *display); 44 44 + 45 45 + /* stolen */ 46 46 + int intel_parent_stolen_insert_node_in_range(struct intel_display *display, 47 47 + struct intel_stolen_node *node, u64 size, 48 48 + unsigned int align, u64 start, u64 end); 49 49 + int intel_parent_stolen_insert_node(struct intel_display *display, struct intel_stolen_node *node, u64 size, 50 50 + unsigned int align); 51 51 + void intel_parent_stolen_remove_node(struct intel_display *display, 52 52 + struct intel_stolen_node *node); 53 53 + bool intel_parent_stolen_initialized(struct intel_display *display); 54 54 + bool intel_parent_stolen_node_allocated(struct intel_display *display, 55 55 + const struct intel_stolen_node *node); 56 56 + u32 intel_parent_stolen_node_offset(struct intel_display *display, struct intel_stolen_node *node); 57 57 + u64 intel_parent_stolen_area_address(struct intel_display *display); 58 58 + u64 intel_parent_stolen_area_size(struct intel_display *display); 59 59 + u64 intel_parent_stolen_node_address(struct intel_display *display, struct intel_stolen_node *node); 60 60 + u64 intel_parent_stolen_node_size(struct intel_display *display, const struct intel_stolen_node *node); 61 61 + struct intel_stolen_node *intel_parent_stolen_node_alloc(struct intel_display *display); 62 62 + void intel_parent_stolen_node_free(struct intel_display *display, const struct intel_stolen_node *node); 63 63 + 64 64 + /* generic */ 65 65 + bool intel_parent_has_auxccs(struct intel_display *display); 66 66 + bool intel_parent_has_fenced_regions(struct intel_display *display); 67 67 + bool intel_parent_vgpu_active(struct intel_display *display); 68 68 + void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence); 69 69 + 70 70 + #endif /* __INTEL_PARENT_H__ */

+3 -5

drivers/gpu/drm/i915/display/intel_pipe_crc.c

reviewed

··· 30 30 31 31 #include <drm/drm_print.h> 32 32 33 33 - #include "i915_drv.h" 34 34 - #include "i915_irq.h" 35 33 #include "intel_atomic.h" 36 34 #include "intel_de.h" 37 35 #include "intel_display_irq.h" 38 36 #include "intel_display_regs.h" 39 37 #include "intel_display_types.h" 38 38 + #include "intel_parent.h" 40 39 #include "intel_pipe_crc.h" 41 40 #include "intel_pipe_crc_regs.h" 42 41 ··· 588 589 enum intel_display_power_domain power_domain; 589 590 enum intel_pipe_crc_source source; 590 591 enum pipe pipe = crtc->pipe; 591 591 - intel_wakeref_t wakeref; 592 592 + struct ref_tracker *wakeref; 592 593 u32 val = 0; /* shut up gcc */ 593 594 int ret = 0; 594 595 bool enable; ··· 657 658 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc) 658 659 { 659 660 struct intel_display *display = to_intel_display(crtc); 660 660 - struct drm_i915_private *dev_priv = to_i915(display->drm); 661 661 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; 662 662 enum pipe pipe = crtc->pipe; 663 663 ··· 667 669 668 670 intel_de_write(display, PIPE_CRC_CTL(display, pipe), 0); 669 671 intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe)); 670 670 - intel_synchronize_irq(dev_priv); 672 672 + intel_parent_irq_synchronize(display); 671 673 }

+49 -47

drivers/gpu/drm/i915/display/intel_plane.c

reviewed

··· 45 45 #include <drm/drm_panic.h> 46 46 #include <drm/drm_print.h> 47 47 48 48 - #include "gem/i915_gem_object.h" 49 48 #include "i9xx_plane_regs.h" 50 49 #include "intel_cdclk.h" 51 50 #include "intel_cursor.h" ··· 55 56 #include "intel_fb.h" 56 57 #include "intel_fb_pin.h" 57 58 #include "intel_fbdev.h" 58 58 - #include "intel_panic.h" 59 59 + #include "intel_parent.h" 59 60 #include "intel_plane.h" 60 61 #include "intel_psr.h" 61 62 #include "skl_scaler.h" ··· 178 179 DISPLAY_INFO(display)->cursor_needs_physical; 179 180 } 180 181 181 181 - bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format, 182 182 + bool intel_plane_can_async_flip(struct intel_plane *plane, 183 183 + const struct drm_format_info *info, 182 184 u64 modifier) 183 185 { 184 184 - if (intel_format_info_is_yuv_semiplanar(drm_format_info(format), modifier) || 185 185 - format == DRM_FORMAT_C8) 186 186 + if (intel_format_info_is_yuv_semiplanar(info, modifier) || 187 187 + info->format == DRM_FORMAT_C8) 186 188 return false; 187 189 188 190 return plane->can_async_flip && plane->can_async_flip(modifier); 189 191 } 190 192 191 191 - bool intel_plane_format_mod_supported_async(struct drm_plane *plane, 192 192 - u32 format, 193 193 - u64 modifier) 193 193 + bool intel_plane_format_mod_supported_async(struct drm_plane *_plane, 194 194 + u32 format, u64 modifier) 194 195 { 195 195 - if (!plane->funcs->format_mod_supported(plane, format, modifier)) 196 196 + struct intel_plane *plane = to_intel_plane(_plane); 197 197 + const struct drm_format_info *info; 198 198 + 199 199 + if (!plane->base.funcs->format_mod_supported(&plane->base, format, modifier)) 196 200 return false; 197 201 198 198 - return intel_plane_can_async_flip(to_intel_plane(plane), 199 199 - format, modifier); 202 202 + info = drm_get_format_info(plane->base.dev, format, modifier); 203 203 + 204 204 + return intel_plane_can_async_flip(plane, info, modifier); 200 205 } 201 206 202 207 unsigned int intel_adjusted_rate(const struct drm_rect *src, ··· 654 651 ilk_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state)) 655 652 new_crtc_state->disable_cxsr = true; 656 653 657 657 - if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) { 654 654 + if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) 658 655 new_crtc_state->do_async_flip = true; 659 659 - new_crtc_state->async_flip_planes |= BIT(plane->id); 660 660 - } else if (plane->need_async_flip_toggle_wa && 661 661 - new_crtc_state->uapi.async_flip) { 656 656 + 657 657 + if (new_crtc_state->uapi.async_flip) { 662 658 /* 663 659 * On platforms with double buffered async flip bit we 664 660 * set the bit already one frame early during the sync ··· 665 663 * hardware will therefore be ready to perform a real 666 664 * async flip during the next commit, without having 667 665 * to wait yet another frame for the bit to latch. 666 666 + * 667 667 + * async_flip_planes bitmask is also used by selective 668 668 + * fetch calculation to choose full frame update. 668 669 */ 669 670 new_crtc_state->async_flip_planes |= BIT(plane->id); 670 671 } ··· 1240 1235 goto unpin_fb; 1241 1236 1242 1237 if (new_plane_state->uapi.fence) { 1243 1243 - i915_gem_fence_wait_priority_display(new_plane_state->uapi.fence); 1244 1244 - 1238 1238 + intel_parent_fence_priority_display(display, new_plane_state->uapi.fence); 1245 1239 intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc, 1246 1240 new_plane_state->uapi.fence); 1247 1241 } ··· 1334 1330 return offset; 1335 1331 } 1336 1332 1337 1337 - static void intel_panic_flush(struct drm_plane *plane) 1333 1333 + static void intel_panic_flush(struct drm_plane *_plane) 1338 1334 { 1339 1339 - struct intel_plane_state *plane_state = to_intel_plane_state(plane->state); 1340 1340 - struct intel_crtc_state *crtc_state = to_intel_crtc_state(plane->state->crtc->state); 1341 1341 - struct intel_plane *iplane = to_intel_plane(plane); 1342 1342 - struct intel_display *display = to_intel_display(iplane); 1343 1343 - struct drm_framebuffer *fb = plane_state->hw.fb; 1344 1344 - struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1335 1335 + struct intel_plane *plane = to_intel_plane(_plane); 1336 1336 + struct intel_display *display = to_intel_display(plane); 1337 1337 + const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); 1338 1338 + struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); 1339 1339 + const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 1340 1340 + const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); 1345 1341 1346 1346 - intel_panic_finish(intel_fb->panic); 1342 1342 + intel_parent_panic_finish(display, fb->panic); 1347 1343 1348 1344 if (crtc_state->enable_psr2_sel_fetch) { 1349 1345 /* Force a full update for psr2 */ 1350 1350 - intel_psr2_panic_force_full_update(display, crtc_state); 1346 1346 + intel_psr2_panic_force_full_update(crtc_state); 1351 1347 } 1352 1348 1353 1349 /* Flush the cache and don't disable tiling if it's the fbdev framebuffer.*/ 1354 1354 - if (intel_fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { 1350 1350 + if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { 1355 1351 struct iosys_map map; 1356 1352 1357 1353 intel_fbdev_get_map(display->fbdev.fbdev, &map); 1358 1358 - drm_clflush_virt_range(map.vaddr, fb->pitches[0] * fb->height); 1354 1354 + drm_clflush_virt_range(map.vaddr, fb->base.pitches[0] * fb->base.height); 1359 1355 return; 1360 1356 } 1361 1357 1362 1362 - if (fb->modifier && iplane->disable_tiling) 1363 1363 - iplane->disable_tiling(iplane); 1358 1358 + if (fb->base.modifier != DRM_FORMAT_MOD_LINEAR && plane->disable_tiling) 1359 1359 + plane->disable_tiling(plane); 1364 1360 } 1365 1361 1366 1362 static unsigned int (*intel_get_tiling_func(u64 fb_modifier))(unsigned int width, ··· 1398 1394 { 1399 1395 struct intel_plane_state *plane_state; 1400 1396 struct drm_gem_object *obj; 1401 1401 - struct drm_framebuffer *fb; 1402 1402 - struct intel_framebuffer *intel_fb; 1397 1397 + struct intel_framebuffer *fb; 1403 1398 struct intel_display *display = to_intel_display(plane->dev); 1404 1399 1405 1400 if (!plane->state || !plane->state->fb || !plane->state->visible) 1406 1401 return -ENODEV; 1407 1402 1408 1403 plane_state = to_intel_plane_state(plane->state); 1409 1409 - fb = plane_state->hw.fb; 1410 1410 - intel_fb = to_intel_framebuffer(fb); 1404 1404 + fb = to_intel_framebuffer(plane_state->hw.fb); 1411 1405 1412 1412 - obj = intel_fb_bo(fb); 1406 1406 + obj = intel_fb_bo(&fb->base); 1413 1407 if (!obj) 1414 1408 return -ENODEV; 1415 1409 1416 1416 - if (intel_fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { 1410 1410 + if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { 1417 1411 intel_fbdev_get_map(display->fbdev.fbdev, &sb->map[0]); 1418 1412 } else { 1419 1413 int ret; 1420 1414 /* Can't disable tiling if DPT is in use */ 1421 1421 - if (intel_fb_uses_dpt(fb)) { 1422 1422 - if (fb->format->cpp[0] != 4) 1415 1415 + if (intel_fb_uses_dpt(&fb->base)) { 1416 1416 + if (fb->base.format->cpp[0] != 4) 1423 1417 return -EOPNOTSUPP; 1424 1424 - intel_fb->panic_tiling = intel_get_tiling_func(fb->modifier); 1425 1425 - if (!intel_fb->panic_tiling) 1418 1418 + fb->panic_tiling = intel_get_tiling_func(fb->base.modifier); 1419 1419 + if (!fb->panic_tiling) 1426 1420 return -EOPNOTSUPP; 1427 1421 } 1428 1428 - sb->private = intel_fb; 1429 1429 - ret = intel_panic_setup(intel_fb->panic, sb); 1422 1422 + sb->private = fb; 1423 1423 + ret = intel_parent_panic_setup(display, fb->panic, sb); 1430 1424 if (ret) 1431 1425 return ret; 1432 1426 } 1433 1433 - sb->width = fb->width; 1434 1434 - sb->height = fb->height; 1427 1427 + sb->width = fb->base.width; 1428 1428 + sb->height = fb->base.height; 1435 1429 /* Use the generic linear format, because tiling, RC, CCS, CC 1436 1430 * will be disabled in disable_tiling() 1437 1431 */ 1438 1438 - sb->format = drm_format_info(fb->format->format); 1439 1439 - sb->pitch[0] = fb->pitches[0]; 1432 1432 + sb->format = drm_format_info(fb->base.format->format); 1433 1433 + sb->pitch[0] = fb->base.pitches[0]; 1440 1434 1441 1435 return 0; 1442 1436 } ··· 1466 1464 old_plane_state->ggtt_vma == new_plane_state->ggtt_vma) 1467 1465 return; 1468 1466 1469 1469 - drm_vblank_work_init(&old_plane_state->unpin_work, old_plane_state->uapi.crtc, 1467 1467 + drm_vblank_work_init(&old_plane_state->unpin_work, old_plane_state->hw.crtc, 1470 1468 intel_cursor_unpin_work); 1471 1469 } 1472 1470

+3 -1

drivers/gpu/drm/i915/display/intel_plane.h

reviewed

··· 8 8 9 9 #include <linux/types.h> 10 10 11 11 + struct drm_format_info; 11 12 struct drm_plane; 12 13 struct drm_property; 13 14 struct drm_rect; ··· 22 21 23 22 struct intel_plane * 24 23 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id); 25 25 - bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format, 24 24 + bool intel_plane_can_async_flip(struct intel_plane *plane, 25 25 + const struct drm_format_info *info, 26 26 u64 modifier); 27 27 unsigned int intel_adjusted_rate(const struct drm_rect *src, 28 28 const struct drm_rect *dst,

+4 -2

drivers/gpu/drm/i915/display/intel_plane_initial.c

reviewed

··· 39 39 const struct intel_crtc_state *crtc_state = 40 40 to_intel_crtc_state(crtc->base.state); 41 41 42 42 - if (!crtc_state->uapi.active) 42 42 + if (!crtc_state->hw.active) 43 43 continue; 44 44 45 45 if (!plane_state->ggtt_vma) ··· 411 411 struct intel_crtc *crtc; 412 412 413 413 for_each_intel_crtc(display->drm, crtc) { 414 414 + const struct intel_crtc_state *crtc_state = 415 415 + to_intel_crtc_state(crtc->base.state); 414 416 struct intel_initial_plane_config *plane_config = 415 417 &plane_configs[crtc->pipe]; 416 418 417 417 - if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 419 419 + if (!crtc_state->hw.active) 418 420 continue; 419 421 420 422 /*

+19 -44

drivers/gpu/drm/i915/display/intel_pps.c

reviewed

··· 67 67 return "PPS <invalid>"; 68 68 } 69 69 70 70 - intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp) 70 70 + struct ref_tracker *intel_pps_lock(struct intel_dp *intel_dp) 71 71 { 72 72 struct intel_display *display = to_intel_display(intel_dp); 73 73 - intel_wakeref_t wakeref; 73 73 + struct ref_tracker *wakeref; 74 74 75 75 /* 76 76 * See vlv_pps_reset_all() why we need a power domain reference here. ··· 81 81 return wakeref; 82 82 } 83 83 84 84 - intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, 85 85 - intel_wakeref_t wakeref) 84 84 + struct ref_tracker *intel_pps_unlock(struct intel_dp *intel_dp, struct ref_tracker *wakeref) 86 85 { 87 86 struct intel_display *display = to_intel_display(intel_dp); 88 87 ··· 696 697 697 698 void intel_pps_wait_power_cycle(struct intel_dp *intel_dp) 698 699 { 699 699 - intel_wakeref_t wakeref; 700 700 - 701 700 if (!intel_dp_is_edp(intel_dp)) 702 701 return; 703 702 704 704 - with_intel_pps_lock(intel_dp, wakeref) 703 703 + with_intel_pps_lock(intel_dp) 705 704 wait_panel_power_cycle(intel_dp); 706 705 } 707 706 ··· 808 811 void intel_pps_vdd_on(struct intel_dp *intel_dp) 809 812 { 810 813 struct intel_display *display = to_intel_display(intel_dp); 811 811 - intel_wakeref_t wakeref; 812 814 bool vdd; 813 815 814 816 if (!intel_dp_is_edp(intel_dp)) 815 817 return; 816 818 817 819 vdd = false; 818 818 - with_intel_pps_lock(intel_dp, wakeref) 820 820 + with_intel_pps_lock(intel_dp) 819 821 vdd = intel_pps_vdd_on_unlocked(intel_dp); 820 822 INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n", 821 823 dp_to_dig_port(intel_dp)->base.base.base.id, ··· 869 873 870 874 void intel_pps_vdd_off_sync(struct intel_dp *intel_dp) 871 875 { 872 872 - intel_wakeref_t wakeref; 873 873 - 874 876 if (!intel_dp_is_edp(intel_dp)) 875 877 return; 876 878 ··· 877 883 * vdd might still be enabled due to the delayed vdd off. 878 884 * Make sure vdd is actually turned off here. 879 885 */ 880 880 - with_intel_pps_lock(intel_dp, wakeref) 886 886 + with_intel_pps_lock(intel_dp) 881 887 intel_pps_vdd_off_sync_unlocked(intel_dp); 882 888 } 883 889 ··· 886 892 struct intel_pps *pps = container_of(to_delayed_work(__work), 887 893 struct intel_pps, panel_vdd_work); 888 894 struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps); 889 889 - intel_wakeref_t wakeref; 890 895 891 891 - with_intel_pps_lock(intel_dp, wakeref) { 896 896 + with_intel_pps_lock(intel_dp) { 892 897 if (!intel_dp->pps.want_panel_vdd) 893 898 intel_pps_vdd_off_sync_unlocked(intel_dp); 894 899 } ··· 945 952 946 953 void intel_pps_vdd_off(struct intel_dp *intel_dp) 947 954 { 948 948 - intel_wakeref_t wakeref; 949 949 - 950 955 if (!intel_dp_is_edp(intel_dp)) 951 956 return; 952 957 953 953 - with_intel_pps_lock(intel_dp, wakeref) 958 958 + with_intel_pps_lock(intel_dp) 954 959 intel_pps_vdd_off_unlocked(intel_dp, false); 955 960 } 956 961 ··· 1017 1026 1018 1027 void intel_pps_on(struct intel_dp *intel_dp) 1019 1028 { 1020 1020 - intel_wakeref_t wakeref; 1021 1021 - 1022 1029 if (!intel_dp_is_edp(intel_dp)) 1023 1030 return; 1024 1031 1025 1025 - with_intel_pps_lock(intel_dp, wakeref) 1032 1032 + with_intel_pps_lock(intel_dp) 1026 1033 intel_pps_on_unlocked(intel_dp); 1027 1034 } 1028 1035 ··· 1071 1082 1072 1083 void intel_pps_off(struct intel_dp *intel_dp) 1073 1084 { 1074 1074 - intel_wakeref_t wakeref; 1075 1075 - 1076 1085 if (!intel_dp_is_edp(intel_dp)) 1077 1086 return; 1078 1087 1079 1079 - with_intel_pps_lock(intel_dp, wakeref) 1088 1088 + with_intel_pps_lock(intel_dp) 1080 1089 intel_pps_off_unlocked(intel_dp); 1081 1090 } 1082 1091 ··· 1082 1095 void intel_pps_backlight_on(struct intel_dp *intel_dp) 1083 1096 { 1084 1097 struct intel_display *display = to_intel_display(intel_dp); 1085 1085 - intel_wakeref_t wakeref; 1086 1098 1087 1099 /* 1088 1100 * If we enable the backlight right away following a panel power ··· 1091 1105 */ 1092 1106 wait_backlight_on(intel_dp); 1093 1107 1094 1094 - with_intel_pps_lock(intel_dp, wakeref) { 1108 1108 + with_intel_pps_lock(intel_dp) { 1095 1109 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1096 1110 u32 pp; 1097 1111 ··· 1107 1121 void intel_pps_backlight_off(struct intel_dp *intel_dp) 1108 1122 { 1109 1123 struct intel_display *display = to_intel_display(intel_dp); 1110 1110 - intel_wakeref_t wakeref; 1111 1124 1112 1125 if (!intel_dp_is_edp(intel_dp)) 1113 1126 return; 1114 1127 1115 1115 - with_intel_pps_lock(intel_dp, wakeref) { 1128 1128 + with_intel_pps_lock(intel_dp) { 1116 1129 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1117 1130 u32 pp; 1118 1131 ··· 1134 1149 { 1135 1150 struct intel_display *display = to_intel_display(connector); 1136 1151 struct intel_dp *intel_dp = intel_attached_dp(connector); 1137 1137 - intel_wakeref_t wakeref; 1138 1152 bool is_enabled; 1139 1153 1140 1154 is_enabled = false; 1141 1141 - with_intel_pps_lock(intel_dp, wakeref) 1155 1155 + with_intel_pps_lock(intel_dp) 1142 1156 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE; 1143 1157 if (is_enabled == enable) 1144 1158 return; ··· 1235 1251 /* Call on all DP, not just eDP */ 1236 1252 void vlv_pps_pipe_reset(struct intel_dp *intel_dp) 1237 1253 { 1238 1238 - intel_wakeref_t wakeref; 1239 1239 - 1240 1240 - with_intel_pps_lock(intel_dp, wakeref) 1254 1254 + with_intel_pps_lock(intel_dp) 1241 1255 intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp); 1242 1256 } 1243 1257 ··· 1311 1329 { 1312 1330 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1313 1331 1314 1314 - intel_wakeref_t wakeref; 1315 1315 - 1316 1316 - with_intel_pps_lock(intel_dp, wakeref) 1332 1332 + with_intel_pps_lock(intel_dp) 1317 1333 intel_dp->pps.vlv_active_pipe = INVALID_PIPE; 1318 1334 } 1319 1335 ··· 1342 1362 1343 1363 bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp) 1344 1364 { 1345 1345 - intel_wakeref_t wakeref; 1346 1365 bool have_power = false; 1347 1366 1348 1348 - with_intel_pps_lock(intel_dp, wakeref) { 1367 1367 + with_intel_pps_lock(intel_dp) { 1349 1368 have_power = edp_have_panel_power(intel_dp) || 1350 1369 edp_have_panel_vdd(intel_dp); 1351 1370 } ··· 1671 1692 void intel_pps_encoder_reset(struct intel_dp *intel_dp) 1672 1693 { 1673 1694 struct intel_display *display = to_intel_display(intel_dp); 1674 1674 - intel_wakeref_t wakeref; 1675 1695 1676 1696 if (!intel_dp_is_edp(intel_dp)) 1677 1697 return; 1678 1698 1679 1679 - with_intel_pps_lock(intel_dp, wakeref) { 1699 1699 + with_intel_pps_lock(intel_dp) { 1680 1700 /* 1681 1701 * Reinit the power sequencer also on the resume path, in case 1682 1702 * BIOS did something nasty with it. ··· 1694 1716 1695 1717 bool intel_pps_init(struct intel_dp *intel_dp) 1696 1718 { 1697 1697 - intel_wakeref_t wakeref; 1698 1719 bool ret; 1699 1720 1700 1721 intel_dp->pps.initializing = true; ··· 1701 1724 1702 1725 pps_init_timestamps(intel_dp); 1703 1726 1704 1704 - with_intel_pps_lock(intel_dp, wakeref) { 1727 1727 + with_intel_pps_lock(intel_dp) { 1705 1728 ret = pps_initial_setup(intel_dp); 1706 1729 1707 1730 pps_init_delays(intel_dp); ··· 1737 1760 1738 1761 void intel_pps_init_late(struct intel_dp *intel_dp) 1739 1762 { 1740 1740 - intel_wakeref_t wakeref; 1741 1741 - 1742 1742 - with_intel_pps_lock(intel_dp, wakeref) { 1763 1763 + with_intel_pps_lock(intel_dp) { 1743 1764 /* Reinit delays after per-panel info has been parsed from VBT */ 1744 1765 pps_init_late(intel_dp); 1745 1766

+8 -6

drivers/gpu/drm/i915/display/intel_pps.h

reviewed

··· 8 8 9 9 #include <linux/types.h> 10 10 11 11 - #include "intel_wakeref.h" 12 12 - 13 11 enum pipe; 14 12 struct intel_connector; 15 13 struct intel_crtc_state; 16 14 struct intel_display; 17 15 struct intel_dp; 18 16 struct intel_encoder; 17 17 + struct ref_tracker; 19 18 20 20 - intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp); 21 21 - intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref); 19 19 + struct ref_tracker *intel_pps_lock(struct intel_dp *intel_dp); 20 20 + struct ref_tracker *intel_pps_unlock(struct intel_dp *intel_dp, struct ref_tracker *wakeref); 22 21 23 23 - #define with_intel_pps_lock(dp, wf) \ 24 24 - for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf))) 22 22 + #define __with_intel_pps_lock(dp, wf) \ 23 23 + for (struct ref_tracker *(wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf))) 24 24 + 25 25 + #define with_intel_pps_lock(dp) \ 26 26 + __with_intel_pps_lock((dp), __UNIQUE_ID(wakeref)) 25 27 26 28 void intel_pps_backlight_on(struct intel_dp *intel_dp); 27 29 void intel_pps_backlight_off(struct intel_dp *intel_dp);

+167 -150

drivers/gpu/drm/i915/display/intel_psr.c

reviewed

··· 494 494 return val; 495 495 } 496 496 497 497 - static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) 498 498 - { 499 499 - u8 su_capability = 0; 500 500 - 501 501 - if (intel_dp->psr.sink_panel_replay_su_support) { 502 502 - if (drm_dp_dpcd_read_byte(&intel_dp->aux, 503 503 - DP_PANEL_REPLAY_CAP_CAPABILITY, 504 504 - &su_capability) < 0) 505 505 - return 0; 506 506 - } else { 507 507 - su_capability = intel_dp->psr_dpcd[1]; 508 508 - } 509 509 - 510 510 - return su_capability; 511 511 - } 512 512 - 513 513 - static unsigned int 514 514 - intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) 515 515 - { 516 516 - return intel_dp->psr.sink_panel_replay_su_support ? 517 517 - DP_PANEL_REPLAY_CAP_X_GRANULARITY : 518 518 - DP_PSR2_SU_X_GRANULARITY; 519 519 - } 520 520 - 521 521 - static unsigned int 522 522 - intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) 523 523 - { 524 524 - return intel_dp->psr.sink_panel_replay_su_support ? 525 525 - DP_PANEL_REPLAY_CAP_Y_GRANULARITY : 526 526 - DP_PSR2_SU_Y_GRANULARITY; 527 527 - } 528 528 - 529 529 - /* 530 530 - * Note: Bits related to granularity are same in panel replay and psr 531 531 - * registers. Rely on PSR definitions on these "common" bits. 532 532 - */ 533 533 - static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) 497 497 + static void _psr_compute_su_granularity(struct intel_dp *intel_dp, 498 498 + struct intel_connector *connector) 534 499 { 535 500 struct intel_display *display = to_intel_display(intel_dp); 536 501 ssize_t r; 537 537 - u16 w; 502 502 + __le16 w; 538 503 u8 y; 539 539 - 540 540 - /* 541 541 - * TODO: Do we need to take into account panel supporting both PSR and 542 542 - * Panel replay? 543 543 - */ 544 504 545 505 /* 546 506 * If sink don't have specific granularity requirements set legacy 547 507 * ones. 548 508 */ 549 549 - if (!(intel_dp_get_su_capability(intel_dp) & 550 550 - DP_PSR2_SU_GRANULARITY_REQUIRED)) { 509 509 + if (!(connector->dp.psr_caps.dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { 551 510 /* As PSR2 HW sends full lines, we do not care about x granularity */ 552 552 - w = 4; 511 511 + w = cpu_to_le16(4); 553 512 y = 4; 554 513 goto exit; 555 514 } 556 515 557 557 - r = drm_dp_dpcd_read(&intel_dp->aux, 558 558 - intel_dp_get_su_x_granularity_offset(intel_dp), 559 559 - &w, 2); 560 560 - if (r != 2) 516 516 + r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w)); 517 517 + if (r != sizeof(w)) 561 518 drm_dbg_kms(display->drm, 562 519 "Unable to read selective update x granularity\n"); 563 520 /* 564 521 * Spec says that if the value read is 0 the default granularity should 565 522 * be used instead. 566 523 */ 567 567 - if (r != 2 || w == 0) 568 568 - w = 4; 524 524 + if (r != sizeof(w) || w == 0) 525 525 + w = cpu_to_le16(4); 569 526 570 570 - r = drm_dp_dpcd_read(&intel_dp->aux, 571 571 - intel_dp_get_su_y_granularity_offset(intel_dp), 572 572 - &y, 1); 527 527 + r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); 573 528 if (r != 1) { 574 529 drm_dbg_kms(display->drm, 575 530 "Unable to read selective update y granularity\n"); ··· 534 579 y = 1; 535 580 536 581 exit: 537 537 - intel_dp->psr.su_w_granularity = w; 538 538 - intel_dp->psr.su_y_granularity = y; 582 582 + connector->dp.psr_caps.su_w_granularity = le16_to_cpu(w); 583 583 + connector->dp.psr_caps.su_y_granularity = y; 539 584 } 540 585 541 586 static enum intel_panel_replay_dsc_support 542 542 - compute_pr_dsc_support(struct intel_dp *intel_dp) 587 587 + compute_pr_dsc_support(struct intel_connector *connector) 543 588 { 544 589 u8 pr_dsc_mode; 545 590 u8 val; 546 591 547 547 - val = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; 592 592 + val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; 548 593 pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val); 549 594 550 595 switch (pr_dsc_mode) { ··· 576 621 }; 577 622 } 578 623 579 579 - static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) 624 624 + static void _panel_replay_compute_su_granularity(struct intel_connector *connector) 625 625 + { 626 626 + u16 w; 627 627 + u8 y; 628 628 + 629 629 + if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 630 630 + DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) { 631 631 + w = 4; 632 632 + y = 4; 633 633 + goto exit; 634 634 + } 635 635 + 636 636 + /* 637 637 + * Spec says that if the value read is 0 the default granularity should 638 638 + * be used instead. 639 639 + */ 640 640 + w = le16_to_cpu(*(__le16 *)&connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4; 641 641 + y = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1; 642 642 + 643 643 + exit: 644 644 + connector->dp.panel_replay_caps.su_w_granularity = w; 645 645 + connector->dp.panel_replay_caps.su_y_granularity = y; 646 646 + } 647 647 + 648 648 + static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 580 649 { 581 650 struct intel_display *display = to_intel_display(intel_dp); 582 651 int ret; ··· 610 631 return; 611 632 612 633 ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT, 613 613 - &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd)); 634 634 + &connector->dp.panel_replay_caps.dpcd, 635 635 + sizeof(connector->dp.panel_replay_caps.dpcd)); 614 636 if (ret < 0) 615 637 return; 616 638 617 617 - if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 639 639 + if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 618 640 DP_PANEL_REPLAY_SUPPORT)) 619 641 return; 620 642 ··· 626 646 return; 627 647 } 628 648 629 629 - if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 649 649 + if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 630 650 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { 631 651 drm_dbg_kms(display->drm, 632 652 "Panel doesn't support early transport, eDP Panel Replay not possible\n"); ··· 634 654 } 635 655 } 636 656 657 657 + connector->dp.panel_replay_caps.support = true; 637 658 intel_dp->psr.sink_panel_replay_support = true; 638 659 639 639 - if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 640 640 - DP_PANEL_REPLAY_SU_SUPPORT) 641 641 - intel_dp->psr.sink_panel_replay_su_support = true; 660 660 + if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 661 661 + DP_PANEL_REPLAY_SU_SUPPORT) { 662 662 + connector->dp.panel_replay_caps.su_support = true; 642 663 643 643 - intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp); 664 664 + _panel_replay_compute_su_granularity(connector); 665 665 + } 666 666 + 667 667 + connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector); 644 668 645 669 drm_dbg_kms(display->drm, 646 670 "Panel replay %sis supported by panel (in DSC mode: %s)\n", 647 647 - intel_dp->psr.sink_panel_replay_su_support ? 671 671 + connector->dp.panel_replay_caps.su_support ? 648 672 "selective_update " : "", 649 649 - panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support)); 673 673 + panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 650 674 } 651 675 652 652 - static void _psr_init_dpcd(struct intel_dp *intel_dp) 676 676 + static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 653 677 { 654 678 struct intel_display *display = to_intel_display(intel_dp); 655 679 int ret; 656 680 657 657 - ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, 658 658 - sizeof(intel_dp->psr_dpcd)); 681 681 + ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_caps.dpcd, 682 682 + sizeof(connector->dp.psr_caps.dpcd)); 659 683 if (ret < 0) 660 684 return; 661 685 662 662 - if (!intel_dp->psr_dpcd[0]) 686 686 + if (!connector->dp.psr_caps.dpcd[0]) 663 687 return; 664 688 665 689 drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n", 666 666 - intel_dp->psr_dpcd[0]); 690 690 + connector->dp.psr_caps.dpcd[0]); 667 691 668 692 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { 669 693 drm_dbg_kms(display->drm, ··· 681 697 return; 682 698 } 683 699 700 700 + connector->dp.psr_caps.support = true; 684 701 intel_dp->psr.sink_support = true; 685 685 - intel_dp->psr.sink_sync_latency = 686 686 - intel_dp_get_sink_sync_latency(intel_dp); 702 702 + 703 703 + connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp); 687 704 688 705 if (DISPLAY_VER(display) >= 9 && 689 689 - intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { 690 690 - bool y_req = intel_dp->psr_dpcd[1] & 706 706 + connector->dp.psr_caps.dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { 707 707 + bool y_req = connector->dp.psr_caps.dpcd[1] & 691 708 DP_PSR2_SU_Y_COORDINATE_REQUIRED; 692 709 693 710 /* ··· 702 717 * Y-coordinate requirement panels we would need to enable 703 718 * GTC first. 704 719 */ 705 705 - intel_dp->psr.sink_psr2_support = y_req && 720 720 + connector->dp.psr_caps.su_support = y_req && 706 721 intel_alpm_aux_wake_supported(intel_dp); 707 722 drm_dbg_kms(display->drm, "PSR2 %ssupported\n", 708 708 - intel_dp->psr.sink_psr2_support ? "" : "not "); 723 723 + connector->dp.psr_caps.su_support ? "" : "not "); 709 724 } 725 725 + 726 726 + if (connector->dp.psr_caps.su_support) 727 727 + _psr_compute_su_granularity(intel_dp, connector); 710 728 } 711 729 712 712 - void intel_psr_init_dpcd(struct intel_dp *intel_dp) 730 730 + void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) 713 731 { 714 714 - _psr_init_dpcd(intel_dp); 732 732 + _psr_init_dpcd(intel_dp, connector); 715 733 716 716 - _panel_replay_init_dpcd(intel_dp); 717 717 - 718 718 - if (intel_dp->psr.sink_psr2_support || 719 719 - intel_dp->psr.sink_panel_replay_su_support) 720 720 - intel_dp_get_su_granularity(intel_dp); 734 734 + _panel_replay_init_dpcd(intel_dp, connector); 721 735 } 722 736 723 737 static void hsw_psr_setup_aux(struct intel_dp *intel_dp) ··· 756 772 aux_ctl); 757 773 } 758 774 759 759 - static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay) 775 775 + static bool psr2_su_region_et_valid(struct intel_connector *connector, bool panel_replay) 760 776 { 777 777 + struct intel_dp *intel_dp = intel_attached_dp(connector); 761 778 struct intel_display *display = to_intel_display(intel_dp); 762 779 763 780 if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) || ··· 766 781 return false; 767 782 768 783 return panel_replay ? 769 769 - intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 784 784 + connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 770 785 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : 771 771 - intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; 786 786 + connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; 772 787 } 773 788 774 789 static void _panel_replay_enable_sink(struct intel_dp *intel_dp, ··· 909 924 * off-by-one issue that HW has in some cases. 910 925 */ 911 926 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); 912 912 - idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); 927 927 + idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1); 913 928 914 929 if (drm_WARN_ON(display->drm, idle_frames > 0xf)) 915 930 idle_frames = 0xf; ··· 1004 1019 1005 1020 static u8 frames_before_su_entry(struct intel_dp *intel_dp) 1006 1021 { 1022 1022 + struct intel_connector *connector = intel_dp->attached_connector; 1007 1023 u8 frames_before_su_entry; 1008 1024 1009 1025 frames_before_su_entry = max_t(u8, 1010 1010 - intel_dp->psr.sink_sync_latency + 1, 1026 1026 + connector->dp.psr_caps.sync_latency + 1, 1011 1027 2); 1012 1028 1013 1029 /* Entry setup frames must be at least 1 less than frames before SU entry */ ··· 1290 1304 return crtc_state->enable_psr2_sel_fetch = true; 1291 1305 } 1292 1306 1293 1293 - static bool psr2_granularity_check(struct intel_dp *intel_dp, 1294 1294 - struct intel_crtc_state *crtc_state) 1307 1307 + static bool psr2_granularity_check(struct intel_crtc_state *crtc_state, 1308 1308 + struct intel_connector *connector) 1295 1309 { 1310 1310 + struct intel_dp *intel_dp = intel_attached_dp(connector); 1296 1311 struct intel_display *display = to_intel_display(intel_dp); 1297 1312 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1298 1313 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1299 1314 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1300 1315 u16 y_granularity = 0; 1316 1316 + u16 sink_y_granularity = crtc_state->has_panel_replay ? 1317 1317 + connector->dp.panel_replay_caps.su_y_granularity : 1318 1318 + connector->dp.psr_caps.su_y_granularity; 1319 1319 + u16 sink_w_granularity = crtc_state->has_panel_replay ? 1320 1320 + connector->dp.panel_replay_caps.su_w_granularity : 1321 1321 + connector->dp.psr_caps.su_w_granularity; 1301 1322 1302 1323 /* PSR2 HW only send full lines so we only need to validate the width */ 1303 1303 - if (crtc_hdisplay % intel_dp->psr.su_w_granularity) 1324 1324 + if (crtc_hdisplay % sink_w_granularity) 1304 1325 return false; 1305 1326 1306 1306 - if (crtc_vdisplay % intel_dp->psr.su_y_granularity) 1327 1327 + if (crtc_vdisplay % sink_y_granularity) 1307 1328 return false; 1308 1329 1309 1330 /* HW tracking is only aligned to 4 lines */ 1310 1331 if (!crtc_state->enable_psr2_sel_fetch) 1311 1311 - return intel_dp->psr.su_y_granularity == 4; 1332 1332 + return sink_y_granularity == 4; 1312 1333 1313 1334 /* 1314 1335 * adl_p and mtl platforms have 1 line granularity. ··· 1323 1330 * to match sink requirement if multiple of 4. 1324 1331 */ 1325 1332 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1326 1326 - y_granularity = intel_dp->psr.su_y_granularity; 1327 1327 - else if (intel_dp->psr.su_y_granularity <= 2) 1333 1333 + y_granularity = sink_y_granularity; 1334 1334 + else if (sink_y_granularity <= 2) 1328 1335 y_granularity = 4; 1329 1329 - else if ((intel_dp->psr.su_y_granularity % 4) == 0) 1330 1330 - y_granularity = intel_dp->psr.su_y_granularity; 1336 1336 + else if ((sink_y_granularity % 4) == 0) 1337 1337 + y_granularity = sink_y_granularity; 1331 1338 1332 1339 if (y_granularity == 0 || crtc_vdisplay % y_granularity) 1333 1340 return false; ··· 1365 1372 } 1366 1373 1367 1374 static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, 1375 1375 + struct drm_connector_state *conn_state, 1368 1376 const struct drm_display_mode *adjusted_mode) 1369 1377 { 1370 1378 struct intel_display *display = to_intel_display(intel_dp); 1371 1371 - int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 1379 1379 + struct intel_connector *connector = to_intel_connector(conn_state->connector); 1380 1380 + int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_caps.dpcd); 1372 1381 int entry_setup_frames = 0; 1373 1382 1374 1383 if (psr_setup_time < 0) { 1375 1384 drm_dbg_kms(display->drm, 1376 1385 "PSR condition failed: Invalid PSR setup time (0x%02x)\n", 1377 1377 - intel_dp->psr_dpcd[1]); 1386 1386 + connector->dp.psr_caps.dpcd[1]); 1378 1387 return -ETIME; 1379 1388 } 1380 1389 ··· 1517 1522 } 1518 1523 1519 1524 static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 1520 1520 - struct intel_crtc_state *crtc_state) 1525 1525 + struct intel_crtc_state *crtc_state, 1526 1526 + struct drm_connector_state *conn_state) 1521 1527 { 1522 1528 struct intel_display *display = to_intel_display(intel_dp); 1529 1529 + struct intel_connector *connector = to_intel_connector(conn_state->connector); 1523 1530 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; 1524 1531 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; 1525 1532 int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; 1526 1533 1527 1527 - if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1) 1534 1534 + if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1) 1528 1535 return false; 1529 1536 1530 1537 /* JSL and EHL only supports eDP 1.3 */ ··· 1618 1621 return true; 1619 1622 } 1620 1623 1621 1621 - static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, 1622 1622 - struct intel_crtc_state *crtc_state) 1624 1624 + static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state, 1625 1625 + struct drm_connector_state *conn_state) 1623 1626 { 1627 1627 + struct intel_connector *connector = to_intel_connector(conn_state->connector); 1628 1628 + struct intel_dp *intel_dp = intel_attached_dp(connector); 1624 1629 struct intel_display *display = to_intel_display(intel_dp); 1625 1630 1626 1631 if (HAS_PSR2_SEL_FETCH(display) && ··· 1639 1640 goto unsupported; 1640 1641 } 1641 1642 1642 1642 - if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state)) 1643 1643 + if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state, 1644 1644 + conn_state)) 1643 1645 goto unsupported; 1644 1646 1645 1647 if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { ··· 1653 1653 if (DISPLAY_VER(display) < 14) 1654 1654 goto unsupported; 1655 1655 1656 1656 - if (!intel_dp->psr.sink_panel_replay_su_support) 1656 1656 + if (!connector->dp.panel_replay_caps.su_support) 1657 1657 goto unsupported; 1658 1658 1659 1659 if (intel_dsc_enabled_on_link(crtc_state) && 1660 1660 - intel_dp->psr.sink_panel_replay_dsc_support != 1660 1660 + connector->dp.panel_replay_caps.dsc_support != 1661 1661 INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) { 1662 1662 drm_dbg_kms(display->drm, 1663 1663 "Selective update with Panel Replay not enabled because it's not supported with DSC\n"); ··· 1671 1671 goto unsupported; 1672 1672 } 1673 1673 1674 1674 - if (!psr2_granularity_check(intel_dp, crtc_state)) { 1674 1674 + if (!psr2_granularity_check(crtc_state, connector)) { 1675 1675 drm_dbg_kms(display->drm, 1676 1676 "Selective update not enabled, SU granularity not compatible\n"); 1677 1677 goto unsupported; 1678 1678 } 1679 1679 1680 1680 - crtc_state->enable_psr2_su_region_et = 1681 1681 - psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay); 1680 1680 + crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector, 1681 1681 + crtc_state->has_panel_replay); 1682 1682 1683 1683 return true; 1684 1684 ··· 1688 1688 } 1689 1689 1690 1690 static bool _psr_compute_config(struct intel_dp *intel_dp, 1691 1691 - struct intel_crtc_state *crtc_state) 1691 1691 + struct intel_crtc_state *crtc_state, 1692 1692 + struct drm_connector_state *conn_state) 1692 1693 { 1693 1694 struct intel_display *display = to_intel_display(intel_dp); 1694 1695 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; ··· 1704 1703 if (crtc_state->vrr.enable) 1705 1704 return false; 1706 1705 1707 1707 - entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode); 1706 1706 + entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode); 1708 1707 1709 1708 if (entry_setup_frames >= 0) { 1710 1709 intel_dp->psr.entry_setup_frames = entry_setup_frames; ··· 1718 1717 return true; 1719 1718 } 1720 1719 1721 1721 - static bool 1722 1722 - _panel_replay_compute_config(struct intel_dp *intel_dp, 1723 1723 - struct intel_crtc_state *crtc_state, 1724 1724 - const struct drm_connector_state *conn_state) 1720 1720 + static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector) 1725 1721 { 1726 1726 - struct intel_display *display = to_intel_display(intel_dp); 1722 1722 + return (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1723 1723 + DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP); 1724 1724 + } 1725 1725 + 1726 1726 + static inline bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector) 1727 1727 + { 1728 1728 + return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & 1729 1729 + DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR); 1730 1730 + } 1731 1731 + 1732 1732 + static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state, 1733 1733 + const struct drm_connector_state *conn_state) 1734 1734 + { 1727 1735 struct intel_connector *connector = 1728 1736 to_intel_connector(conn_state->connector); 1737 1737 + struct intel_dp *intel_dp = intel_attached_dp(connector); 1738 1738 + struct intel_display *display = to_intel_display(intel_dp); 1729 1739 struct intel_hdcp *hdcp = &connector->hdcp; 1730 1740 1731 1741 if (!CAN_PANEL_REPLAY(intel_dp)) 1742 1742 + return false; 1743 1743 + 1744 1744 + if (!connector->dp.panel_replay_caps.support) 1732 1745 return false; 1733 1746 1734 1747 if (!panel_replay_global_enabled(intel_dp)) { ··· 1757 1742 } 1758 1743 1759 1744 if (intel_dsc_enabled_on_link(crtc_state) && 1760 1760 - intel_dp->psr.sink_panel_replay_dsc_support == 1745 1745 + connector->dp.panel_replay_caps.dsc_support == 1761 1746 INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) { 1762 1747 drm_dbg_kms(display->drm, 1763 1748 "Panel Replay not enabled because it's not supported with DSC\n"); 1764 1749 return false; 1765 1750 } 1751 1751 + 1752 1752 + crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector); 1753 1753 + crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector); 1766 1754 1767 1755 if (!intel_dp_is_edp(intel_dp)) 1768 1756 return true; ··· 1842 1824 struct drm_connector_state *conn_state) 1843 1825 { 1844 1826 struct intel_display *display = to_intel_display(intel_dp); 1827 1827 + struct intel_connector *connector = to_intel_connector(conn_state->connector); 1845 1828 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1846 1829 1847 1830 if (!psr_global_enabled(intel_dp)) { ··· 1874 1855 } 1875 1856 1876 1857 /* Only used for state verification. */ 1877 1877 - crtc_state->panel_replay_dsc_support = intel_dp->psr.sink_panel_replay_dsc_support; 1878 1878 - crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp, 1879 1879 - crtc_state, 1880 1880 - conn_state); 1858 1858 + crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support; 1859 1859 + crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state, conn_state); 1881 1860 1882 1861 crtc_state->has_psr = crtc_state->has_panel_replay ? true : 1883 1883 - _psr_compute_config(intel_dp, crtc_state); 1862 1862 + _psr_compute_config(intel_dp, crtc_state, conn_state); 1884 1863 1885 1864 if (!crtc_state->has_psr) 1886 1865 return; 1887 1866 1888 1888 - crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state); 1867 1867 + crtc_state->has_sel_update = intel_sel_update_config_valid(crtc_state, conn_state); 1889 1868 } 1890 1869 1891 1870 void intel_psr_get_config(struct intel_encoder *encoder, ··· 2718 2701 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { 2719 2702 struct drm_rect inter; 2720 2703 2721 2721 - if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 2704 2704 + if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2722 2705 continue; 2723 2706 2724 2707 if (plane->id != PLANE_CURSOR) ··· 2751 2734 if (plane_state->uapi.dst.y1 < 0 || 2752 2735 plane_state->uapi.dst.x1 < 0 || 2753 2736 plane_state->scaler_id >= 0 || 2754 2754 - plane_state->uapi.rotation != DRM_MODE_ROTATE_0) 2737 2737 + plane_state->hw.rotation != DRM_MODE_ROTATE_0) 2755 2738 return false; 2756 2739 2757 2740 return true; ··· 2766 2749 */ 2767 2750 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) 2768 2751 { 2769 2769 - if (crtc_state->scaler_state.scaler_id >= 0) 2752 2752 + if (crtc_state->scaler_state.scaler_id >= 0 || 2753 2753 + crtc_state->async_flip_planes) 2770 2754 return false; 2771 2755 2772 2756 return true; ··· 2856 2838 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, 2857 2839 .x2 = INT_MAX }; 2858 2840 2859 2859 - if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) 2841 2841 + if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) 2860 2842 continue; 2861 2843 2862 2844 if (!new_plane_state->uapi.visible && ··· 2955 2937 struct drm_rect *sel_fetch_area, inter; 2956 2938 struct intel_plane *linked = new_plane_state->planar_linked_plane; 2957 2939 2958 2958 - if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || 2940 2940 + if (new_plane_state->hw.crtc != crtc_state->uapi.crtc || 2959 2941 !new_plane_state->uapi.visible) 2960 2942 continue; 2961 2943 ··· 3010 2992 return 0; 3011 2993 } 3012 2994 3013 3013 - void intel_psr2_panic_force_full_update(struct intel_display *display, 3014 3014 - struct intel_crtc_state *crtc_state) 2995 2995 + void intel_psr2_panic_force_full_update(const struct intel_crtc_state *crtc_state) 3015 2996 { 2997 2997 + struct intel_display *display = to_intel_display(crtc_state); 3016 2998 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3017 2999 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3018 3000 u32 val = man_trk_ctl_enable_bit_get(display); ··· 4127 4109 seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val); 4128 4110 } 4129 4111 4130 4130 - static void intel_psr_sink_capability(struct intel_dp *intel_dp, 4112 4112 + static void intel_psr_sink_capability(struct intel_connector *connector, 4131 4113 struct seq_file *m) 4132 4114 { 4133 4133 - struct intel_psr *psr = &intel_dp->psr; 4134 4134 - 4135 4115 seq_printf(m, "Sink support: PSR = %s", 4136 4136 - str_yes_no(psr->sink_support)); 4116 4116 + str_yes_no(connector->dp.psr_caps.support)); 4137 4117 4138 4138 - if (psr->sink_support) 4139 4139 - seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); 4140 4140 - if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) 4118 4118 + if (connector->dp.psr_caps.support) 4119 4119 + seq_printf(m, " [0x%02x]", connector->dp.psr_caps.dpcd[0]); 4120 4120 + if (connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) 4141 4121 seq_printf(m, " (Early Transport)"); 4142 4142 - seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support)); 4122 4122 + seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support)); 4143 4123 seq_printf(m, ", Panel Replay Selective Update = %s", 4144 4144 - str_yes_no(psr->sink_panel_replay_su_support)); 4124 4124 + str_yes_no(connector->dp.panel_replay_caps.su_support)); 4145 4125 seq_printf(m, ", Panel Replay DSC support = %s", 4146 4146 - panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support)); 4147 4147 - if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 4126 4126 + panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); 4127 4127 + if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & 4148 4128 DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) 4149 4129 seq_printf(m, " (Early Transport)"); 4150 4130 seq_printf(m, "\n"); ··· 4180 4164 seq_printf(m, " %s\n", psr->no_psr_reason); 4181 4165 } 4182 4166 4183 4183 - static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) 4167 4167 + static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp, 4168 4168 + struct intel_connector *connector) 4184 4169 { 4185 4170 struct intel_display *display = to_intel_display(intel_dp); 4186 4171 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; ··· 4190 4173 bool enabled; 4191 4174 u32 val, psr2_ctl; 4192 4175 4193 4193 - intel_psr_sink_capability(intel_dp, m); 4176 4176 + intel_psr_sink_capability(connector, m); 4194 4177 4195 4195 - if (!(psr->sink_support || psr->sink_panel_replay_support)) 4178 4178 + if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support)) 4196 4179 return 0; 4197 4180 4198 4181 wakeref = intel_display_rpm_get(display); ··· 4306 4289 if (!intel_dp) 4307 4290 return -ENODEV; 4308 4291 4309 4309 - return intel_psr_status(m, intel_dp); 4292 4292 + return intel_psr_status(m, intel_dp, intel_dp->attached_connector); 4310 4293 } 4311 4294 DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status); 4312 4295 ··· 4440 4423 struct intel_connector *connector = m->private; 4441 4424 struct intel_dp *intel_dp = intel_attached_dp(connector); 4442 4425 4443 4443 - return intel_psr_status(m, intel_dp); 4426 4426 + return intel_psr_status(m, intel_dp, connector); 4444 4427 } 4445 4428 DEFINE_SHOW_ATTRIBUTE(i915_psr_status); 4446 4429

+2 -3

drivers/gpu/drm/i915/display/intel_psr.h

reviewed

··· 28 28 bool intel_encoder_can_psr(struct intel_encoder *encoder); 29 29 bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, 30 30 const struct intel_crtc_state *crtc_state); 31 31 - void intel_psr_init_dpcd(struct intel_dp *intel_dp); 31 31 + void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector); 32 32 void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp); 33 33 void intel_psr_pre_plane_update(struct intel_atomic_state *state, 34 34 struct intel_crtc *crtc); ··· 59 59 struct intel_crtc *crtc); 60 60 void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, 61 61 const struct intel_crtc_state *crtc_state); 62 62 - void intel_psr2_panic_force_full_update(struct intel_display *display, 63 63 - struct intel_crtc_state *crtc_state); 62 62 + void intel_psr2_panic_force_full_update(const struct intel_crtc_state *crtc_state); 64 63 void intel_psr_pause(struct intel_dp *intel_dp); 65 64 void intel_psr_resume(struct intel_dp *intel_dp); 66 65 bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state);

+6 -3

drivers/gpu/drm/i915/display/intel_sprite.c

reviewed

··· 462 462 struct intel_display *display = to_intel_display(plane); 463 463 enum intel_display_power_domain power_domain; 464 464 enum plane_id plane_id = plane->id; 465 465 - intel_wakeref_t wakeref; 465 465 + struct ref_tracker *wakeref; 466 466 bool ret; 467 467 468 468 power_domain = POWER_DOMAIN_PIPE(plane->pipe); ··· 893 893 { 894 894 struct intel_display *display = to_intel_display(plane); 895 895 enum intel_display_power_domain power_domain; 896 896 - intel_wakeref_t wakeref; 896 896 + struct ref_tracker *wakeref; 897 897 bool ret; 898 898 899 899 power_domain = POWER_DOMAIN_PIPE(plane->pipe); ··· 1233 1233 { 1234 1234 struct intel_display *display = to_intel_display(plane); 1235 1235 enum intel_display_power_domain power_domain; 1236 1236 - intel_wakeref_t wakeref; 1236 1236 + struct ref_tracker *wakeref; 1237 1237 bool ret; 1238 1238 1239 1239 power_domain = POWER_DOMAIN_PIPE(plane->pipe); ··· 1567 1567 .atomic_duplicate_state = intel_plane_duplicate_state, 1568 1568 .atomic_destroy_state = intel_plane_destroy_state, 1569 1569 .format_mod_supported = g4x_sprite_format_mod_supported, 1570 1570 + .format_mod_supported_async = intel_plane_format_mod_supported_async, 1570 1571 }; 1571 1572 1572 1573 static const struct drm_plane_funcs snb_sprite_funcs = { ··· 1577 1576 .atomic_duplicate_state = intel_plane_duplicate_state, 1578 1577 .atomic_destroy_state = intel_plane_destroy_state, 1579 1578 .format_mod_supported = snb_sprite_format_mod_supported, 1579 1579 + .format_mod_supported_async = intel_plane_format_mod_supported_async, 1580 1580 }; 1581 1581 1582 1582 static const struct drm_plane_funcs vlv_sprite_funcs = { ··· 1587 1585 .atomic_duplicate_state = intel_plane_duplicate_state, 1588 1586 .atomic_destroy_state = intel_plane_destroy_state, 1589 1587 .format_mod_supported = vlv_sprite_format_mod_supported, 1588 1588 + .format_mod_supported_async = intel_plane_format_mod_supported_async, 1590 1589 }; 1591 1590 1592 1591 struct intel_plane *

+17 -23

drivers/gpu/drm/i915/display/intel_tc.c

reviewed

··· 51 51 const struct intel_tc_phy_ops *phy_ops; 52 52 53 53 struct mutex lock; /* protects the TypeC port mode */ 54 54 - intel_wakeref_t lock_wakeref; 54 54 + struct ref_tracker *lock_wakeref; 55 55 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 56 56 enum intel_display_power_domain lock_power_domain; 57 57 #endif ··· 182 182 intel_display_power_legacy_aux_domain(display, dig_port->aux_ch); 183 183 } 184 184 185 185 - static intel_wakeref_t 185 185 + static struct ref_tracker * 186 186 __tc_cold_block(struct intel_tc_port *tc, enum intel_display_power_domain *domain) 187 187 { 188 188 struct intel_display *display = to_intel_display(tc->dig_port); ··· 192 192 return intel_display_power_get(display, *domain); 193 193 } 194 194 195 195 - static intel_wakeref_t 195 195 + static struct ref_tracker * 196 196 tc_cold_block(struct intel_tc_port *tc) 197 197 { 198 198 enum intel_display_power_domain domain; 199 199 - intel_wakeref_t wakeref; 199 199 + struct ref_tracker *wakeref; 200 200 201 201 wakeref = __tc_cold_block(tc, &domain); 202 202 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) ··· 207 207 208 208 static void 209 209 __tc_cold_unblock(struct intel_tc_port *tc, enum intel_display_power_domain domain, 210 210 - intel_wakeref_t wakeref) 210 210 + struct ref_tracker *wakeref) 211 211 { 212 212 struct intel_display *display = to_intel_display(tc->dig_port); 213 213 ··· 215 215 } 216 216 217 217 static void 218 218 - tc_cold_unblock(struct intel_tc_port *tc, intel_wakeref_t wakeref) 218 218 + tc_cold_unblock(struct intel_tc_port *tc, struct ref_tracker *wakeref) 219 219 { 220 220 struct intel_display __maybe_unused *display = to_intel_display(tc->dig_port); 221 221 enum intel_display_power_domain domain = tc_phy_cold_off_domain(tc); ··· 269 269 static u32 get_lane_mask(struct intel_tc_port *tc) 270 270 { 271 271 struct intel_display *display = to_intel_display(tc->dig_port); 272 272 - intel_wakeref_t wakeref; 273 272 u32 lane_mask; 274 273 275 275 - with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) 274 274 + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) 276 275 lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia)); 277 276 278 277 drm_WARN_ON(display->drm, lane_mask == 0xffffffff); ··· 295 296 struct intel_display *display = to_intel_display(tc->dig_port); 296 297 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); 297 298 enum intel_tc_pin_assignment pin_assignment; 298 298 - intel_wakeref_t wakeref; 299 299 i915_reg_t reg; 300 300 u32 mask; 301 301 u32 val; ··· 310 312 mask = DP_PIN_ASSIGNMENT_MASK(tc->phy_fia_idx); 311 313 } 312 314 313 313 - with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) 315 315 + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) 314 316 val = intel_de_read(display, reg); 315 317 316 318 drm_WARN_ON(display->drm, val == 0xffffffff); ··· 525 527 struct intel_display *display = to_intel_display(tc->dig_port); 526 528 struct intel_digital_port *dig_port = tc->dig_port; 527 529 u32 isr_bit = display->hotplug.pch_hpd[dig_port->base.hpd_pin]; 528 528 - intel_wakeref_t wakeref; 529 530 u32 fia_isr; 530 531 u32 pch_isr; 531 532 u32 mask = 0; 532 533 533 533 - with_intel_display_power(display, tc_phy_cold_off_domain(tc), wakeref) { 534 534 + with_intel_display_power(display, tc_phy_cold_off_domain(tc)) { 534 535 fia_isr = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia)); 535 536 pch_isr = intel_de_read(display, SDEISR); 536 537 } ··· 625 628 static void icl_tc_phy_get_hw_state(struct intel_tc_port *tc) 626 629 { 627 630 enum intel_display_power_domain domain; 628 628 - intel_wakeref_t tc_cold_wref; 631 631 + struct ref_tracker *tc_cold_wref; 629 632 630 633 tc_cold_wref = __tc_cold_block(tc, &domain); 631 634 ··· 771 774 static void tgl_tc_phy_init(struct intel_tc_port *tc) 772 775 { 773 776 struct intel_display *display = to_intel_display(tc->dig_port); 774 774 - intel_wakeref_t wakeref; 775 777 u32 val; 776 778 777 777 - with_intel_display_power(display, tc_phy_cold_off_domain(tc), wakeref) 779 779 + with_intel_display_power(display, tc_phy_cold_off_domain(tc)) 778 780 val = intel_de_read(display, PORT_TX_DFLEXDPSP(FIA1)); 779 781 780 782 drm_WARN_ON(display->drm, val == 0xffffffff); ··· 815 819 enum hpd_pin hpd_pin = dig_port->base.hpd_pin; 816 820 u32 cpu_isr_bits = display->hotplug.hpd[hpd_pin]; 817 821 u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin]; 818 818 - intel_wakeref_t wakeref; 819 822 u32 cpu_isr; 820 823 u32 pch_isr; 821 824 u32 mask = 0; 822 825 823 823 - with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { 826 826 + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) { 824 827 cpu_isr = intel_de_read(display, GEN11_DE_HPD_ISR); 825 828 pch_isr = intel_de_read(display, SDEISR); 826 829 } ··· 892 897 struct intel_display *display = to_intel_display(tc->dig_port); 893 898 enum intel_display_power_domain port_power_domain = 894 899 tc_port_power_domain(tc); 895 895 - intel_wakeref_t port_wakeref; 900 900 + struct ref_tracker *port_wakeref; 896 901 897 902 port_wakeref = intel_display_power_get(display, port_power_domain); 898 903 ··· 911 916 struct intel_display *display = to_intel_display(tc->dig_port); 912 917 enum intel_display_power_domain port_power_domain = 913 918 tc_port_power_domain(tc); 914 914 - intel_wakeref_t port_wakeref; 919 919 + struct ref_tracker *port_wakeref; 915 920 916 921 if (tc->mode == TC_PORT_TBT_ALT) { 917 922 tc->lock_wakeref = tc_cold_block(tc); ··· 963 968 struct intel_display *display = to_intel_display(tc->dig_port); 964 969 enum intel_display_power_domain port_power_domain = 965 970 tc_port_power_domain(tc); 966 966 - intel_wakeref_t port_wakeref; 971 971 + struct ref_tracker *port_wakeref; 967 972 968 973 port_wakeref = intel_display_power_get(display, port_power_domain); 969 974 ··· 1010 1015 enum hpd_pin hpd_pin = dig_port->base.hpd_pin; 1011 1016 u32 pica_isr_bits = display->hotplug.hpd[hpd_pin]; 1012 1017 u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin]; 1013 1013 - intel_wakeref_t wakeref; 1014 1018 u32 pica_isr; 1015 1019 u32 pch_isr; 1016 1020 u32 mask = 0; 1017 1021 1018 1018 - with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { 1022 1022 + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) { 1019 1023 pica_isr = intel_de_read(display, PICAINTERRUPT_ISR); 1020 1024 pch_isr = intel_de_read(display, SDEISR); 1021 1025 } ··· 1169 1175 static void xelpdp_tc_phy_get_hw_state(struct intel_tc_port *tc) 1170 1176 { 1171 1177 struct intel_display *display = to_intel_display(tc->dig_port); 1172 1172 - intel_wakeref_t tc_cold_wref; 1178 1178 + struct ref_tracker *tc_cold_wref; 1173 1179 enum intel_display_power_domain domain; 1174 1180 1175 1181 tc_cold_wref = __tc_cold_block(tc, &domain);

+2 -1

drivers/gpu/drm/i915/display/intel_vbt_defs.h

reviewed

··· 554 554 u8 dvo_function; 555 555 u8 dp_usb_type_c:1; /* 195+ */ 556 556 u8 tbt:1; /* 209+ */ 557 557 - u8 flags2_reserved:2; /* 195+ */ 557 557 + u8 dedicated_external:1; /* 264+ */ 558 558 + u8 dyn_port_over_tc:1; /* 264+ */ 558 559 u8 dp_port_trace_length:4; /* 209+ */ 559 560 u8 dp_gpio_index; /* 195+ */ 560 561 u16 dp_gpio_pin_num; /* 195+ */

+1 -1

drivers/gpu/drm/i915/display/intel_vdsc.c

reviewed

··· 999 999 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1000 1000 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 1001 1001 enum intel_display_power_domain power_domain; 1002 1002 - intel_wakeref_t wakeref; 1002 1002 + struct ref_tracker *wakeref; 1003 1003 u32 dss_ctl1, dss_ctl2; 1004 1004 1005 1005 if (!intel_dsc_source_support(crtc_state))

+42 -2

drivers/gpu/drm/i915/display/intel_vga.c

reviewed

··· 9 9 10 10 #include <drm/drm_device.h> 11 11 #include <drm/drm_print.h> 12 12 + #include <drm/intel/i915_drm.h> 12 13 #include <video/vga.h> 13 13 - 14 14 - #include "soc/intel_gmch.h" 15 14 16 15 #include "intel_de.h" 17 16 #include "intel_display.h" 17 17 + #include "intel_display_types.h" 18 18 #include "intel_vga.h" 19 19 #include "intel_vga_regs.h" 20 20 ··· 93 93 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); 94 94 outb(inb(VGA_MIS_R), VGA_MIS_W); 95 95 vga_put(pdev, VGA_RSRC_LEGACY_IO); 96 96 + } 97 97 + 98 98 + static int intel_gmch_vga_set_state(struct intel_display *display, bool enable_decode) 99 99 + { 100 100 + struct pci_dev *pdev = to_pci_dev(display->drm->dev); 101 101 + unsigned int reg = DISPLAY_VER(display) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; 102 102 + u16 gmch_ctrl; 103 103 + 104 104 + if (pci_bus_read_config_word(pdev->bus, PCI_DEVFN(0, 0), reg, &gmch_ctrl)) { 105 105 + drm_err(display->drm, "failed to read control word\n"); 106 106 + return -EIO; 107 107 + } 108 108 + 109 109 + if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode) 110 110 + return 0; 111 111 + 112 112 + if (enable_decode) 113 113 + gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 114 114 + else 115 115 + gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 116 116 + 117 117 + if (pci_bus_write_config_word(pdev->bus, PCI_DEVFN(0, 0), reg, gmch_ctrl)) { 118 118 + drm_err(display->drm, "failed to write control word\n"); 119 119 + return -EIO; 120 120 + } 121 121 + 122 122 + return 0; 123 123 + } 124 124 + 125 125 + static unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode) 126 126 + { 127 127 + struct intel_display *display = to_intel_display(pdev); 128 128 + 129 129 + intel_gmch_vga_set_state(display, enable_decode); 130 130 + 131 131 + if (enable_decode) 132 132 + return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 133 133 + VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 134 134 + else 135 135 + return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 96 136 } 97 137 98 138 int intel_vga_register(struct intel_display *display)

+6 -13

drivers/gpu/drm/i915/display/skl_universal_plane.c

reviewed

··· 9 9 #include <drm/drm_fourcc.h> 10 10 #include <drm/drm_print.h> 11 11 12 12 - #include "pxp/intel_pxp.h" 13 12 #include "intel_bo.h" 14 13 #include "intel_color.h" 15 14 #include "intel_color_pipeline.h" ··· 21 22 #include "intel_fb.h" 22 23 #include "intel_fbc.h" 23 24 #include "intel_frontbuffer.h" 24 24 - #include "intel_panic.h" 25 25 + #include "intel_parent.h" 25 26 #include "intel_plane.h" 26 27 #include "intel_psr.h" 27 28 #include "intel_psr_regs.h" ··· 596 597 * Figure out what's going on here... 597 598 */ 598 599 if (display->platform.alderlake_p && 599 599 - intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) 600 600 + intel_plane_can_async_flip(plane, fb->format, fb->modifier)) 600 601 return mult * 16 * 1024; 601 602 602 603 switch (fb->modifier) { ··· 940 941 struct intel_display *display = to_intel_display(plane); 941 942 enum intel_display_power_domain power_domain; 942 943 enum plane_id plane_id = plane->id; 943 943 - intel_wakeref_t wakeref; 944 944 + struct ref_tracker *wakeref; 944 945 bool ret; 945 946 946 947 power_domain = POWER_DOMAIN_PIPE(plane->pipe); ··· 1602 1603 } 1603 1604 1604 1605 /* FLAT CCS doesn't need to program AUX_DIST */ 1605 1605 - if (HAS_AUX_CCS(display)) 1606 1606 + if (HAS_AUX_DIST(display)) 1606 1607 intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id), 1607 1608 skl_plane_aux_dist(plane_state, color_plane)); 1608 1609 ··· 2307 2308 if (DISPLAY_VER(display) < 11) 2308 2309 return; 2309 2310 2310 2310 - plane_state->decrypt = intel_pxp_key_check(obj, false) == 0; 2311 2311 + plane_state->decrypt = intel_bo_key_check(obj) == 0; 2311 2312 plane_state->force_black = intel_bo_is_protected(obj) && 2312 2313 !plane_state->decrypt; 2313 2314 } ··· 2461 2462 enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe); 2462 2463 2463 2464 if (skl_plane_has_fbc(display, fbc_id, plane_id)) 2464 2464 - return display->fbc[fbc_id]; 2465 2465 + return display->fbc.instances[fbc_id]; 2465 2466 else 2466 2467 return NULL; 2467 2468 } ··· 2971 2972 caps = glk_plane_caps(display, pipe, plane_id); 2972 2973 else 2973 2974 caps = skl_plane_caps(display, pipe, plane_id); 2974 2974 - 2975 2975 - /* FIXME: xe has problems with AUX */ 2976 2976 - if (!IS_ENABLED(I915) && HAS_AUX_CCS(display)) 2977 2977 - caps &= ~(INTEL_PLANE_CAP_CCS_RC | 2978 2978 - INTEL_PLANE_CAP_CCS_RC_CC | 2979 2979 - INTEL_PLANE_CAP_CCS_MC); 2980 2975 2981 2976 modifiers = intel_fb_plane_get_modifiers(display, caps); 2982 2977

+4 -4

drivers/gpu/drm/i915/display/skl_watermark.c

reviewed

··· 8 8 #include <drm/drm_blend.h> 9 9 #include <drm/drm_print.h> 10 10 11 11 - #include "soc/intel_dram.h" 12 11 #include "i915_reg.h" 13 12 #include "i9xx_wm.h" 14 13 #include "intel_atomic.h" ··· 22 23 #include "intel_display_rpm.h" 23 24 #include "intel_display_types.h" 24 25 #include "intel_display_utils.h" 26 26 + #include "intel_dram.h" 25 27 #include "intel_fb.h" 26 28 #include "intel_fixed.h" 27 29 #include "intel_flipq.h" ··· 718 718 struct intel_display *display = to_intel_display(crtc); 719 719 enum intel_display_power_domain power_domain; 720 720 enum pipe pipe = crtc->pipe; 721 721 - intel_wakeref_t wakeref; 721 721 + struct ref_tracker *wakeref; 722 722 enum plane_id plane_id; 723 723 724 724 power_domain = POWER_DOMAIN_PIPE(pipe); ··· 3125 3125 if (display->platform.kabylake || 3126 3126 display->platform.coffeelake || 3127 3127 display->platform.cometlake) { 3128 3128 - const struct dram_info *dram_info = intel_dram_info(display->drm); 3128 3128 + const struct dram_info *dram_info = intel_dram_info(display); 3129 3129 3130 3130 return dram_info->symmetric_memory; 3131 3131 } ··· 3169 3169 3170 3170 static bool need_16gb_dimm_wa(struct intel_display *display) 3171 3171 { 3172 3172 - const struct dram_info *dram_info = intel_dram_info(display->drm); 3172 3172 + const struct dram_info *dram_info = intel_dram_info(display); 3173 3173 3174 3174 return (display->platform.skylake || display->platform.kabylake || 3175 3175 display->platform.coffeelake || display->platform.cometlake ||

+1 -1

drivers/gpu/drm/i915/display/vlv_dsi.c

reviewed

··· 936 936 { 937 937 struct intel_display *display = to_intel_display(encoder); 938 938 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 939 939 - intel_wakeref_t wakeref; 939 939 + struct ref_tracker *wakeref; 940 940 enum port port; 941 941 bool active = false; 942 942

+34 -18

drivers/gpu/drm/i915/gem/i915_gem_stolen.c

reviewed

··· 8 8 9 9 #include <drm/drm_mm.h> 10 10 #include <drm/drm_print.h> 11 11 + #include <drm/intel/display_parent_interface.h> 11 12 #include <drm/intel/i915_drm.h> 12 13 13 14 #include "gem/i915_gem_lmem.h" ··· 65 64 return ret; 66 65 } 67 66 68 68 - int i915_gem_stolen_insert_node_in_range(struct intel_stolen_node *node, u64 size, 69 69 - unsigned int alignment, u64 start, u64 end) 67 67 + static int i915_gem_stolen_insert_node_in_range(struct intel_stolen_node *node, u64 size, 68 68 + unsigned int alignment, u64 start, u64 end) 70 69 { 71 70 return __i915_gem_stolen_insert_node_in_range(node->i915, &node->node, 72 71 size, alignment, ··· 83 82 U64_MAX); 84 83 } 85 84 86 86 - int i915_gem_stolen_insert_node(struct intel_stolen_node *node, u64 size, 87 87 - unsigned int alignment) 85 85 + static int i915_gem_stolen_insert_node(struct intel_stolen_node *node, u64 size, 86 86 + unsigned int alignment) 88 87 { 89 88 return __i915_gem_stolen_insert_node(node->i915, &node->node, size, alignment); 90 89 } ··· 97 96 mutex_unlock(&i915->mm.stolen_lock); 98 97 } 99 98 100 100 - void i915_gem_stolen_remove_node(struct intel_stolen_node *node) 99 99 + static void i915_gem_stolen_remove_node(struct intel_stolen_node *node) 101 100 { 102 101 __i915_gem_stolen_remove_node(node->i915, &node->node); 103 102 } ··· 1026 1025 return obj->ops == &i915_gem_object_stolen_ops; 1027 1026 } 1028 1027 1029 1029 - bool i915_gem_stolen_initialized(struct drm_device *drm) 1028 1028 + static bool i915_gem_stolen_initialized(struct drm_device *drm) 1030 1029 { 1031 1030 struct drm_i915_private *i915 = to_i915(drm); 1032 1031 1033 1032 return drm_mm_initialized(&i915->mm.stolen); 1034 1033 } 1035 1034 1036 1036 - u64 i915_gem_stolen_area_address(struct drm_device *drm) 1035 1035 + static u64 i915_gem_stolen_area_address(struct drm_device *drm) 1037 1036 { 1038 1037 struct drm_i915_private *i915 = to_i915(drm); 1039 1038 1040 1039 return i915->dsm.stolen.start; 1041 1040 } 1042 1041 1043 1043 - u64 i915_gem_stolen_area_size(struct drm_device *drm) 1042 1042 + static u64 i915_gem_stolen_area_size(struct drm_device *drm) 1044 1043 { 1045 1044 struct drm_i915_private *i915 = to_i915(drm); 1046 1045 1047 1046 return resource_size(&i915->dsm.stolen); 1048 1047 } 1049 1048 1050 1050 - u64 i915_gem_stolen_node_address(const struct intel_stolen_node *node) 1049 1049 + static u64 i915_gem_stolen_node_offset(const struct intel_stolen_node *node) 1050 1050 + { 1051 1051 + return node->node.start; 1052 1052 + } 1053 1053 + 1054 1054 + static u64 i915_gem_stolen_node_address(const struct intel_stolen_node *node) 1051 1055 { 1052 1056 struct drm_i915_private *i915 = node->i915; 1053 1057 1054 1058 return i915->dsm.stolen.start + i915_gem_stolen_node_offset(node); 1055 1059 } 1056 1060 1057 1057 - bool i915_gem_stolen_node_allocated(const struct intel_stolen_node *node) 1061 1061 + static bool i915_gem_stolen_node_allocated(const struct intel_stolen_node *node) 1058 1062 { 1059 1063 return drm_mm_node_allocated(&node->node); 1060 1064 } 1061 1065 1062 1062 - u64 i915_gem_stolen_node_offset(const struct intel_stolen_node *node) 1063 1063 - { 1064 1064 - return node->node.start; 1065 1065 - } 1066 1066 - 1067 1067 - u64 i915_gem_stolen_node_size(const struct intel_stolen_node *node) 1066 1066 + static u64 i915_gem_stolen_node_size(const struct intel_stolen_node *node) 1068 1067 { 1069 1068 return node->node.size; 1070 1069 } 1071 1070 1072 1072 - struct intel_stolen_node *i915_gem_stolen_node_alloc(struct drm_device *drm) 1071 1071 + static struct intel_stolen_node *i915_gem_stolen_node_alloc(struct drm_device *drm) 1073 1072 { 1074 1073 struct drm_i915_private *i915 = to_i915(drm); 1075 1074 struct intel_stolen_node *node; ··· 1083 1082 return node; 1084 1083 } 1085 1084 1086 1086 - void i915_gem_stolen_node_free(const struct intel_stolen_node *node) 1085 1085 + static void i915_gem_stolen_node_free(const struct intel_stolen_node *node) 1087 1086 { 1088 1087 kfree(node); 1089 1088 } 1089 1089 + 1090 1090 + const struct intel_display_stolen_interface i915_display_stolen_interface = { 1091 1091 + .insert_node_in_range = i915_gem_stolen_insert_node_in_range, 1092 1092 + .insert_node = i915_gem_stolen_insert_node, 1093 1093 + .remove_node = i915_gem_stolen_remove_node, 1094 1094 + .initialized = i915_gem_stolen_initialized, 1095 1095 + .node_allocated = i915_gem_stolen_node_allocated, 1096 1096 + .node_offset = i915_gem_stolen_node_offset, 1097 1097 + .area_address = i915_gem_stolen_area_address, 1098 1098 + .area_size = i915_gem_stolen_area_size, 1099 1099 + .node_address = i915_gem_stolen_node_address, 1100 1100 + .node_size = i915_gem_stolen_node_size, 1101 1101 + .node_alloc = i915_gem_stolen_node_alloc, 1102 1102 + .node_free = i915_gem_stolen_node_free, 1103 1103 + };

+1 -20

drivers/gpu/drm/i915/gem/i915_gem_stolen.h

reviewed

··· 8 8 9 9 #include <linux/types.h> 10 10 11 11 - struct drm_device; 12 11 struct drm_i915_gem_object; 13 12 struct drm_i915_private; 14 14 - struct intel_stolen_node; 15 13 16 16 - int i915_gem_stolen_insert_node(struct intel_stolen_node *node, u64 size, 17 17 - unsigned alignment); 18 18 - int i915_gem_stolen_insert_node_in_range(struct intel_stolen_node *node, u64 size, 19 19 - unsigned alignment, u64 start, 20 20 - u64 end); 21 21 - void i915_gem_stolen_remove_node(struct intel_stolen_node *node); 22 14 struct intel_memory_region * 23 15 i915_gem_stolen_smem_setup(struct drm_i915_private *i915, u16 type, 24 16 u16 instance); ··· 26 34 27 35 #define I915_GEM_STOLEN_BIAS SZ_128K 28 36 29 29 - bool i915_gem_stolen_initialized(struct drm_device *drm); 30 30 - u64 i915_gem_stolen_area_address(struct drm_device *drm); 31 31 - u64 i915_gem_stolen_area_size(struct drm_device *drm); 32 32 - 33 33 - u64 i915_gem_stolen_node_address(const struct intel_stolen_node *node); 34 34 - 35 35 - bool i915_gem_stolen_node_allocated(const struct intel_stolen_node *node); 36 36 - u64 i915_gem_stolen_node_offset(const struct intel_stolen_node *node); 37 37 - u64 i915_gem_stolen_node_size(const struct intel_stolen_node *node); 38 38 - 39 39 - struct intel_stolen_node *i915_gem_stolen_node_alloc(struct drm_device *drm); 40 40 - void i915_gem_stolen_node_free(const struct intel_stolen_node *node); 37 37 + extern const struct intel_display_stolen_interface i915_display_stolen_interface; 41 38 42 39 #endif /* __I915_GEM_STOLEN_H__ */

+1 -3

drivers/gpu/drm/i915/gt/intel_engine_cs.c

reviewed

··· 963 963 drm_WARN_ON(&i915->drm, engine_mask & 964 964 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); 965 965 966 966 - if (i915_inject_probe_failure(i915)) 967 967 - return -ENODEV; 968 968 - 969 966 for (class = 0; class < MAX_ENGINE_CLASS + 1; ++class) { 970 967 setup_logical_ids(gt, logical_ids, class); 971 968 ··· 1004 1007 intel_engines_free(gt); 1005 1008 return err; 1006 1009 } 1010 1010 + ALLOW_ERROR_INJECTION(intel_engines_init_mmio, ERRNO); 1007 1011 1008 1012 void intel_engine_init_execlists(struct intel_engine_cs *engine) 1009 1013 {

+1 -8

drivers/gpu/drm/i915/gt/intel_gt.c

reviewed

··· 686 686 { 687 687 int err; 688 688 689 689 - err = i915_inject_probe_error(gt->i915, -ENODEV); 690 690 - if (err) 691 691 - return err; 692 692 - 693 689 intel_gt_init_workarounds(gt); 694 690 695 691 /* ··· 736 740 if (err) 737 741 goto err_gt; 738 742 739 739 - err = i915_inject_probe_error(gt->i915, -EIO); 740 740 - if (err) 741 741 - goto err_gt; 742 742 - 743 743 intel_uc_init_late(&gt->uc); 744 744 745 745 intel_migrate_init(&gt->migrate, gt); ··· 758 766 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); 759 767 return err; 760 768 } 769 769 + ALLOW_ERROR_INJECTION(intel_gt_init, ERRNO); 761 770 762 771 void intel_gt_driver_remove(struct intel_gt *gt) 763 772 {

+2 -2

drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c

reviewed

··· 4 4 */ 5 5 6 6 #include "i915_drv.h" 7 7 + #include "i915_freq.h" 7 8 #include "i915_reg.h" 8 9 #include "intel_gt.h" 9 10 #include "intel_gt_clock_utils.h" 10 11 #include "intel_gt_print.h" 11 12 #include "intel_gt_regs.h" 12 12 - #include "soc/intel_dram.h" 13 13 14 14 static u32 read_reference_ts_freq(struct intel_uncore *uncore) 15 15 { ··· 148 148 * 149 149 * Testing on actual hardware has shown there is no /16. 150 150 */ 151 151 - return DIV_ROUND_CLOSEST(intel_fsb_freq(uncore->i915), 4) * 1000; 151 151 + return DIV_ROUND_CLOSEST(i9xx_fsb_freq(uncore->i915), 4) * 1000; 152 152 } 153 153 154 154 static u32 read_clock_frequency(struct intel_uncore *uncore)

+1 -4

drivers/gpu/drm/i915/gt/intel_gt_print.h

reviewed

··· 36 36 37 37 #define gt_probe_error(_gt, _fmt, ...) \ 38 38 do { \ 39 39 - if (i915_error_injected()) \ 40 40 - gt_dbg(_gt, _fmt, ##__VA_ARGS__); \ 41 41 - else \ 42 42 - gt_err(_gt, _fmt, ##__VA_ARGS__); \ 39 39 + gt_err(_gt, _fmt, ##__VA_ARGS__); \ 43 40 } while (0) 44 41 45 42 #define gt_WARN(_gt, _condition, _fmt, ...) \

-4

drivers/gpu/drm/i915/gt/intel_lrc.c

reviewed

··· 1911 1911 __i915_gem_object_flush_map(wa_ctx->vma->obj, 0, batch_ptr - batch); 1912 1912 __i915_gem_object_release_map(wa_ctx->vma->obj); 1913 1913 1914 1914 - /* Verify that we can handle failure to setup the wa_ctx */ 1915 1915 - if (!err) 1916 1916 - err = i915_inject_probe_error(engine->i915, -ENODEV); 1917 1917 - 1918 1914 err_unpin: 1919 1915 if (err) 1920 1916 i915_vma_unpin(wa_ctx->vma);

+37 -3

drivers/gpu/drm/i915/gt/intel_rps.c

reviewed

··· 6 6 #include <linux/string_helpers.h> 7 7 8 8 #include <drm/intel/i915_drm.h> 9 9 + #include <drm/intel/display_parent_interface.h> 9 10 10 11 #include "display/intel_display_rps.h" 11 12 #include "display/vlv_clock.h" 12 12 - #include "soc/intel_dram.h" 13 13 14 14 #include "i915_drv.h" 15 15 + #include "i915_freq.h" 15 16 #include "i915_irq.h" 16 17 #include "i915_reg.h" 17 18 #include "i915_wait_util.h" ··· 285 284 u32 rgvmodectl; 286 285 int c_m, i; 287 286 288 288 - fsb_freq = intel_fsb_freq(i915); 289 289 - mem_freq = intel_mem_freq(i915); 287 287 + fsb_freq = ilk_fsb_freq(i915); 288 288 + mem_freq = ilk_mem_freq(i915); 290 289 291 290 if (fsb_freq <= 3200000) 292 291 c_m = 0; ··· 2914 2913 return ret; 2915 2914 } 2916 2915 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); 2916 2916 + 2917 2917 + static void boost_if_not_started(struct dma_fence *fence) 2918 2918 + { 2919 2919 + struct i915_request *rq; 2920 2920 + 2921 2921 + if (!dma_fence_is_i915(fence)) 2922 2922 + return; 2923 2923 + 2924 2924 + rq = to_request(fence); 2925 2925 + 2926 2926 + if (!i915_request_started(rq)) 2927 2927 + intel_rps_boost(rq); 2928 2928 + } 2929 2929 + 2930 2930 + static void mark_interactive(struct drm_device *drm, bool interactive) 2931 2931 + { 2932 2932 + struct drm_i915_private *i915 = to_i915(drm); 2933 2933 + 2934 2934 + intel_rps_mark_interactive(&to_gt(i915)->rps, interactive); 2935 2935 + } 2936 2936 + 2937 2937 + static void ilk_irq_handler(struct drm_device *drm) 2938 2938 + { 2939 2939 + struct drm_i915_private *i915 = to_i915(drm); 2940 2940 + 2941 2941 + gen5_rps_irq_handler(&to_gt(i915)->rps); 2942 2942 + } 2943 2943 + 2944 2944 + const struct intel_display_rps_interface i915_display_rps_interface = { 2945 2945 + .boost_if_not_started = boost_if_not_started, 2946 2946 + .mark_interactive = mark_interactive, 2947 2947 + .ilk_irq_handler = ilk_irq_handler, 2948 2948 + }; 2917 2949 2918 2950 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2919 2951 #include "selftest_rps.c"

+2

drivers/gpu/drm/i915/gt/intel_rps.h

reviewed

··· 128 128 clear_bit(INTEL_RPS_TIMER, &rps->flags); 129 129 } 130 130 131 131 + extern const struct intel_display_rps_interface i915_display_rps_interface; 132 132 + 131 133 #endif /* INTEL_RPS_H */

-3

drivers/gpu/drm/i915/gt/intel_wopcm.c

reviewed

··· 253 253 GEM_BUG_ON(huc_fw_size >= wopcm_size); 254 254 GEM_BUG_ON(ctx_rsvd + WOPCM_RESERVED_SIZE >= wopcm_size); 255 255 256 256 - if (i915_inject_probe_failure(i915)) 257 257 - return; 258 258 - 259 256 if (__wopcm_regs_locked(gt->uncore, &guc_wopcm_base, &guc_wopcm_size)) { 260 257 drm_dbg(&i915->drm, "GuC WOPCM is already locked [%uK, %uK)\n", 261 258 guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);

+1 -7

drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

reviewed

··· 266 266 u32 *cmds; 267 267 int err; 268 268 269 269 - err = i915_inject_probe_error(guc_to_i915(guc), -ENXIO); 270 270 - if (err) 271 271 - return err; 272 272 - 273 269 GEM_BUG_ON(ct->vma); 274 270 275 271 blob_size = 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE + CTB_G2H_BUFFER_SIZE; ··· 302 306 303 307 return 0; 304 308 } 309 309 + ALLOW_ERROR_INJECTION(intel_guc_ct_init, ERRNO); 305 310 306 311 /** 307 312 * intel_guc_ct_fini - Fini buffer-based communication ··· 1389 1392 struct intel_guc *guc = ct_to_guc(ct); 1390 1393 1391 1394 if (ct->dead_ct_reported) 1392 1392 - return; 1393 1393 - 1394 1394 - if (i915_error_injected()) 1395 1395 return; 1396 1396 1397 1397 ct->dead_ct_reported = true;

-4

drivers/gpu/drm/i915/gt/uc/intel_huc.c

reviewed

··· 541 541 if (intel_huc_is_authenticated(huc, type)) 542 542 return -EEXIST; 543 543 544 544 - ret = i915_inject_probe_error(gt->i915, -ENXIO); 545 545 - if (ret) 546 546 - goto fail; 547 547 - 548 544 switch (type) { 549 545 case INTEL_HUC_AUTH_BY_GUC: 550 546 ret = intel_guc_auth_huc(guc, intel_guc_ggtt_offset(guc, huc->fw.rsa_data));

+1 -16

drivers/gpu/drm/i915/gt/uc/intel_uc.c

reviewed

··· 60 60 int ret; 61 61 u32 guc_status; 62 62 63 63 - ret = i915_inject_probe_error(gt->i915, -ENXIO); 64 64 - if (ret) 65 65 - return ret; 66 66 - 67 63 ret = intel_reset_guc(gt); 68 64 if (ret) { 69 65 gt_err(gt, "Failed to reset GuC, ret = %d\n", ret); ··· 216 220 static int guc_enable_communication(struct intel_guc *guc) 217 221 { 218 222 struct intel_gt *gt = guc_to_gt(guc); 219 219 - struct drm_i915_private *i915 = gt->i915; 220 223 int ret; 221 224 222 225 GEM_BUG_ON(intel_guc_ct_enabled(&guc->ct)); 223 223 - 224 224 - ret = i915_inject_probe_error(i915, -ENXIO); 225 225 - if (ret) 226 226 - return ret; 227 226 228 227 ret = intel_guc_ct_enable(&guc->ct); 229 228 if (ret) ··· 314 323 if (!intel_uc_uses_guc(uc)) 315 324 return 0; 316 325 317 317 - if (i915_inject_probe_failure(uc_to_gt(uc)->i915)) 318 318 - return -ENOMEM; 319 319 - 320 326 ret = intel_guc_init(guc); 321 327 if (ret) 322 328 return ret; ··· 326 338 327 339 return 0; 328 340 } 341 341 + ALLOW_ERROR_INJECTION(__uc_init, ERRNO); 329 342 330 343 static void __uc_fini(struct intel_uc *uc) 331 344 { ··· 369 380 GEM_BUG_ON(base & ~GUC_WOPCM_OFFSET_MASK); 370 381 GEM_BUG_ON(!(size & GUC_WOPCM_SIZE_MASK)); 371 382 GEM_BUG_ON(size & ~GUC_WOPCM_SIZE_MASK); 372 372 - 373 373 - err = i915_inject_probe_error(gt->i915, -ENXIO); 374 374 - if (err) 375 375 - return err; 376 383 377 384 mask = GUC_WOPCM_SIZE_MASK | GUC_WOPCM_SIZE_LOCKED; 378 385 err = intel_uncore_write_and_verify(uncore, GUC_WOPCM_SIZE, size, mask,

+2 -58

drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c

reviewed

··· 542 542 INTEL_UC_FIRMWARE_NOT_SUPPORTED); 543 543 } 544 544 545 545 - static void __force_fw_fetch_failures(struct intel_uc_fw *uc_fw, int e) 546 546 - { 547 547 - struct drm_i915_private *i915 = __uc_fw_to_gt(uc_fw)->i915; 548 548 - bool user = e == -EINVAL; 549 549 - 550 550 - if (i915_inject_probe_error(i915, e)) { 551 551 - /* non-existing blob */ 552 552 - uc_fw->file_selected.path = "<invalid>"; 553 553 - uc_fw->user_overridden = user; 554 554 - } else if (i915_inject_probe_error(i915, e)) { 555 555 - /* require next major version */ 556 556 - uc_fw->file_wanted.ver.major += 1; 557 557 - uc_fw->file_wanted.ver.minor = 0; 558 558 - uc_fw->user_overridden = user; 559 559 - } else if (i915_inject_probe_error(i915, e)) { 560 560 - /* require next minor version */ 561 561 - uc_fw->file_wanted.ver.minor += 1; 562 562 - uc_fw->user_overridden = user; 563 563 - } else if (uc_fw->file_wanted.ver.major && 564 564 - i915_inject_probe_error(i915, e)) { 565 565 - /* require prev major version */ 566 566 - uc_fw->file_wanted.ver.major -= 1; 567 567 - uc_fw->file_wanted.ver.minor = 0; 568 568 - uc_fw->user_overridden = user; 569 569 - } else if (uc_fw->file_wanted.ver.minor && 570 570 - i915_inject_probe_error(i915, e)) { 571 571 - /* require prev minor version - hey, this should work! */ 572 572 - uc_fw->file_wanted.ver.minor -= 1; 573 573 - uc_fw->user_overridden = user; 574 574 - } else if (user && i915_inject_probe_error(i915, e)) { 575 575 - /* officially unsupported platform */ 576 576 - uc_fw->file_wanted.ver.major = 0; 577 577 - uc_fw->file_wanted.ver.minor = 0; 578 578 - uc_fw->user_overridden = true; 579 579 - } 580 580 - } 581 581 - 582 545 static void uc_unpack_css_version(struct intel_uc_fw_ver *ver, u32 css_value) 583 546 { 584 547 /* Get version numbers from the CSS header */ ··· 729 766 return -EINVAL; 730 767 } 731 768 732 732 - return i915_inject_probe_error(gt->i915, -EINVAL); 769 769 + return 0; 733 770 } 734 771 735 772 static int check_fw_header(struct intel_gt *gt, ··· 867 904 868 905 GEM_BUG_ON(!gt->wopcm.size); 869 906 GEM_BUG_ON(!intel_uc_fw_is_enabled(uc_fw)); 870 870 - 871 871 - err = i915_inject_probe_error(i915, -ENXIO); 872 872 - if (err) 873 873 - goto fail; 874 874 - 875 875 - __force_fw_fetch_failures(uc_fw, -EINVAL); 876 876 - __force_fw_fetch_failures(uc_fw, -ESTALE); 877 907 878 908 err = try_firmware_load(uc_fw, &fw); 879 909 memcpy(&file_ideal, &uc_fw->file_wanted, sizeof(file_ideal)); ··· 1044 1088 u64 offset; 1045 1089 int ret; 1046 1090 1047 1047 - ret = i915_inject_probe_error(gt->i915, -ETIMEDOUT); 1048 1048 - if (ret) 1049 1049 - return ret; 1050 1050 - 1051 1091 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 1052 1092 1053 1093 /* Set the source address for the uCode */ ··· 1107 1155 */ 1108 1156 int intel_uc_fw_upload(struct intel_uc_fw *uc_fw, u32 dst_offset, u32 dma_flags) 1109 1157 { 1110 1110 - struct intel_gt *gt = __uc_fw_to_gt(uc_fw); 1111 1158 int err; 1112 1159 1113 1160 /* make sure the status was cleared the last time we reset the uc */ 1114 1161 GEM_BUG_ON(intel_uc_fw_is_loaded(uc_fw)); 1115 1115 - 1116 1116 - err = i915_inject_probe_error(gt->i915, -ENOEXEC); 1117 1117 - if (err) 1118 1118 - return err; 1119 1162 1120 1163 if (!intel_uc_fw_is_loadable(uc_fw)) 1121 1164 return -ENOEXEC; ··· 1144 1197 size_t copied; 1145 1198 void *vaddr; 1146 1199 int err; 1147 1147 - 1148 1148 - err = i915_inject_probe_error(gt->i915, -ENXIO); 1149 1149 - if (err) 1150 1150 - return err; 1151 1200 1152 1201 if (!uc_fw_need_rsa_in_memory(uc_fw)) 1153 1202 return 0; ··· 1186 1243 i915_vma_unpin_and_release(&vma, 0); 1187 1244 return err; 1188 1245 } 1246 1246 + ALLOW_ERROR_INJECTION(uc_fw_rsa_data_create, ERRNO); 1189 1247 1190 1248 static void uc_fw_rsa_data_destroy(struct intel_uc_fw *uc_fw) 1191 1249 {

+31

drivers/gpu/drm/i915/i915_display_pc8.c

reviewed

··· 1 1 + // SPDX-License-Identifier: MIT 2 2 + /* 3 3 + * Copyright 2025, Intel Corporation. 4 4 + */ 5 5 + 6 6 + #include <drm/drm_print.h> 7 7 + #include <drm/intel/display_parent_interface.h> 8 8 + 9 9 + #include "i915_display_pc8.h" 10 10 + #include "i915_drv.h" 11 11 + #include "intel_uncore.h" 12 12 + 13 13 + static void i915_display_pc8_block(struct drm_device *drm) 14 14 + { 15 15 + struct intel_uncore *uncore = &to_i915(drm)->uncore; 16 16 + 17 17 + /* to prevent PC8 state, just enable force_wake */ 18 18 + intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 19 19 + } 20 20 + 21 21 + static void i915_display_pc8_unblock(struct drm_device *drm) 22 22 + { 23 23 + struct intel_uncore *uncore = &to_i915(drm)->uncore; 24 24 + 25 25 + intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 26 26 + } 27 27 + 28 28 + const struct intel_display_pc8_interface i915_display_pc8_interface = { 29 29 + .block = i915_display_pc8_block, 30 30 + .unblock = i915_display_pc8_unblock, 31 31 + };

+9

drivers/gpu/drm/i915/i915_display_pc8.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #ifndef __I915_DISPLAY_PC8_H__ 5 5 + #define __I915_DISPLAY_PC8_H__ 6 6 + 7 7 + extern const struct intel_display_pc8_interface i915_display_pc8_interface; 8 8 + 9 9 + #endif /* __I915_DISPLAY_PC8_H__ */

+55 -20

drivers/gpu/drm/i915/i915_driver.c

reviewed

··· 59 59 #include "display/intel_dmc.h" 60 60 #include "display/intel_dp.h" 61 61 #include "display/intel_dpt.h" 62 62 + #include "display/intel_dram.h" 62 63 #include "display/intel_encoder.h" 63 64 #include "display/intel_fbdev.h" 64 65 #include "display/intel_gmbus.h" ··· 82 81 #include "gt/intel_gt_pm.h" 83 82 #include "gt/intel_gt_print.h" 84 83 #include "gt/intel_rc6.h" 84 84 + #include "gt/intel_rps.h" 85 85 86 86 #include "pxp/intel_pxp.h" 87 87 #include "pxp/intel_pxp_debugfs.h" 88 88 #include "pxp/intel_pxp_pm.h" 89 89 90 90 - #include "soc/intel_dram.h" 91 91 - #include "soc/intel_gmch.h" 92 92 - 93 90 #include "i915_debugfs.h" 91 91 + #include "i915_display_pc8.h" 94 92 #include "i915_driver.h" 95 93 #include "i915_drm_client.h" 96 94 #include "i915_drv.h" 95 95 + #include "i915_edram.h" 97 96 #include "i915_file_private.h" 98 97 #include "i915_getparam.h" 98 98 + #include "i915_gmch.h" 99 99 + #include "i915_hdcp_gsc.h" 99 100 #include "i915_hwmon.h" 100 101 #include "i915_ioc32.h" 101 102 #include "i915_ioctl.h" 102 103 #include "i915_irq.h" 103 104 #include "i915_memcpy.h" 105 105 + #include "i915_panic.h" 104 106 #include "i915_perf.h" 105 107 #include "i915_query.h" 106 108 #include "i915_reg.h" ··· 228 224 struct intel_display *display = dev_priv->display; 229 225 int ret = 0; 230 226 231 231 - if (i915_inject_probe_failure(dev_priv)) 232 232 - return -ENODEV; 233 233 - 234 227 intel_device_info_runtime_init_early(dev_priv); 235 228 236 229 intel_step_init(dev_priv); ··· 263 262 264 263 intel_irq_init(dev_priv); 265 264 intel_display_driver_early_probe(display); 266 266 - intel_clock_gating_hooks_init(dev_priv); 265 265 + intel_clock_gating_hooks_init(&dev_priv->drm); 267 266 268 267 intel_detect_preproduction_hw(dev_priv); 269 268 ··· 277 276 i915_workqueues_cleanup(dev_priv); 278 277 return ret; 279 278 } 279 279 + ALLOW_ERROR_INJECTION(i915_driver_early_probe, ERRNO); 280 280 281 281 /** 282 282 * i915_driver_late_release - cleanup the setup done in ··· 320 318 struct intel_gt *gt; 321 319 int ret, i; 322 320 323 323 - if (i915_inject_probe_failure(dev_priv)) 324 324 - return -ENODEV; 325 325 - 326 326 - ret = intel_gmch_bridge_setup(dev_priv); 321 321 + ret = i915_gmch_bridge_setup(dev_priv); 327 322 if (ret < 0) 328 323 return ret; 329 324 ··· 337 338 } 338 339 339 340 /* Try to make sure MCHBAR is enabled before poking at it */ 340 340 - intel_gmch_bar_setup(dev_priv); 341 341 + i915_gmch_bar_setup(dev_priv); 341 342 intel_device_info_runtime_init(dev_priv); 342 343 intel_display_device_info_runtime_init(display); 343 344 ··· 353 354 return 0; 354 355 355 356 err_uncore: 356 356 - intel_gmch_bar_teardown(dev_priv); 357 357 + i915_gmch_bar_teardown(dev_priv); 357 358 358 359 return ret; 359 360 } 361 361 + ALLOW_ERROR_INJECTION(i915_driver_mmio_probe, ERRNO); 360 362 361 363 /** 362 364 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() ··· 365 365 */ 366 366 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 367 367 { 368 368 - intel_gmch_bar_teardown(dev_priv); 368 368 + i915_gmch_bar_teardown(dev_priv); 369 369 } 370 370 371 371 /** ··· 465 465 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 466 466 int ret; 467 467 468 468 - if (i915_inject_probe_failure(dev_priv)) 469 469 - return -ENODEV; 470 470 - 471 468 if (HAS_PPGTT(dev_priv)) { 472 469 if (intel_vgpu_active(dev_priv) && 473 470 !intel_vgpu_has_full_ppgtt(dev_priv)) { ··· 489 492 } 490 493 491 494 /* needs to be done before ggtt probe */ 492 492 - intel_dram_edram_detect(dev_priv); 495 495 + i915_edram_detect(dev_priv); 493 496 494 497 ret = i915_set_dma_info(dev_priv); 495 498 if (ret) ··· 569 572 * Fill the dram structure to get the system dram info. This will be 570 573 * used for memory latency calculation. 571 574 */ 572 572 - ret = intel_dram_detect(dev_priv); 575 575 + ret = intel_dram_detect(display); 573 576 if (ret) 574 577 goto err_opregion; 575 578 ··· 592 595 i915_perf_fini(dev_priv); 593 596 return ret; 594 597 } 598 598 + ALLOW_ERROR_INJECTION(i915_driver_hw_probe, ERRNO); 595 599 596 600 /** 597 601 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() ··· 737 739 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 738 740 } 739 741 742 742 + static void fence_priority_display(struct dma_fence *fence) 743 743 + { 744 744 + if (dma_fence_is_i915(fence)) 745 745 + i915_gem_fence_wait_priority_display(fence); 746 746 + } 747 747 + 748 748 + static bool has_auxccs(struct drm_device *drm) 749 749 + { 750 750 + struct drm_i915_private *i915 = to_i915(drm); 751 751 + 752 752 + return IS_GRAPHICS_VER(i915, 9, 12) || 753 753 + IS_ALDERLAKE_P(i915) || 754 754 + IS_METEORLAKE(i915); 755 755 + } 756 756 + 757 757 + static bool has_fenced_regions(struct drm_device *drm) 758 758 + { 759 759 + return intel_gt_support_legacy_fencing(to_gt(to_i915(drm))); 760 760 + } 761 761 + 762 762 + static bool vgpu_active(struct drm_device *drm) 763 763 + { 764 764 + return intel_vgpu_active(to_i915(drm)); 765 765 + } 766 766 + 740 767 static const struct intel_display_parent_interface parent = { 768 768 + .hdcp = &i915_display_hdcp_interface, 769 769 + .irq = &i915_display_irq_interface, 770 770 + .panic = &i915_display_panic_interface, 771 771 + .pc8 = &i915_display_pc8_interface, 741 772 .rpm = &i915_display_rpm_interface, 773 773 + .rps = &i915_display_rps_interface, 774 774 + .stolen = &i915_display_stolen_interface, 775 775 + 776 776 + .fence_priority_display = fence_priority_display, 777 777 + .has_auxccs = has_auxccs, 778 778 + .has_fenced_regions = has_fenced_regions, 779 779 + .vgpu_active = vgpu_active, 742 780 }; 743 781 744 782 const struct intel_display_parent_interface *i915_driver_parent_interface(void) ··· 924 890 i915_gem_drain_freed_objects(i915); 925 891 i915_ggtt_driver_late_release(i915); 926 892 out_cleanup_mmio: 893 893 + intel_gvt_driver_remove(i915); 927 894 i915_driver_mmio_release(i915); 928 895 out_runtime_pm_put: 929 896 enable_rpm_wakeref_asserts(&i915->runtime_pm); ··· 1289 1254 1290 1255 intel_display_driver_init_hw(display); 1291 1256 1292 1292 - intel_clock_gating_init(dev_priv); 1257 1257 + intel_clock_gating_init(&dev_priv->drm); 1293 1258 1294 1259 if (intel_display_device_present(display)) 1295 1260 intel_display_driver_resume_access(display);

-3

drivers/gpu/drm/i915/i915_drv.h

reviewed

··· 60 60 #include "intel_step.h" 61 61 #include "intel_uncore.h" 62 62 63 63 - struct dram_info; 64 63 struct drm_i915_clock_gating_funcs; 65 64 struct intel_display; 66 65 struct intel_pxp; ··· 272 273 273 274 u32 suspend_count; 274 275 struct vlv_s0ix_state *vlv_s0ix_state; 275 275 - 276 276 - const struct dram_info *dram_info; 277 276 278 277 struct intel_runtime_pm runtime_pm; 279 278

+44

drivers/gpu/drm/i915/i915_edram.c

reviewed

··· 1 1 + // SPDX-License-Identifier: MIT 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #include <drm/drm_print.h> 5 5 + 6 6 + #include "i915_drv.h" 7 7 + #include "i915_edram.h" 8 8 + #include "i915_reg.h" 9 9 + 10 10 + static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap) 11 11 + { 12 12 + static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; 13 13 + static const u8 sets[4] = { 1, 1, 2, 2 }; 14 14 + 15 15 + return EDRAM_NUM_BANKS(cap) * 16 16 + ways[EDRAM_WAYS_IDX(cap)] * 17 17 + sets[EDRAM_SETS_IDX(cap)]; 18 18 + } 19 19 + 20 20 + void i915_edram_detect(struct drm_i915_private *i915) 21 21 + { 22 22 + u32 edram_cap = 0; 23 23 + 24 24 + if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9)) 25 25 + return; 26 26 + 27 27 + edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP); 28 28 + 29 29 + /* NB: We can't write IDICR yet because we don't have gt funcs set up */ 30 30 + 31 31 + if (!(edram_cap & EDRAM_ENABLED)) 32 32 + return; 33 33 + 34 34 + /* 35 35 + * The needed capability bits for size calculation are not there with 36 36 + * pre gen9 so return 128MB always. 37 37 + */ 38 38 + if (GRAPHICS_VER(i915) < 9) 39 39 + i915->edram_size_mb = 128; 40 40 + else 41 41 + i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap); 42 42 + 43 43 + drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb); 44 44 + }

+11

drivers/gpu/drm/i915/i915_edram.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #ifndef __I915_DRAM_H__ 5 5 + #define __I915_DRAM_H__ 6 6 + 7 7 + struct drm_i915_private; 8 8 + 9 9 + void i915_edram_detect(struct drm_i915_private *i915); 10 10 + 11 11 + #endif /* __I915_DRAM_H__ */

+111

drivers/gpu/drm/i915/i915_freq.c

reviewed

··· 1 1 + // SPDX-License-Identifier: MIT 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #include <drm/drm_print.h> 5 5 + 6 6 + #include "i915_drv.h" 7 7 + #include "i915_freq.h" 8 8 + #include "intel_mchbar_regs.h" 9 9 + 10 10 + unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) 11 11 + { 12 12 + u32 fsb; 13 13 + 14 14 + /* 15 15 + * Note that this only reads the state of the FSB 16 16 + * straps, not the actual FSB frequency. Some BIOSen 17 17 + * let you configure each independently. Ideally we'd 18 18 + * read out the actual FSB frequency but sadly we 19 19 + * don't know which registers have that information, 20 20 + * and all the relevant docs have gone to bit heaven :( 21 21 + */ 22 22 + fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK; 23 23 + 24 24 + if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) { 25 25 + switch (fsb) { 26 26 + case CLKCFG_FSB_400: 27 27 + return 400000; 28 28 + case CLKCFG_FSB_533: 29 29 + return 533333; 30 30 + case CLKCFG_FSB_667: 31 31 + return 666667; 32 32 + case CLKCFG_FSB_800: 33 33 + return 800000; 34 34 + case CLKCFG_FSB_1067: 35 35 + return 1066667; 36 36 + case CLKCFG_FSB_1333: 37 37 + return 1333333; 38 38 + default: 39 39 + MISSING_CASE(fsb); 40 40 + return 1333333; 41 41 + } 42 42 + } else { 43 43 + switch (fsb) { 44 44 + case CLKCFG_FSB_400_ALT: 45 45 + return 400000; 46 46 + case CLKCFG_FSB_533: 47 47 + return 533333; 48 48 + case CLKCFG_FSB_667: 49 49 + return 666667; 50 50 + case CLKCFG_FSB_800: 51 51 + return 800000; 52 52 + case CLKCFG_FSB_1067_ALT: 53 53 + return 1066667; 54 54 + case CLKCFG_FSB_1333_ALT: 55 55 + return 1333333; 56 56 + case CLKCFG_FSB_1600_ALT: 57 57 + return 1600000; 58 58 + default: 59 59 + MISSING_CASE(fsb); 60 60 + return 1333333; 61 61 + } 62 62 + } 63 63 + } 64 64 + 65 65 + unsigned int ilk_fsb_freq(struct drm_i915_private *i915) 66 66 + { 67 67 + u16 fsb; 68 68 + 69 69 + fsb = intel_uncore_read16(&i915->uncore, CSIPLL0) & 0x3ff; 70 70 + 71 71 + switch (fsb) { 72 72 + case 0x00c: 73 73 + return 3200000; 74 74 + case 0x00e: 75 75 + return 3733333; 76 76 + case 0x010: 77 77 + return 4266667; 78 78 + case 0x012: 79 79 + return 4800000; 80 80 + case 0x014: 81 81 + return 5333333; 82 82 + case 0x016: 83 83 + return 5866667; 84 84 + case 0x018: 85 85 + return 6400000; 86 86 + default: 87 87 + drm_dbg(&i915->drm, "unknown fsb frequency 0x%04x\n", fsb); 88 88 + return 0; 89 89 + } 90 90 + } 91 91 + 92 92 + unsigned int ilk_mem_freq(struct drm_i915_private *i915) 93 93 + { 94 94 + u16 ddrpll; 95 95 + 96 96 + ddrpll = intel_uncore_read16(&i915->uncore, DDRMPLL1); 97 97 + switch (ddrpll & 0xff) { 98 98 + case 0xc: 99 99 + return 800000; 100 100 + case 0x10: 101 101 + return 1066667; 102 102 + case 0x14: 103 103 + return 1333333; 104 104 + case 0x18: 105 105 + return 1600000; 106 106 + default: 107 107 + drm_dbg(&i915->drm, "unknown memory frequency 0x%02x\n", 108 108 + ddrpll & 0xff); 109 109 + return 0; 110 110 + } 111 111 + }

+13

drivers/gpu/drm/i915/i915_freq.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #ifndef __I915_FREQ_H__ 5 5 + #define __I915_FREQ_H__ 6 6 + 7 7 + struct drm_i915_private; 8 8 + 9 9 + unsigned int i9xx_fsb_freq(struct drm_i915_private *i915); 10 10 + unsigned int ilk_fsb_freq(struct drm_i915_private *i915); 11 11 + unsigned int ilk_mem_freq(struct drm_i915_private *i915); 12 12 + 13 13 + #endif /* __I915_FREQ_H__ */

+2 -2

drivers/gpu/drm/i915/i915_gem.c

reviewed

··· 1184 1184 * 1185 1185 * FIXME: break up the workarounds and apply them at the right time! 1186 1186 */ 1187 1187 - intel_clock_gating_init(dev_priv); 1187 1187 + intel_clock_gating_init(&dev_priv->drm); 1188 1188 1189 1189 for_each_gt(gt, dev_priv, i) { 1190 1190 ret = intel_gt_init(gt); ··· 1235 1235 /* Minimal basic recovery for KMS */ 1236 1236 ret = i915_ggtt_enable_hw(dev_priv); 1237 1237 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1238 1238 - intel_clock_gating_init(dev_priv); 1238 1238 + intel_clock_gating_init(&dev_priv->drm); 1239 1239 } 1240 1240 1241 1241 i915_gem_drain_freed_objects(dev_priv);

+13

drivers/gpu/drm/i915/i915_gmch.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #ifndef __I915_GMCH_H__ 5 5 + #define __I915_GMCH_H__ 6 6 + 7 7 + struct drm_i915_private; 8 8 + 9 9 + int i915_gmch_bridge_setup(struct drm_i915_private *i915); 10 10 + void i915_gmch_bar_setup(struct drm_i915_private *i915); 11 11 + void i915_gmch_bar_teardown(struct drm_i915_private *i915); 12 12 + 13 13 + #endif /* __I915_GMCH_H__ */

+9

drivers/gpu/drm/i915/i915_hdcp_gsc.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #ifndef __I915_HDCP_GSC_H__ 5 5 + #define __I915_HDCP_GSC_H__ 6 6 + 7 7 + extern const struct intel_display_hdcp_interface i915_display_hdcp_interface; 8 8 + 9 9 + #endif /* __I915_HDCP_GSC_H__ */

+16

drivers/gpu/drm/i915/i915_irq.c

reviewed

··· 33 33 34 34 #include <drm/drm_drv.h> 35 35 #include <drm/drm_print.h> 36 36 + #include <drm/intel/display_parent_interface.h> 36 37 37 38 #include "display/intel_display_irq.h" 38 39 #include "display/intel_hotplug.h" ··· 1253 1252 { 1254 1253 synchronize_hardirq(to_pci_dev(i915->drm.dev)->irq); 1255 1254 } 1255 1255 + 1256 1256 + static bool _intel_irq_enabled(struct drm_device *drm) 1257 1257 + { 1258 1258 + return intel_irqs_enabled(to_i915(drm)); 1259 1259 + } 1260 1260 + 1261 1261 + static void _intel_irq_synchronize(struct drm_device *drm) 1262 1262 + { 1263 1263 + return intel_synchronize_irq(to_i915(drm)); 1264 1264 + } 1265 1265 + 1266 1266 + const struct intel_display_irq_interface i915_display_irq_interface = { 1267 1267 + .enabled = _intel_irq_enabled, 1268 1268 + .synchronize = _intel_irq_synchronize, 1269 1269 + };

+2

drivers/gpu/drm/i915/i915_irq.h

reviewed

··· 51 51 void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs, 52 52 u32 emr_val); 53 53 54 54 + extern const struct intel_display_irq_interface i915_display_irq_interface; 55 55 + 54 56 #endif /* __I915_IRQ_H__ */

+35

drivers/gpu/drm/i915/i915_panic.c

reviewed

··· 1 1 + // SPDX-License-Identifier: MIT 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #include <drm/drm_panic.h> 5 5 + #include <drm/intel/display_parent_interface.h> 6 6 + 7 7 + #include "display/intel_display_types.h" 8 8 + #include "display/intel_fb.h" 9 9 + #include "gem/i915_gem_object.h" 10 10 + 11 11 + #include "i915_panic.h" 12 12 + 13 13 + static struct intel_panic *intel_panic_alloc(void) 14 14 + { 15 15 + return i915_gem_object_alloc_panic(); 16 16 + } 17 17 + 18 18 + static int intel_panic_setup(struct intel_panic *panic, struct drm_scanout_buffer *sb) 19 19 + { 20 20 + struct intel_framebuffer *fb = sb->private; 21 21 + struct drm_gem_object *obj = intel_fb_bo(&fb->base); 22 22 + 23 23 + return i915_gem_object_panic_setup(panic, sb, obj, fb->panic_tiling); 24 24 + } 25 25 + 26 26 + static void intel_panic_finish(struct intel_panic *panic) 27 27 + { 28 28 + return i915_gem_object_panic_finish(panic); 29 29 + } 30 30 + 31 31 + const struct intel_display_panic_interface i915_display_panic_interface = { 32 32 + .alloc = intel_panic_alloc, 33 33 + .setup = intel_panic_setup, 34 34 + .finish = intel_panic_finish, 35 35 + };

+9

drivers/gpu/drm/i915/i915_panic.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #ifndef __I915_PANIC_H__ 5 5 + #define __I915_PANIC_H__ 6 6 + 7 7 + extern const struct intel_display_panic_interface i915_display_panic_interface; 8 8 + 9 9 + #endif /* __I915_PANIC_H__ */

-5

drivers/gpu/drm/i915/i915_params.c

reviewed

··· 110 110 i915_param_named_unsafe(gsc_firmware_path, charp, 0400, 111 111 "GSC firmware path to use instead of the default one"); 112 112 113 113 - #if IS_ENABLED(CONFIG_DRM_I915_DEBUG) 114 114 - i915_param_named_unsafe(inject_probe_failure, uint, 0400, 115 115 - "Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)"); 116 116 - #endif 117 117 - 118 113 #if IS_ENABLED(CONFIG_DRM_I915_GVT) 119 114 i915_param_named(enable_gvt, bool, 0400, 120 115 "Enable support for Intel GVT-g graphics virtualization host support(default:false)");

-1

drivers/gpu/drm/i915/i915_params.h

reviewed

··· 55 55 param(bool, memtest, false, 0400) \ 56 56 param(int, mmio_debug, -IS_ENABLED(CONFIG_DRM_I915_DEBUG_MMIO), 0600) \ 57 57 param(unsigned int, reset, 3, 0600) \ 58 58 - param(unsigned int, inject_probe_failure, 0, 0) \ 59 58 param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \ 60 59 param(unsigned int, request_timeout_ms, CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \ 61 60 param(unsigned int, lmem_size, 0, 0400) \

+1 -5

drivers/gpu/drm/i915/i915_pci.c

reviewed

··· 999 999 if (err) 1000 1000 return err; 1001 1001 1002 1002 - if (i915_inject_probe_failure(pdev_to_i915(pdev))) { 1003 1003 - i915_pci_remove(pdev); 1004 1004 - return -ENODEV; 1005 1005 - } 1006 1006 - 1007 1002 err = i915_live_selftests(pdev); 1008 1003 if (err) { 1009 1004 i915_pci_remove(pdev); ··· 1013 1018 1014 1019 return 0; 1015 1020 } 1021 1021 + ALLOW_ERROR_INJECTION(i915_pci_probe, ERRNO); 1016 1022 1017 1023 static void i915_pci_shutdown(struct pci_dev *pdev) 1018 1024 {

+1 -29

drivers/gpu/drm/i915/i915_utils.c

reviewed

··· 17 17 drm_notice(&i915->drm, "CI tainted: %#x by %pS\n", 18 18 taint, __builtin_return_address(0)); 19 19 20 20 - /* Failures that occur during fault injection testing are expected */ 21 21 - if (!i915_error_injected()) 22 22 - __add_taint_for_CI(taint); 20 20 + __add_taint_for_CI(taint); 23 21 } 24 24 - 25 25 - #if IS_ENABLED(CONFIG_DRM_I915_DEBUG) 26 26 - static unsigned int i915_probe_fail_count; 27 27 - 28 28 - int __i915_inject_probe_error(struct drm_i915_private *i915, int err, 29 29 - const char *func, int line) 30 30 - { 31 31 - if (i915_probe_fail_count >= i915_modparams.inject_probe_failure) 32 32 - return 0; 33 33 - 34 34 - if (++i915_probe_fail_count < i915_modparams.inject_probe_failure) 35 35 - return 0; 36 36 - 37 37 - drm_info(&i915->drm, "Injecting failure %d at checkpoint %u [%s:%d]\n", 38 38 - err, i915_modparams.inject_probe_failure, func, line); 39 39 - 40 40 - i915_modparams.inject_probe_failure = 0; 41 41 - return err; 42 42 - } 43 43 - 44 44 - bool i915_error_injected(void) 45 45 - { 46 46 - return i915_probe_fail_count && !i915_modparams.inject_probe_failure; 47 47 - } 48 48 - 49 49 - #endif 50 22 51 23 bool i915_vtd_active(struct drm_i915_private *i915) 52 24 {

+1 -21

drivers/gpu/drm/i915/i915_utils.h

reviewed

··· 43 43 __stringify(x), (long)(x)) 44 44 #endif 45 45 46 46 - #if IS_ENABLED(CONFIG_DRM_I915_DEBUG) 47 47 - 48 48 - int __i915_inject_probe_error(struct drm_i915_private *i915, int err, 49 49 - const char *func, int line); 50 50 - #define i915_inject_probe_error(_i915, _err) \ 51 51 - __i915_inject_probe_error((_i915), (_err), __func__, __LINE__) 52 52 - bool i915_error_injected(void); 53 53 - 54 54 - #else 55 55 - 56 56 - #define i915_inject_probe_error(i915, e) ({ BUILD_BUG_ON_INVALID(i915); 0; }) 57 57 - #define i915_error_injected() false 58 58 - 59 59 - #endif 60 60 - 61 61 - #define i915_inject_probe_failure(i915) i915_inject_probe_error((i915), -ENODEV) 62 62 - 63 46 #define i915_probe_error(i915, fmt, ...) ({ \ 64 64 - if (i915_error_injected()) \ 65 65 - drm_dbg(&(i915)->drm, fmt, ##__VA_ARGS__); \ 66 66 - else \ 67 67 - drm_err(&(i915)->drm, fmt, ##__VA_ARGS__); \ 47 47 + drm_err(&(i915)->drm, fmt, ##__VA_ARGS__); \ 68 48 }) 69 49 70 50 #ifndef fetch_and_zero

+7 -3

drivers/gpu/drm/i915/intel_clock_gating.c

reviewed

··· 709 709 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); 710 710 } 711 711 712 712 - void intel_clock_gating_init(struct drm_i915_private *i915) 712 712 + void intel_clock_gating_init(struct drm_device *drm) 713 713 { 714 714 + struct drm_i915_private *i915 = to_i915(drm); 715 715 + 714 716 i915->clock_gating_funcs->init_clock_gating(i915); 715 717 } 716 718 ··· 751 749 752 750 /** 753 751 * intel_clock_gating_hooks_init - setup the clock gating hooks 754 754 - * @i915: device private 752 752 + * @drm: drm device 755 753 * 756 754 * Setup the hooks that configure which clocks of a given platform can be 757 755 * gated and also apply various GT and display specific workarounds for these 758 756 * platforms. Note that some GT specific workarounds are applied separately 759 757 * when GPU contexts or batchbuffers start their execution. 760 758 */ 761 761 - void intel_clock_gating_hooks_init(struct drm_i915_private *i915) 759 759 + void intel_clock_gating_hooks_init(struct drm_device *drm) 762 760 { 761 761 + struct drm_i915_private *i915 = to_i915(drm); 762 762 + 763 763 if (IS_DG2(i915)) 764 764 i915->clock_gating_funcs = &dg2_clock_gating_funcs; 765 765 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))

+3 -3

drivers/gpu/drm/i915/intel_clock_gating.h

reviewed

··· 6 6 #ifndef __INTEL_CLOCK_GATING_H__ 7 7 #define __INTEL_CLOCK_GATING_H__ 8 8 9 9 - struct drm_i915_private; 9 9 + struct drm_device; 10 10 11 11 - void intel_clock_gating_init(struct drm_i915_private *i915); 12 12 - void intel_clock_gating_hooks_init(struct drm_i915_private *i915); 11 11 + void intel_clock_gating_init(struct drm_device *drm); 12 12 + void intel_clock_gating_hooks_init(struct drm_device *drm); 13 13 14 14 #endif /* __INTEL_CLOCK_GATING_H__ */

-3

drivers/gpu/drm/i915/intel_gvt.c

reviewed

··· 238 238 */ 239 239 int intel_gvt_init(struct drm_i915_private *dev_priv) 240 240 { 241 241 - if (i915_inject_probe_failure(dev_priv)) 242 242 - return -ENODEV; 243 243 - 244 241 mutex_lock(&intel_gvt_mutex); 245 242 list_add_tail(&dev_priv->vgpu.entry, &intel_gvt_devices); 246 243 if (intel_gvt_ops)

+39 -29

drivers/gpu/drm/i915/intel_mchbar_regs.h

reviewed

··· 130 130 #define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1) 131 131 132 132 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000) 133 133 - #define SKL_DRAM_DDR_TYPE_MASK (0x3 << 0) 134 134 - #define SKL_DRAM_DDR_TYPE_DDR4 (0 << 0) 135 135 - #define SKL_DRAM_DDR_TYPE_DDR3 (1 << 0) 136 136 - #define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0) 137 137 - #define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0) 133 133 + #define SKL_DRAM_DDR_TYPE_MASK REG_GENMASK(1, 0) 134 134 + #define SKL_DRAM_DDR_TYPE_DDR4 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 0) 135 135 + #define SKL_DRAM_DDR_TYPE_DDR3 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 1) 136 136 + #define SKL_DRAM_DDR_TYPE_LPDDR3 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 2) 137 137 + #define SKL_DRAM_DDR_TYPE_LPDDR4 REG_FIELD_PREP(SKL_DRAM_DDR_TYPE_MASK, 3) 138 138 139 139 /* snb MCH registers for reading the DRAM channel configuration */ 140 140 #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) ··· 160 160 161 161 #define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C) 162 162 #define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010) 163 163 - #define SKL_DRAM_S_SHIFT 16 164 164 - #define SKL_DRAM_SIZE_MASK 0x3F 165 165 - #define SKL_DRAM_WIDTH_MASK (0x3 << 8) 166 166 - #define SKL_DRAM_WIDTH_SHIFT 8 167 167 - #define SKL_DRAM_WIDTH_X8 (0x0 << 8) 168 168 - #define SKL_DRAM_WIDTH_X16 (0x1 << 8) 169 169 - #define SKL_DRAM_WIDTH_X32 (0x2 << 8) 170 170 - #define SKL_DRAM_RANK_MASK (0x1 << 10) 171 171 - #define SKL_DRAM_RANK_SHIFT 10 172 172 - #define SKL_DRAM_RANK_1 (0x0 << 10) 173 173 - #define SKL_DRAM_RANK_2 (0x1 << 10) 174 174 - #define SKL_DRAM_RANK_MASK (0x1 << 10) 175 175 - #define ICL_DRAM_SIZE_MASK 0x7F 176 176 - #define ICL_DRAM_WIDTH_MASK (0x3 << 7) 177 177 - #define ICL_DRAM_WIDTH_SHIFT 7 178 178 - #define ICL_DRAM_WIDTH_X8 (0x0 << 7) 179 179 - #define ICL_DRAM_WIDTH_X16 (0x1 << 7) 180 180 - #define ICL_DRAM_WIDTH_X32 (0x2 << 7) 181 181 - #define ICL_DRAM_RANK_MASK (0x3 << 9) 182 182 - #define ICL_DRAM_RANK_SHIFT 9 183 183 - #define ICL_DRAM_RANK_1 (0x0 << 9) 184 184 - #define ICL_DRAM_RANK_2 (0x1 << 9) 185 185 - #define ICL_DRAM_RANK_3 (0x2 << 9) 186 186 - #define ICL_DRAM_RANK_4 (0x3 << 9) 163 163 + #define SKL_DIMM_S_RANK_MASK REG_GENMASK(26, 26) 164 164 + #define SKL_DIMM_S_RANK_1 REG_FIELD_PREP(SKL_DIMM_S_RANK_MASK, 0) 165 165 + #define SKL_DIMM_S_RANK_2 REG_FIELD_PREP(SKL_DIMM_S_RANK_MASK, 1) 166 166 + #define SKL_DIMM_S_WIDTH_MASK REG_GENMASK(25, 24) 167 167 + #define SKL_DIMM_S_WIDTH_X8 REG_FIELD_PREP(SKL_DIMM_S_WIDTH_MASK, 0) 168 168 + #define SKL_DIMM_S_WIDTH_X16 REG_FIELD_PREP(SKL_DIMM_S_WIDTH_MASK, 1) 169 169 + #define SKL_DIMM_S_WIDTH_X32 REG_FIELD_PREP(SKL_DIMM_S_WIDTH_MASK, 2) 170 170 + #define SKL_DIMM_S_SIZE_MASK REG_GENMASK(21, 16) 171 171 + #define SKL_DIMM_L_RANK_MASK REG_GENMASK(10, 10) 172 172 + #define SKL_DIMM_L_RANK_1 REG_FIELD_PREP(SKL_DIMM_L_RANK_MASK, 0) 173 173 + #define SKL_DIMM_L_RANK_2 REG_FIELD_PREP(SKL_DIMM_L_RANK_MASK, 1) 174 174 + #define SKL_DIMM_L_WIDTH_MASK REG_GENMASK(9, 8) 175 175 + #define SKL_DIMM_L_WIDTH_X8 REG_FIELD_PREP(SKL_DIMM_L_WIDTH_MASK, 0) 176 176 + #define SKL_DIMM_L_WIDTH_X16 REG_FIELD_PREP(SKL_DIMM_L_WIDTH_MASK, 1) 177 177 + #define SKL_DIMM_L_WIDTH_X32 REG_FIELD_PREP(SKL_DIMM_L_WIDTH_MASK, 2) 178 178 + #define SKL_DIMM_L_SIZE_MASK REG_GENMASK(5, 0) 179 179 + #define ICL_DIMM_S_RANK_MASK REG_GENMASK(27, 26) 180 180 + #define ICL_DIMM_S_RANK_1 REG_FIELD_PREP(ICL_DIMM_S_RANK_MASK, 0) 181 181 + #define ICL_DIMM_S_RANK_2 REG_FIELD_PREP(ICL_DIMM_S_RANK_MASK, 1) 182 182 + #define ICL_DIMM_S_WIDTH_MASK REG_GENMASK(25, 24) 183 183 + #define ICL_DIMM_S_WIDTH_X8 REG_FIELD_PREP(ICL_DIMM_S_WIDTH_MASK, 0) 184 184 + #define ICL_DIMM_S_WIDTH_X16 REG_FIELD_PREP(ICL_DIMM_S_WIDTH_MASK, 1) 185 185 + #define ICL_DIMM_S_WIDTH_X32 REG_FIELD_PREP(ICL_DIMM_S_WIDTH_MASK, 2) 186 186 + #define ICL_DIMM_S_SIZE_MASK REG_GENMASK(22, 16) 187 187 + #define ICL_DIMM_L_RANK_MASK REG_GENMASK(10, 9) 188 188 + #define ICL_DIMM_L_RANK_1 REG_FIELD_PREP(ICL_DIMM_L_RANK_MASK, 0) 189 189 + #define ICL_DIMM_L_RANK_2 REG_FIELD_PREP(ICL_DIMM_L_RANK_MASK, 1) 190 190 + #define ICL_DIMM_L_RANK_3 REG_FIELD_PREP(ICL_DIMM_L_RANK_MASK, 2) 191 191 + #define ICL_DIMM_L_RANK_4 REG_FIELD_PREP(ICL_DIMM_L_RANK_MASK, 3) 192 192 + #define ICL_DIMM_L_WIDTH_MASK REG_GENMASK(8, 7) 193 193 + #define ICL_DIMM_L_WIDTH_X8 REG_FIELD_PREP(ICL_DIMM_L_WIDTH_MASK, 0) 194 194 + #define ICL_DIMM_L_WIDTH_X16 REG_FIELD_PREP(ICL_DIMM_L_WIDTH_MASK, 1) 195 195 + #define ICL_DIMM_L_WIDTH_X32 REG_FIELD_PREP(ICL_DIMM_L_WIDTH_MASK, 2) 196 196 + #define ICL_DIMM_L_SIZE_MASK REG_GENMASK(6, 0) 187 197 188 198 #define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918) 189 199 #define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)

+1 -3

drivers/gpu/drm/i915/intel_uncore.c

reviewed

··· 2072 2072 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); 2073 2073 GEM_BUG_ON(uncore->fw_domain[domain_id]); 2074 2074 2075 2075 - if (i915_inject_probe_failure(uncore->i915)) 2076 2076 - return -ENOMEM; 2077 2077 - 2078 2075 d = kzalloc(sizeof(*d), GFP_KERNEL); 2079 2076 if (!d) 2080 2077 return -ENOMEM; ··· 2115 2118 2116 2119 return 0; 2117 2120 } 2121 2121 + ALLOW_ERROR_INJECTION(__fw_domain_init, ERRNO); 2118 2122 2119 2123 static void fw_domain_fini(struct intel_uncore *uncore, 2120 2124 enum forcewake_domain_id domain_id)

+1 -1

drivers/gpu/drm/i915/intel_wakeref.c

reviewed

··· 80 80 /* Assume we are not in process context and so cannot sleep. */ 81 81 if (flags & INTEL_WAKEREF_PUT_ASYNC || !mutex_trylock(&wf->mutex)) { 82 82 mod_delayed_work(wf->i915->unordered_wq, &wf->work, 83 83 - FIELD_GET(INTEL_WAKEREF_PUT_DELAY, flags)); 83 83 + FIELD_GET(INTEL_WAKEREF_PUT_DELAY_MASK, flags)); 84 84 return; 85 85 } 86 86

+5 -9

drivers/gpu/drm/i915/intel_wakeref.h

reviewed

··· 128 128 return atomic_inc_not_zero(&wf->count); 129 129 } 130 130 131 131 - enum { 132 132 - INTEL_WAKEREF_PUT_ASYNC_BIT = 0, 133 133 - __INTEL_WAKEREF_PUT_LAST_BIT__ 134 134 - }; 135 135 - 136 131 static inline void 137 132 intel_wakeref_might_get(struct intel_wakeref *wf) 138 133 { 139 134 might_lock(&wf->mutex); 140 135 } 136 136 + 137 137 + /* flags for __intel_wakeref_put() and __intel_wakeref_put_last */ 138 138 + #define INTEL_WAKEREF_PUT_ASYNC BIT(0) 139 139 + #define INTEL_WAKEREF_PUT_DELAY_MASK GENMASK(BITS_PER_LONG - 1, 1) 141 140 142 141 /** 143 142 * __intel_wakeref_put: Release the wakeref ··· 153 154 */ 154 155 static inline void 155 156 __intel_wakeref_put(struct intel_wakeref *wf, unsigned long flags) 156 156 - #define INTEL_WAKEREF_PUT_ASYNC BIT(INTEL_WAKEREF_PUT_ASYNC_BIT) 157 157 - #define INTEL_WAKEREF_PUT_DELAY \ 158 158 - GENMASK(BITS_PER_LONG - 1, __INTEL_WAKEREF_PUT_LAST_BIT__) 159 157 { 160 158 INTEL_WAKEREF_BUG_ON(atomic_read(&wf->count) <= 0); 161 159 if (unlikely(!atomic_add_unless(&wf->count, -1, 1))) ··· 177 181 { 178 182 __intel_wakeref_put(wf, 179 183 INTEL_WAKEREF_PUT_ASYNC | 180 180 - FIELD_PREP(INTEL_WAKEREF_PUT_DELAY, delay)); 184 184 + FIELD_PREP(INTEL_WAKEREF_PUT_DELAY_MASK, delay)); 181 185 } 182 186 183 187 static inline void

+221 -176

drivers/gpu/drm/i915/soc/intel_dram.c drivers/gpu/drm/i915/display/intel_dram.c

reviewed

··· 8 8 #include <drm/drm_managed.h> 9 9 #include <drm/drm_print.h> 10 10 11 11 - #include "../display/intel_display_core.h" /* FIXME */ 12 12 - 13 11 #include "i915_drv.h" 14 12 #include "i915_reg.h" 15 15 - #include "i915_utils.h" 13 13 + #include "intel_display_core.h" 14 14 + #include "intel_display_utils.h" 16 15 #include "intel_dram.h" 17 16 #include "intel_mchbar_regs.h" 18 17 #include "intel_pcode.h" ··· 56 57 57 58 #undef DRAM_TYPE_STR 58 59 59 59 - static enum intel_dram_type pnv_dram_type(struct drm_i915_private *i915) 60 60 + static enum intel_dram_type pnv_dram_type(struct intel_display *display) 60 61 { 62 62 + struct drm_i915_private *i915 = to_i915(display->drm); 63 63 + 61 64 return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3 ? 62 65 INTEL_DRAM_DDR3 : INTEL_DRAM_DDR2; 63 66 } 64 67 65 65 - static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv) 68 68 + static unsigned int pnv_mem_freq(struct intel_display *display) 66 69 { 70 70 + struct drm_i915_private *dev_priv = to_i915(display->drm); 67 71 u32 tmp; 68 72 69 73 tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG); ··· 83 81 return 0; 84 82 } 85 83 86 86 - static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv) 84 84 + static unsigned int ilk_mem_freq(struct intel_display *display) 87 85 { 86 86 + struct drm_i915_private *dev_priv = to_i915(display->drm); 88 87 u16 ddrpll; 89 88 90 89 ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); ··· 99 96 case 0x18: 100 97 return 1600000; 101 98 default: 102 102 - drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n", 103 103 - ddrpll & 0xff); 99 99 + drm_dbg_kms(display->drm, "unknown memory frequency 0x%02x\n", 100 100 + ddrpll & 0xff); 104 101 return 0; 105 102 } 106 103 } 107 104 108 108 - static unsigned int chv_mem_freq(struct drm_i915_private *i915) 105 105 + static unsigned int chv_mem_freq(struct intel_display *display) 109 106 { 110 107 u32 val; 111 108 112 112 - vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_CCK)); 113 113 - val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_CCK, CCK_FUSE_REG); 114 114 - vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_CCK)); 109 109 + vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK)); 110 110 + val = vlv_iosf_sb_read(display->drm, VLV_IOSF_SB_CCK, CCK_FUSE_REG); 111 111 + vlv_iosf_sb_put(display->drm, BIT(VLV_IOSF_SB_CCK)); 115 112 116 113 switch ((val >> 2) & 0x7) { 117 114 case 3: ··· 121 118 } 122 119 } 123 120 124 124 - static unsigned int vlv_mem_freq(struct drm_i915_private *i915) 121 121 + static unsigned int vlv_mem_freq(struct intel_display *display) 125 122 { 126 123 u32 val; 127 124 128 128 - vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); 129 129 - val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS); 130 130 - vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); 125 125 + vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_PUNIT)); 126 126 + val = vlv_iosf_sb_read(display->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS); 127 127 + vlv_iosf_sb_put(display->drm, BIT(VLV_IOSF_SB_PUNIT)); 131 128 132 129 switch ((val >> 6) & 3) { 133 130 case 0: ··· 142 139 return 0; 143 140 } 144 141 145 145 - unsigned int intel_mem_freq(struct drm_i915_private *i915) 142 142 + unsigned int intel_mem_freq(struct intel_display *display) 146 143 { 147 147 - if (IS_PINEVIEW(i915)) 148 148 - return pnv_mem_freq(i915); 149 149 - else if (GRAPHICS_VER(i915) == 5) 150 150 - return ilk_mem_freq(i915); 151 151 - else if (IS_CHERRYVIEW(i915)) 152 152 - return chv_mem_freq(i915); 153 153 - else if (IS_VALLEYVIEW(i915)) 154 154 - return vlv_mem_freq(i915); 144 144 + if (display->platform.pineview) 145 145 + return pnv_mem_freq(display); 146 146 + else if (DISPLAY_VER(display) == 5) 147 147 + return ilk_mem_freq(display); 148 148 + else if (display->platform.cherryview) 149 149 + return chv_mem_freq(display); 150 150 + else if (display->platform.valleyview) 151 151 + return vlv_mem_freq(display); 155 152 else 156 153 return 0; 157 154 } 158 155 159 159 - static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) 156 156 + static unsigned int i9xx_fsb_freq(struct intel_display *display) 160 157 { 158 158 + struct drm_i915_private *i915 = to_i915(display->drm); 161 159 u32 fsb; 162 160 163 161 /* ··· 171 167 */ 172 168 fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK; 173 169 174 174 - if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) { 170 170 + if (display->platform.pineview || display->platform.mobile) { 175 171 switch (fsb) { 176 172 case CLKCFG_FSB_400: 177 173 return 400000; ··· 212 208 } 213 209 } 214 210 215 215 - static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv) 211 211 + static unsigned int ilk_fsb_freq(struct intel_display *display) 216 212 { 213 213 + struct drm_i915_private *dev_priv = to_i915(display->drm); 217 214 u16 fsb; 218 215 219 216 fsb = intel_uncore_read16(&dev_priv->uncore, CSIPLL0) & 0x3ff; ··· 235 230 case 0x018: 236 231 return 6400000; 237 232 default: 238 238 - drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb); 233 233 + drm_dbg_kms(display->drm, "unknown fsb frequency 0x%04x\n", fsb); 239 234 return 0; 240 235 } 241 236 } 242 237 243 243 - unsigned int intel_fsb_freq(struct drm_i915_private *i915) 238 238 + unsigned int intel_fsb_freq(struct intel_display *display) 244 239 { 245 245 - if (GRAPHICS_VER(i915) == 5) 246 246 - return ilk_fsb_freq(i915); 247 247 - else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4) 248 248 - return i9xx_fsb_freq(i915); 240 240 + if (DISPLAY_VER(display) == 5) 241 241 + return ilk_fsb_freq(display); 242 242 + else if (IS_DISPLAY_VER(display, 3, 4)) 243 243 + return i9xx_fsb_freq(display); 249 244 else 250 245 return 0; 251 246 } 252 247 253 253 - static int i915_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) 248 248 + static int i915_get_dram_info(struct intel_display *display, struct dram_info *dram_info) 254 249 { 255 255 - dram_info->fsb_freq = intel_fsb_freq(i915); 250 250 + dram_info->fsb_freq = intel_fsb_freq(display); 256 251 if (dram_info->fsb_freq) 257 257 - drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", dram_info->fsb_freq); 252 252 + drm_dbg_kms(display->drm, "FSB frequency: %d kHz\n", dram_info->fsb_freq); 258 253 259 259 - dram_info->mem_freq = intel_mem_freq(i915); 254 254 + dram_info->mem_freq = intel_mem_freq(display); 260 255 if (dram_info->mem_freq) 261 261 - drm_dbg(&i915->drm, "DDR speed: %d kHz\n", dram_info->mem_freq); 256 256 + drm_dbg_kms(display->drm, "DDR speed: %d kHz\n", dram_info->mem_freq); 262 257 263 263 - if (IS_PINEVIEW(i915)) 264 264 - dram_info->type = pnv_dram_type(i915); 258 258 + if (display->platform.pineview) 259 259 + dram_info->type = pnv_dram_type(display); 265 260 266 261 return 0; 267 262 } ··· 272 267 } 273 268 274 269 /* Returns total Gb for the whole DIMM */ 275 275 - static int skl_get_dimm_size(u16 val) 270 270 + static int skl_get_dimm_s_size(u32 val) 276 271 { 277 277 - return (val & SKL_DRAM_SIZE_MASK) * 8; 272 272 + return REG_FIELD_GET(SKL_DIMM_S_SIZE_MASK, val) * 8; 278 273 } 279 274 280 280 - static int skl_get_dimm_width(u16 val) 275 275 + static int skl_get_dimm_l_size(u32 val) 281 276 { 282 282 - if (skl_get_dimm_size(val) == 0) 277 277 + return REG_FIELD_GET(SKL_DIMM_L_SIZE_MASK, val) * 8; 278 278 + } 279 279 + 280 280 + static int skl_get_dimm_s_width(u32 val) 281 281 + { 282 282 + if (skl_get_dimm_s_size(val) == 0) 283 283 return 0; 284 284 285 285 - switch (val & SKL_DRAM_WIDTH_MASK) { 286 286 - case SKL_DRAM_WIDTH_X8: 287 287 - case SKL_DRAM_WIDTH_X16: 288 288 - case SKL_DRAM_WIDTH_X32: 289 289 - val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT; 290 290 - return 8 << val; 285 285 + switch (val & SKL_DIMM_S_WIDTH_MASK) { 286 286 + case SKL_DIMM_S_WIDTH_X8: 287 287 + case SKL_DIMM_S_WIDTH_X16: 288 288 + case SKL_DIMM_S_WIDTH_X32: 289 289 + return 8 << REG_FIELD_GET(SKL_DIMM_S_WIDTH_MASK, val); 291 290 default: 292 291 MISSING_CASE(val); 293 292 return 0; 294 293 } 295 294 } 296 295 297 297 - static int skl_get_dimm_ranks(u16 val) 296 296 + static int skl_get_dimm_l_width(u32 val) 298 297 { 299 299 - if (skl_get_dimm_size(val) == 0) 298 298 + if (skl_get_dimm_l_size(val) == 0) 300 299 return 0; 301 300 302 302 - val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT; 301 301 + switch (val & SKL_DIMM_L_WIDTH_MASK) { 302 302 + case SKL_DIMM_L_WIDTH_X8: 303 303 + case SKL_DIMM_L_WIDTH_X16: 304 304 + case SKL_DIMM_L_WIDTH_X32: 305 305 + return 8 << REG_FIELD_GET(SKL_DIMM_L_WIDTH_MASK, val); 306 306 + default: 307 307 + MISSING_CASE(val); 308 308 + return 0; 309 309 + } 310 310 + } 303 311 304 304 - return val + 1; 312 312 + static int skl_get_dimm_s_ranks(u32 val) 313 313 + { 314 314 + if (skl_get_dimm_s_size(val) == 0) 315 315 + return 0; 316 316 + 317 317 + return REG_FIELD_GET(SKL_DIMM_S_RANK_MASK, val) + 1; 318 318 + } 319 319 + 320 320 + static int skl_get_dimm_l_ranks(u32 val) 321 321 + { 322 322 + if (skl_get_dimm_l_size(val) == 0) 323 323 + return 0; 324 324 + 325 325 + return REG_FIELD_GET(SKL_DIMM_L_RANK_MASK, val) + 1; 305 326 } 306 327 307 328 /* Returns total Gb for the whole DIMM */ 308 308 - static int icl_get_dimm_size(u16 val) 329 329 + static int icl_get_dimm_s_size(u32 val) 309 330 { 310 310 - return (val & ICL_DRAM_SIZE_MASK) * 8 / 2; 331 331 + return REG_FIELD_GET(ICL_DIMM_S_SIZE_MASK, val) * 8 / 2; 311 332 } 312 333 313 313 - static int icl_get_dimm_width(u16 val) 334 334 + static int icl_get_dimm_l_size(u32 val) 314 335 { 315 315 - if (icl_get_dimm_size(val) == 0) 336 336 + return REG_FIELD_GET(ICL_DIMM_L_SIZE_MASK, val) * 8 / 2; 337 337 + } 338 338 + 339 339 + static int icl_get_dimm_s_width(u32 val) 340 340 + { 341 341 + if (icl_get_dimm_s_size(val) == 0) 316 342 return 0; 317 343 318 318 - switch (val & ICL_DRAM_WIDTH_MASK) { 319 319 - case ICL_DRAM_WIDTH_X8: 320 320 - case ICL_DRAM_WIDTH_X16: 321 321 - case ICL_DRAM_WIDTH_X32: 322 322 - val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT; 323 323 - return 8 << val; 344 344 + switch (val & ICL_DIMM_S_WIDTH_MASK) { 345 345 + case ICL_DIMM_S_WIDTH_X8: 346 346 + case ICL_DIMM_S_WIDTH_X16: 347 347 + case ICL_DIMM_S_WIDTH_X32: 348 348 + return 8 << REG_FIELD_GET(ICL_DIMM_S_WIDTH_MASK, val); 324 349 default: 325 350 MISSING_CASE(val); 326 351 return 0; 327 352 } 328 353 } 329 354 330 330 - static int icl_get_dimm_ranks(u16 val) 355 355 + static int icl_get_dimm_l_width(u32 val) 331 356 { 332 332 - if (icl_get_dimm_size(val) == 0) 357 357 + if (icl_get_dimm_l_size(val) == 0) 333 358 return 0; 334 359 335 335 - val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT; 360 360 + switch (val & ICL_DIMM_L_WIDTH_MASK) { 361 361 + case ICL_DIMM_L_WIDTH_X8: 362 362 + case ICL_DIMM_L_WIDTH_X16: 363 363 + case ICL_DIMM_L_WIDTH_X32: 364 364 + return 8 << REG_FIELD_GET(ICL_DIMM_L_WIDTH_MASK, val); 365 365 + default: 366 366 + MISSING_CASE(val); 367 367 + return 0; 368 368 + } 369 369 + } 336 370 337 337 - return val + 1; 371 371 + static int icl_get_dimm_s_ranks(u32 val) 372 372 + { 373 373 + if (icl_get_dimm_s_size(val) == 0) 374 374 + return 0; 375 375 + 376 376 + return REG_FIELD_GET(ICL_DIMM_S_RANK_MASK, val) + 1; 377 377 + } 378 378 + 379 379 + static int icl_get_dimm_l_ranks(u32 val) 380 380 + { 381 381 + if (icl_get_dimm_l_size(val) == 0) 382 382 + return 0; 383 383 + 384 384 + return REG_FIELD_GET(ICL_DIMM_L_RANK_MASK, val) + 1; 338 385 } 339 386 340 387 static bool ··· 397 340 } 398 341 399 342 static void 400 400 - skl_dram_get_dimm_info(struct drm_i915_private *i915, 401 401 - struct dram_dimm_info *dimm, 402 402 - int channel, char dimm_name, u16 val) 343 343 + skl_dram_print_dimm_info(struct intel_display *display, 344 344 + struct dram_dimm_info *dimm, 345 345 + int channel, char dimm_name) 403 346 { 404 404 - if (GRAPHICS_VER(i915) >= 11) { 405 405 - dimm->size = icl_get_dimm_size(val); 406 406 - dimm->width = icl_get_dimm_width(val); 407 407 - dimm->ranks = icl_get_dimm_ranks(val); 408 408 - } else { 409 409 - dimm->size = skl_get_dimm_size(val); 410 410 - dimm->width = skl_get_dimm_width(val); 411 411 - dimm->ranks = skl_get_dimm_ranks(val); 412 412 - } 413 413 - 414 414 - drm_dbg_kms(&i915->drm, 347 347 + drm_dbg_kms(display->drm, 415 348 "CH%u DIMM %c size: %u Gb, width: X%u, ranks: %u, 16Gb+ DIMMs: %s\n", 416 349 channel, dimm_name, dimm->size, dimm->width, dimm->ranks, 417 350 str_yes_no(skl_is_16gb_dimm(dimm))); 418 351 } 419 352 353 353 + static void 354 354 + skl_dram_get_dimm_l_info(struct intel_display *display, 355 355 + struct dram_dimm_info *dimm, 356 356 + int channel, u32 val) 357 357 + { 358 358 + if (DISPLAY_VER(display) >= 11) { 359 359 + dimm->size = icl_get_dimm_l_size(val); 360 360 + dimm->width = icl_get_dimm_l_width(val); 361 361 + dimm->ranks = icl_get_dimm_l_ranks(val); 362 362 + } else { 363 363 + dimm->size = skl_get_dimm_l_size(val); 364 364 + dimm->width = skl_get_dimm_l_width(val); 365 365 + dimm->ranks = skl_get_dimm_l_ranks(val); 366 366 + } 367 367 + 368 368 + skl_dram_print_dimm_info(display, dimm, channel, 'L'); 369 369 + } 370 370 + 371 371 + static void 372 372 + skl_dram_get_dimm_s_info(struct intel_display *display, 373 373 + struct dram_dimm_info *dimm, 374 374 + int channel, u32 val) 375 375 + { 376 376 + if (DISPLAY_VER(display) >= 11) { 377 377 + dimm->size = icl_get_dimm_s_size(val); 378 378 + dimm->width = icl_get_dimm_s_width(val); 379 379 + dimm->ranks = icl_get_dimm_s_ranks(val); 380 380 + } else { 381 381 + dimm->size = skl_get_dimm_s_size(val); 382 382 + dimm->width = skl_get_dimm_s_width(val); 383 383 + dimm->ranks = skl_get_dimm_s_ranks(val); 384 384 + } 385 385 + 386 386 + skl_dram_print_dimm_info(display, dimm, channel, 'S'); 387 387 + } 388 388 + 420 389 static int 421 421 - skl_dram_get_channel_info(struct drm_i915_private *i915, 390 390 + skl_dram_get_channel_info(struct intel_display *display, 422 391 struct dram_channel_info *ch, 423 392 int channel, u32 val) 424 393 { 425 425 - skl_dram_get_dimm_info(i915, &ch->dimm_l, 426 426 - channel, 'L', val & 0xffff); 427 427 - skl_dram_get_dimm_info(i915, &ch->dimm_s, 428 428 - channel, 'S', val >> 16); 394 394 + skl_dram_get_dimm_l_info(display, &ch->dimm_l, channel, val); 395 395 + skl_dram_get_dimm_s_info(display, &ch->dimm_s, channel, val); 429 396 430 397 if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) { 431 431 - drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel); 398 398 + drm_dbg_kms(display->drm, "CH%u not populated\n", channel); 432 399 return -EINVAL; 433 400 } 434 401 ··· 466 385 ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) || 467 386 skl_is_16gb_dimm(&ch->dimm_s); 468 387 469 469 - drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb+ DIMMs: %s\n", 388 388 + drm_dbg_kms(display->drm, "CH%u ranks: %u, 16Gb+ DIMMs: %s\n", 470 389 channel, ch->ranks, str_yes_no(ch->is_16gb_dimm)); 471 390 472 391 return 0; ··· 482 401 } 483 402 484 403 static int 485 485 - skl_dram_get_channels_info(struct drm_i915_private *i915, struct dram_info *dram_info) 404 404 + skl_dram_get_channels_info(struct intel_display *display, struct dram_info *dram_info) 486 405 { 406 406 + struct drm_i915_private *i915 = to_i915(display->drm); 487 407 struct dram_channel_info ch0 = {}, ch1 = {}; 488 408 u32 val; 489 409 int ret; ··· 494 412 495 413 val = intel_uncore_read(&i915->uncore, 496 414 SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); 497 497 - ret = skl_dram_get_channel_info(i915, &ch0, 0, val); 415 415 + ret = skl_dram_get_channel_info(display, &ch0, 0, val); 498 416 if (ret == 0) 499 417 dram_info->num_channels++; 500 418 501 419 val = intel_uncore_read(&i915->uncore, 502 420 SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); 503 503 - ret = skl_dram_get_channel_info(i915, &ch1, 1, val); 421 421 + ret = skl_dram_get_channel_info(display, &ch1, 1, val); 504 422 if (ret == 0) 505 423 dram_info->num_channels++; 506 424 507 425 if (dram_info->num_channels == 0) { 508 508 - drm_info(&i915->drm, "Number of memory channels is zero\n"); 426 426 + drm_info(display->drm, "Number of memory channels is zero\n"); 509 427 return -EINVAL; 510 428 } 511 429 512 430 if (ch0.ranks == 0 && ch1.ranks == 0) { 513 513 - drm_info(&i915->drm, "couldn't get memory rank information\n"); 431 431 + drm_info(display->drm, "couldn't get memory rank information\n"); 514 432 return -EINVAL; 515 433 } 516 434 ··· 518 436 519 437 dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1); 520 438 521 521 - drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n", 439 439 + drm_dbg_kms(display->drm, "Memory configuration is symmetric? %s\n", 522 440 str_yes_no(dram_info->symmetric_memory)); 523 441 524 524 - drm_dbg_kms(&i915->drm, "16Gb+ DIMMs: %s\n", 442 442 + drm_dbg_kms(display->drm, "16Gb+ DIMMs: %s\n", 525 443 str_yes_no(dram_info->has_16gb_dimms)); 526 444 527 445 return 0; 528 446 } 529 447 530 448 static enum intel_dram_type 531 531 - skl_get_dram_type(struct drm_i915_private *i915) 449 449 + skl_get_dram_type(struct intel_display *display) 532 450 { 451 451 + struct drm_i915_private *i915 = to_i915(display->drm); 533 452 u32 val; 534 453 535 454 val = intel_uncore_read(&i915->uncore, ··· 552 469 } 553 470 554 471 static int 555 555 - skl_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) 472 472 + skl_get_dram_info(struct intel_display *display, struct dram_info *dram_info) 556 473 { 557 474 int ret; 558 475 559 559 - dram_info->type = skl_get_dram_type(i915); 476 476 + dram_info->type = skl_get_dram_type(display); 560 477 561 561 - ret = skl_dram_get_channels_info(i915, dram_info); 478 478 + ret = skl_dram_get_channels_info(display, dram_info); 562 479 if (ret) 563 480 return ret; 564 481 ··· 643 560 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm); 644 561 } 645 562 646 646 - static int bxt_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) 563 563 + static int bxt_get_dram_info(struct intel_display *display, struct dram_info *dram_info) 647 564 { 565 565 + struct drm_i915_private *i915 = to_i915(display->drm); 648 566 u32 val; 649 567 u8 valid_ranks = 0; 650 568 int i; ··· 666 582 bxt_get_dimm_info(&dimm, val); 667 583 type = bxt_get_dimm_type(val); 668 584 669 669 - drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN && 585 585 + drm_WARN_ON(display->drm, type != INTEL_DRAM_UNKNOWN && 670 586 dram_info->type != INTEL_DRAM_UNKNOWN && 671 587 dram_info->type != type); 672 588 673 673 - drm_dbg_kms(&i915->drm, 589 589 + drm_dbg_kms(display->drm, 674 590 "CH%u DIMM size: %u Gb, width: X%u, ranks: %u\n", 675 591 i - BXT_D_CR_DRP0_DUNIT_START, 676 592 dimm.size, dimm.width, dimm.ranks); ··· 683 599 } 684 600 685 601 if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) { 686 686 - drm_info(&i915->drm, "couldn't get memory information\n"); 602 602 + drm_info(display->drm, "couldn't get memory information\n"); 687 603 return -EINVAL; 688 604 } 689 605 690 606 return 0; 691 607 } 692 608 693 693 - static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv, 609 609 + static int icl_pcode_read_mem_global_info(struct intel_display *display, 694 610 struct dram_info *dram_info) 695 611 { 696 612 u32 val = 0; 697 613 int ret; 698 614 699 699 - ret = intel_pcode_read(&dev_priv->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | 615 615 + ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | 700 616 ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL); 701 617 if (ret) 702 618 return ret; 703 619 704 704 - if (GRAPHICS_VER(dev_priv) == 12) { 620 620 + if (DISPLAY_VER(display) >= 12) { 705 621 switch (val & 0xf) { 706 622 case 0: 707 623 dram_info->type = INTEL_DRAM_DDR4; ··· 752 668 return 0; 753 669 } 754 670 755 755 - static int gen11_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) 671 671 + static int gen11_get_dram_info(struct intel_display *display, struct dram_info *dram_info) 756 672 { 757 673 int ret; 758 674 759 759 - ret = skl_dram_get_channels_info(i915, dram_info); 675 675 + ret = skl_dram_get_channels_info(display, dram_info); 760 676 if (ret) 761 677 return ret; 762 678 763 763 - return icl_pcode_read_mem_global_info(i915, dram_info); 679 679 + return icl_pcode_read_mem_global_info(display, dram_info); 764 680 } 765 681 766 766 - static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) 682 682 + static int gen12_get_dram_info(struct intel_display *display, struct dram_info *dram_info) 767 683 { 768 768 - return icl_pcode_read_mem_global_info(i915, dram_info); 684 684 + return icl_pcode_read_mem_global_info(display, dram_info); 769 685 } 770 686 771 771 - static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) 687 687 + static int xelpdp_get_dram_info(struct intel_display *display, struct dram_info *dram_info) 772 688 { 773 773 - struct intel_display *display = i915->display; 689 689 + struct drm_i915_private *i915 = to_i915(display->drm); 774 690 u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL); 775 691 776 692 switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) { ··· 793 709 dram_info->type = INTEL_DRAM_LPDDR3; 794 710 break; 795 711 case 8: 796 796 - drm_WARN_ON(&i915->drm, !IS_DGFX(i915)); 712 712 + drm_WARN_ON(display->drm, !display->platform.dgfx); 797 713 dram_info->type = INTEL_DRAM_GDDR; 798 714 break; 799 715 case 9: 800 800 - drm_WARN_ON(&i915->drm, !IS_DGFX(i915)); 716 716 + drm_WARN_ON(display->drm, !display->platform.dgfx); 801 717 dram_info->type = INTEL_DRAM_GDDR_ECC; 802 718 break; 803 719 default: ··· 815 731 return 0; 816 732 } 817 733 818 818 - int intel_dram_detect(struct drm_i915_private *i915) 734 734 + int intel_dram_detect(struct intel_display *display) 819 735 { 820 820 - struct intel_display *display = i915->display; 821 736 struct dram_info *dram_info; 822 737 int ret; 823 738 824 824 - if (IS_DG2(i915) || !intel_display_device_present(display)) 739 739 + if (display->platform.dg2 || !HAS_DISPLAY(display)) 825 740 return 0; 826 741 827 827 - dram_info = drmm_kzalloc(&i915->drm, sizeof(*dram_info), GFP_KERNEL); 742 742 + dram_info = drmm_kzalloc(display->drm, sizeof(*dram_info), GFP_KERNEL); 828 743 if (!dram_info) 829 744 return -ENOMEM; 830 745 831 831 - i915->dram_info = dram_info; 746 746 + display->dram.info = dram_info; 832 747 833 748 if (DISPLAY_VER(display) >= 14) 834 834 - ret = xelpdp_get_dram_info(i915, dram_info); 835 835 - else if (GRAPHICS_VER(i915) >= 12) 836 836 - ret = gen12_get_dram_info(i915, dram_info); 837 837 - else if (GRAPHICS_VER(i915) >= 11) 838 838 - ret = gen11_get_dram_info(i915, dram_info); 839 839 - else if (IS_BROXTON(i915) || IS_GEMINILAKE(i915)) 840 840 - ret = bxt_get_dram_info(i915, dram_info); 841 841 - else if (GRAPHICS_VER(i915) >= 9) 842 842 - ret = skl_get_dram_info(i915, dram_info); 749 749 + ret = xelpdp_get_dram_info(display, dram_info); 750 750 + else if (DISPLAY_VER(display) >= 12) 751 751 + ret = gen12_get_dram_info(display, dram_info); 752 752 + else if (DISPLAY_VER(display) >= 11) 753 753 + ret = gen11_get_dram_info(display, dram_info); 754 754 + else if (display->platform.broxton || display->platform.geminilake) 755 755 + ret = bxt_get_dram_info(display, dram_info); 756 756 + else if (DISPLAY_VER(display) >= 9) 757 757 + ret = skl_get_dram_info(display, dram_info); 843 758 else 844 844 - ret = i915_get_dram_info(i915, dram_info); 759 759 + ret = i915_get_dram_info(display, dram_info); 845 760 846 846 - drm_dbg_kms(&i915->drm, "DRAM type: %s\n", 761 761 + drm_dbg_kms(display->drm, "DRAM type: %s\n", 847 762 intel_dram_type_str(dram_info->type)); 848 763 849 849 - drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels); 764 764 + drm_dbg_kms(display->drm, "DRAM channels: %u\n", dram_info->num_channels); 850 765 851 851 - drm_dbg_kms(&i915->drm, "Num QGV points %u\n", dram_info->num_qgv_points); 852 852 - drm_dbg_kms(&i915->drm, "Num PSF GV points %u\n", dram_info->num_psf_gv_points); 766 766 + drm_dbg_kms(display->drm, "Num QGV points %u\n", dram_info->num_qgv_points); 767 767 + drm_dbg_kms(display->drm, "Num PSF GV points %u\n", dram_info->num_psf_gv_points); 853 768 854 769 /* TODO: Do we want to abort probe on dram detection failures? */ 855 770 if (ret) ··· 862 779 * checks, and prefer not dereferencing on platforms that shouldn't look at dram 863 780 * info, to catch accidental and incorrect dram info checks. 864 781 */ 865 865 - const struct dram_info *intel_dram_info(struct drm_device *drm) 782 782 + const struct dram_info *intel_dram_info(struct intel_display *display) 866 783 { 867 867 - struct drm_i915_private *i915 = to_i915(drm); 868 868 - 869 869 - return i915->dram_info; 870 870 - } 871 871 - 872 872 - static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap) 873 873 - { 874 874 - static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; 875 875 - static const u8 sets[4] = { 1, 1, 2, 2 }; 876 876 - 877 877 - return EDRAM_NUM_BANKS(cap) * 878 878 - ways[EDRAM_WAYS_IDX(cap)] * 879 879 - sets[EDRAM_SETS_IDX(cap)]; 880 880 - } 881 881 - 882 882 - void intel_dram_edram_detect(struct drm_i915_private *i915) 883 883 - { 884 884 - u32 edram_cap = 0; 885 885 - 886 886 - if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9)) 887 887 - return; 888 888 - 889 889 - edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP); 890 890 - 891 891 - /* NB: We can't write IDICR yet because we don't have gt funcs set up */ 892 892 - 893 893 - if (!(edram_cap & EDRAM_ENABLED)) 894 894 - return; 895 895 - 896 896 - /* 897 897 - * The needed capability bits for size calculation are not there with 898 898 - * pre gen9 so return 128MB always. 899 899 - */ 900 900 - if (GRAPHICS_VER(i915) < 9) 901 901 - i915->edram_size_mb = 128; 902 902 - else 903 903 - i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap); 904 904 - 905 905 - drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb); 784 784 + return display->dram.info; 906 785 }

+5 -7

drivers/gpu/drm/i915/soc/intel_dram.h drivers/gpu/drm/i915/display/intel_dram.h

reviewed

··· 8 8 9 9 #include <linux/types.h> 10 10 11 11 - struct drm_i915_private; 12 12 - struct drm_device; 11 11 + struct intel_display; 13 12 14 13 struct dram_info { 15 14 enum intel_dram_type { ··· 34 35 bool has_16gb_dimms; 35 36 }; 36 37 37 37 - void intel_dram_edram_detect(struct drm_i915_private *i915); 38 38 - int intel_dram_detect(struct drm_i915_private *i915); 39 39 - unsigned int intel_fsb_freq(struct drm_i915_private *i915); 40 40 - unsigned int intel_mem_freq(struct drm_i915_private *i915); 41 41 - const struct dram_info *intel_dram_info(struct drm_device *drm); 38 38 + int intel_dram_detect(struct intel_display *display); 39 39 + unsigned int intel_fsb_freq(struct intel_display *display); 40 40 + unsigned int intel_mem_freq(struct intel_display *display); 41 41 + const struct dram_info *intel_dram_info(struct intel_display *display); 42 42 const char *intel_dram_type_str(enum intel_dram_type type); 43 43 44 44 #endif /* __INTEL_DRAM_H__ */

+7 -54

drivers/gpu/drm/i915/soc/intel_gmch.c drivers/gpu/drm/i915/i915_gmch.c

reviewed

··· 1 1 // SPDX-License-Identifier: MIT 2 2 - /* 3 3 - * Copyright © 2023 Intel Corporation 4 4 - */ 2 2 + /* Copyright © 2025 Intel Corporation */ 5 3 6 6 - #include <linux/pci.h> 7 4 #include <linux/pnp.h> 8 8 - #include <linux/vgaarb.h> 9 5 10 6 #include <drm/drm_managed.h> 11 7 #include <drm/drm_print.h> 12 12 - #include <drm/intel/i915_drm.h> 13 13 - 14 14 - #include "../display/intel_display_core.h" /* FIXME */ 15 8 16 9 #include "i915_drv.h" 17 17 - #include "intel_gmch.h" 10 10 + #include "i915_gmch.h" 18 11 #include "intel_pci_config.h" 19 12 20 20 - static void intel_gmch_bridge_release(struct drm_device *dev, void *bridge) 13 13 + static void i915_gmch_bridge_release(struct drm_device *dev, void *bridge) 21 14 { 22 15 pci_dev_put(bridge); 23 16 } 24 17 25 25 - int intel_gmch_bridge_setup(struct drm_i915_private *i915) 18 18 + int i915_gmch_bridge_setup(struct drm_i915_private *i915) 26 19 { 27 20 int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus); 28 21 ··· 25 32 return -EIO; 26 33 } 27 34 28 28 - return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release, 35 35 + return drmm_add_action_or_reset(&i915->drm, i915_gmch_bridge_release, 29 36 i915->gmch.pdev); 30 37 } 31 38 ··· 77 84 } 78 85 79 86 /* Setup MCHBAR if possible, return true if we should disable it again */ 80 80 - void intel_gmch_bar_setup(struct drm_i915_private *i915) 87 87 + void i915_gmch_bar_setup(struct drm_i915_private *i915) 81 88 { 82 89 u32 temp; 83 90 bool enabled; ··· 114 121 } 115 122 } 116 123 117 117 - void intel_gmch_bar_teardown(struct drm_i915_private *i915) 124 124 + void i915_gmch_bar_teardown(struct drm_i915_private *i915) 118 125 { 119 126 if (i915->gmch.mchbar_need_disable) { 120 127 if (IS_I915G(i915) || IS_I915GM(i915)) { ··· 138 145 139 146 if (i915->gmch.mch_res.start) 140 147 release_resource(&i915->gmch.mch_res); 141 141 - } 142 142 - 143 143 - int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode) 144 144 - { 145 145 - struct intel_display *display = i915->display; 146 146 - unsigned int reg = DISPLAY_VER(display) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; 147 147 - u16 gmch_ctrl; 148 148 - 149 149 - if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) { 150 150 - drm_err(&i915->drm, "failed to read control word\n"); 151 151 - return -EIO; 152 152 - } 153 153 - 154 154 - if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode) 155 155 - return 0; 156 156 - 157 157 - if (enable_decode) 158 158 - gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 159 159 - else 160 160 - gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 161 161 - 162 162 - if (pci_write_config_word(i915->gmch.pdev, reg, gmch_ctrl)) { 163 163 - drm_err(&i915->drm, "failed to write control word\n"); 164 164 - return -EIO; 165 165 - } 166 166 - 167 167 - return 0; 168 168 - } 169 169 - 170 170 - unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode) 171 171 - { 172 172 - struct drm_i915_private *i915 = pdev_to_i915(pdev); 173 173 - 174 174 - intel_gmch_vga_set_state(i915, enable_decode); 175 175 - 176 176 - if (enable_decode) 177 177 - return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 178 178 - VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 179 179 - else 180 180 - return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 181 148 }

-20

drivers/gpu/drm/i915/soc/intel_gmch.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2023 Intel Corporation 4 4 - */ 5 5 - 6 6 - #ifndef __INTEL_GMCH_H__ 7 7 - #define __INTEL_GMCH_H__ 8 8 - 9 9 - #include <linux/types.h> 10 10 - 11 11 - struct pci_dev; 12 12 - struct drm_i915_private; 13 13 - 14 14 - int intel_gmch_bridge_setup(struct drm_i915_private *i915); 15 15 - void intel_gmch_bar_setup(struct drm_i915_private *i915); 16 16 - void intel_gmch_bar_teardown(struct drm_i915_private *i915); 17 17 - int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode); 18 18 - unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode); 19 19 - 20 20 - #endif /* __INTEL_GMCH_H__ */

drivers/gpu/drm/i915/soc/intel_rom.c drivers/gpu/drm/i915/display/intel_rom.c

reviewed

drivers/gpu/drm/i915/soc/intel_rom.h drivers/gpu/drm/i915/display/intel_rom.h

reviewed

+1 -1

drivers/gpu/drm/i915/vlv_suspend.c

reviewed

··· 453 453 vlv_check_no_gt_access(dev_priv); 454 454 455 455 if (rpm_resume) 456 456 - intel_clock_gating_init(dev_priv); 456 456 + intel_clock_gating_init(&dev_priv->drm); 457 457 458 458 return ret; 459 459 }

+5 -14

drivers/gpu/drm/xe/Makefile

reviewed

··· 195 195 196 196 # i915 Display compat #defines and #includes 197 197 subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \ 198 198 - -I$(src)/display/ext \ 199 198 -I$(src)/compat-i915-headers \ 200 199 -I$(srctree)/drivers/gpu/drm/i915/display/ \ 201 200 -Ddrm_i915_private=xe_device 202 202 - 203 203 - # Rule to build SOC code shared with i915 204 204 - $(obj)/i915-soc/%.o: $(srctree)/drivers/gpu/drm/i915/soc/%.c FORCE 205 205 - $(call cmd,force_checksrc) 206 206 - $(call if_changed_rule,cc_o_c) 207 201 208 202 # Rule to build display code shared with i915 209 203 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE ··· 206 212 207 213 # Display code specific to xe 208 214 xe-$(CONFIG_DRM_XE_DISPLAY) += \ 209 209 - display/ext/i915_irq.o \ 210 215 display/intel_bo.o \ 211 216 display/intel_fb_bo.o \ 212 217 display/intel_fbdev_fb.o \ 213 218 display/xe_display.o \ 214 214 - display/xe_display_misc.o \ 215 219 display/xe_display_rpm.o \ 216 220 display/xe_display_wa.o \ 217 221 display/xe_dsb_buffer.o \ ··· 219 227 display/xe_plane_initial.o \ 220 228 display/xe_stolen.o \ 221 229 display/xe_tdf.o 222 222 - 223 223 - # SOC code shared with i915 224 224 - xe-$(CONFIG_DRM_XE_DISPLAY) += \ 225 225 - i915-soc/intel_dram.o \ 226 226 - i915-soc/intel_rom.o 227 230 228 231 # Display code shared with i915 229 232 xe-$(CONFIG_DRM_XE_DISPLAY) += \ ··· 254 267 i915-display/intel_display_power_map.o \ 255 268 i915-display/intel_display_power_well.o \ 256 269 i915-display/intel_display_rpm.o \ 270 270 + i915-display/intel_display_rps.o \ 257 271 i915-display/intel_display_trace.o \ 258 272 i915-display/intel_display_utils.o \ 259 273 i915-display/intel_display_wa.o \ ··· 271 283 i915-display/intel_dpll.o \ 272 284 i915-display/intel_dpll_mgr.o \ 273 285 i915-display/intel_dpt_common.o \ 286 286 + i915-display/intel_dram.o \ 274 287 i915-display/intel_drrs.o \ 275 288 i915-display/intel_dsb.o \ 276 289 i915-display/intel_dsi.o \ ··· 299 310 i915-display/intel_modeset_setup.o \ 300 311 i915-display/intel_modeset_verify.o \ 301 312 i915-display/intel_panel.o \ 313 313 + i915-display/intel_parent.o \ 314 314 + i915-display/intel_pch.o \ 302 315 i915-display/intel_pfit.o \ 303 316 i915-display/intel_plane.o \ 304 317 i915-display/intel_pmdemand.o \ 305 305 - i915-display/intel_pch.o \ 306 318 i915-display/intel_pps.o \ 307 319 i915-display/intel_psr.o \ 308 320 i915-display/intel_qp_tables.o \ 309 321 i915-display/intel_quirks.o \ 322 322 + i915-display/intel_rom.o \ 310 323 i915-display/intel_snps_hdmi_pll.o \ 311 324 i915-display/intel_snps_phy.o \ 312 325 i915-display/intel_tc.o \

-13

drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* Copyright © 2025 Intel Corporation */ 3 3 - 4 4 - #ifndef __I915_GEM_OBJECT_H__ 5 5 - #define __I915_GEM_OBJECT_H__ 6 6 - 7 7 - struct dma_fence; 8 8 - 9 9 - static inline void i915_gem_fence_wait_priority_display(struct dma_fence *fence) 10 10 - { 11 11 - } 12 12 - 13 13 - #endif

-40

drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_stolen.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2024 Intel Corporation 4 4 - */ 5 5 - 6 6 - #ifndef _I915_GEM_STOLEN_H_ 7 7 - #define _I915_GEM_STOLEN_H_ 8 8 - 9 9 - #include <linux/types.h> 10 10 - 11 11 - struct drm_device; 12 12 - struct intel_stolen_node; 13 13 - 14 14 - int i915_gem_stolen_insert_node_in_range(struct intel_stolen_node *node, u64 size, 15 15 - unsigned int align, u64 start, u64 end); 16 16 - 17 17 - int i915_gem_stolen_insert_node(struct intel_stolen_node *node, u64 size, 18 18 - unsigned int align); 19 19 - 20 20 - void i915_gem_stolen_remove_node(struct intel_stolen_node *node); 21 21 - 22 22 - bool i915_gem_stolen_initialized(struct drm_device *drm); 23 23 - 24 24 - bool i915_gem_stolen_node_allocated(const struct intel_stolen_node *node); 25 25 - 26 26 - u32 i915_gem_stolen_node_offset(struct intel_stolen_node *node); 27 27 - 28 28 - u64 i915_gem_stolen_area_address(struct drm_device *drm); 29 29 - 30 30 - u64 i915_gem_stolen_area_size(struct drm_device *drm); 31 31 - 32 32 - u64 i915_gem_stolen_node_address(struct intel_stolen_node *node); 33 33 - 34 34 - u64 i915_gem_stolen_node_size(const struct intel_stolen_node *node); 35 35 - 36 36 - struct intel_stolen_node *i915_gem_stolen_node_alloc(struct drm_device *drm); 37 37 - 38 38 - void i915_gem_stolen_node_free(const struct intel_stolen_node *node); 39 39 - 40 40 - #endif

-11

drivers/gpu/drm/xe/compat-i915-headers/gt/intel_gt_types.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2023 Intel Corporation 4 4 - */ 5 5 - 6 6 - #ifndef __INTEL_GT_TYPES__ 7 7 - #define __INTEL_GT_TYPES__ 8 8 - 9 9 - #define intel_gt_support_legacy_fencing(gt) 0 10 10 - 11 11 - #endif

-22

drivers/gpu/drm/xe/compat-i915-headers/i915_active.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2022 Intel Corporation 4 4 - */ 5 5 - 6 6 - #ifndef _I915_ACTIVE_H_ 7 7 - #define _I915_ACTIVE_H_ 8 8 - 9 9 - #include "i915_active_types.h" 10 10 - 11 11 - static inline void i915_active_init(struct i915_active *ref, 12 12 - int (*active)(struct i915_active *ref), 13 13 - void (*retire)(struct i915_active *ref), 14 14 - unsigned long flags) 15 15 - { 16 16 - (void) active; 17 17 - (void) retire; 18 18 - } 19 19 - 20 20 - #define i915_active_fini(active) do { } while (0) 21 21 - 22 22 - #endif

-13

drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h

reviewed

··· 1 1 - /* 2 2 - * SPDX-License-Identifier: MIT 3 3 - * 4 4 - * Copyright © 2019 Intel Corporation 5 5 - */ 6 6 - 7 7 - #ifndef _I915_ACTIVE_TYPES_H_ 8 8 - #define _I915_ACTIVE_TYPES_H_ 9 9 - 10 10 - struct i915_active {}; 11 11 - #define I915_ACTIVE_RETIRE_SLEEPS 0 12 12 - 13 13 - #endif /* _I915_ACTIVE_TYPES_H_ */

-15

drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h

reviewed

··· 19 19 return container_of(dev, struct drm_i915_private, drm); 20 20 } 21 21 22 22 - /* compat platform checks only for soc/ usage */ 23 23 - #define IS_PLATFORM(xe, x) ((xe)->info.platform == x) 24 24 - #define IS_I915G(dev_priv) (dev_priv && 0) 25 25 - #define IS_I915GM(dev_priv) (dev_priv && 0) 26 26 - #define IS_PINEVIEW(dev_priv) (dev_priv && 0) 27 27 - #define IS_VALLEYVIEW(dev_priv) (dev_priv && 0) 28 28 - #define IS_CHERRYVIEW(dev_priv) (dev_priv && 0) 29 29 - #define IS_HASWELL(dev_priv) (dev_priv && 0) 30 30 - #define IS_BROADWELL(dev_priv) (dev_priv && 0) 31 31 - #define IS_BROXTON(dev_priv) (dev_priv && 0) 32 32 - #define IS_GEMINILAKE(dev_priv) (dev_priv && 0) 33 33 - #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) 34 34 - 35 35 - #define IS_MOBILE(xe) (xe && 0) 36 36 - 37 22 #endif

-6

drivers/gpu/drm/xe/compat-i915-headers/i915_irq.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2023 Intel Corporation 4 4 - */ 5 5 - 6 6 - #include "../../i915/i915_irq.h"

-6

drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h

reviewed

··· 3 3 * Copyright © 2023 Intel Corporation 4 4 */ 5 5 6 6 - /* for soc/ */ 7 7 - #ifndef MISSING_CASE 8 8 - #define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \ 9 9 - __stringify(x), (long)(x)) 10 10 - #endif 11 11 - 12 6 /* for a couple of users under i915/display */ 13 7 #define i915_inject_probe_failure(unused) ((unused) && 0)

-18

drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2023 Intel Corporation 4 4 - */ 5 5 - 6 6 - #ifndef _I915_VGPU_H_ 7 7 - #define _I915_VGPU_H_ 8 8 - 9 9 - #include <linux/types.h> 10 10 - 11 11 - struct drm_i915_private; 12 12 - 13 13 - static inline bool intel_vgpu_active(struct drm_i915_private *i915) 14 14 - { 15 15 - return false; 16 16 - } 17 17 - 18 18 - #endif /* _I915_VGPU_H_ */

-10

drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2023 Intel Corporation 4 4 - */ 5 5 - 6 6 - #include <linux/types.h> 7 7 - 8 8 - typedef struct ref_tracker *intel_wakeref_t; 9 9 - 10 10 - #define INTEL_WAKEREF_DEF ERR_PTR(-ENOENT)

-29

drivers/gpu/drm/xe/compat-i915-headers/pxp/intel_pxp.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2023 Intel Corporation 4 4 - */ 5 5 - 6 6 - #ifndef __INTEL_PXP_H__ 7 7 - #define __INTEL_PXP_H__ 8 8 - 9 9 - #include <linux/errno.h> 10 10 - #include <linux/types.h> 11 11 - 12 12 - #include "xe_pxp.h" 13 13 - 14 14 - struct drm_gem_object; 15 15 - 16 16 - static inline int intel_pxp_key_check(struct drm_gem_object *obj, bool assign) 17 17 - { 18 18 - /* 19 19 - * The assign variable is used in i915 to assign the key to the BO at 20 20 - * first submission time. In Xe the key is instead assigned at BO 21 21 - * creation time, so the assign variable must always be false. 22 22 - */ 23 23 - if (assign) 24 24 - return -EINVAL; 25 25 - 26 26 - return xe_pxp_obj_key_check(obj); 27 27 - } 28 28 - 29 29 - #endif

-6

drivers/gpu/drm/xe/compat-i915-headers/soc/intel_dram.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2023 Intel Corporation 4 4 - */ 5 5 - 6 6 - #include "../../../i915/soc/intel_dram.h"

-6

drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2023 Intel Corporation 4 4 - */ 5 5 - 6 6 - #include "../../../i915/soc/intel_gmch.h"

-6

drivers/gpu/drm/xe/compat-i915-headers/soc/intel_rom.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2024 Intel Corporation 4 4 - */ 5 5 - 6 6 - #include "../../../i915/soc/intel_rom.h"

-85

drivers/gpu/drm/xe/display/ext/i915_irq.c

reviewed

··· 1 1 - // SPDX-License-Identifier: MIT 2 2 - /* 3 3 - * Copyright © 2023 Intel Corporation 4 4 - */ 5 5 - 6 6 - #include "i915_irq.h" 7 7 - #include "i915_reg.h" 8 8 - #include "intel_uncore.h" 9 9 - 10 10 - void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs) 11 11 - { 12 12 - intel_uncore_write(uncore, regs.imr, 0xffffffff); 13 13 - intel_uncore_posting_read(uncore, regs.imr); 14 14 - 15 15 - intel_uncore_write(uncore, regs.ier, 0); 16 16 - 17 17 - /* IIR can theoretically queue up two events. Be paranoid. */ 18 18 - intel_uncore_write(uncore, regs.iir, 0xffffffff); 19 19 - intel_uncore_posting_read(uncore, regs.iir); 20 20 - intel_uncore_write(uncore, regs.iir, 0xffffffff); 21 21 - intel_uncore_posting_read(uncore, regs.iir); 22 22 - } 23 23 - 24 24 - /* 25 25 - * We should clear IMR at preinstall/uninstall, and just check at postinstall. 26 26 - */ 27 27 - void gen2_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg) 28 28 - { 29 29 - struct xe_device *xe = container_of(uncore, struct xe_device, uncore); 30 30 - u32 val = intel_uncore_read(uncore, reg); 31 31 - 32 32 - if (val == 0) 33 33 - return; 34 34 - 35 35 - drm_WARN(&xe->drm, 1, 36 36 - "Interrupt register 0x%x is not zero: 0x%08x\n", 37 37 - i915_mmio_reg_offset(reg), val); 38 38 - intel_uncore_write(uncore, reg, 0xffffffff); 39 39 - intel_uncore_posting_read(uncore, reg); 40 40 - intel_uncore_write(uncore, reg, 0xffffffff); 41 41 - intel_uncore_posting_read(uncore, reg); 42 42 - } 43 43 - 44 44 - void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs, 45 45 - u32 imr_val, u32 ier_val) 46 46 - { 47 47 - gen2_assert_iir_is_zero(uncore, regs.iir); 48 48 - 49 49 - intel_uncore_write(uncore, regs.ier, ier_val); 50 50 - intel_uncore_write(uncore, regs.imr, imr_val); 51 51 - intel_uncore_posting_read(uncore, regs.imr); 52 52 - } 53 53 - 54 54 - void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs) 55 55 - { 56 56 - intel_uncore_write(uncore, regs.emr, 0xffffffff); 57 57 - intel_uncore_posting_read(uncore, regs.emr); 58 58 - 59 59 - intel_uncore_write(uncore, regs.eir, 0xffffffff); 60 60 - intel_uncore_posting_read(uncore, regs.eir); 61 61 - intel_uncore_write(uncore, regs.eir, 0xffffffff); 62 62 - intel_uncore_posting_read(uncore, regs.eir); 63 63 - } 64 64 - 65 65 - void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs, 66 66 - u32 emr_val) 67 67 - { 68 68 - intel_uncore_write(uncore, regs.eir, 0xffffffff); 69 69 - intel_uncore_posting_read(uncore, regs.eir); 70 70 - intel_uncore_write(uncore, regs.eir, 0xffffffff); 71 71 - intel_uncore_posting_read(uncore, regs.eir); 72 72 - 73 73 - intel_uncore_write(uncore, regs.emr, emr_val); 74 74 - intel_uncore_posting_read(uncore, regs.emr); 75 75 - } 76 76 - 77 77 - bool intel_irqs_enabled(struct xe_device *xe) 78 78 - { 79 79 - return atomic_read(&xe->irq.enabled); 80 80 - } 81 81 - 82 82 - void intel_synchronize_irq(struct xe_device *xe) 83 83 - { 84 84 - synchronize_irq(to_pci_dev(xe->drm.dev)->irq); 85 85 - }

+7 -1

drivers/gpu/drm/xe/display/intel_bo.c

reviewed

··· 3 3 4 4 #include <drm/drm_gem.h> 5 5 6 6 - #include "xe_bo.h" 7 6 #include "intel_bo.h" 8 7 #include "intel_frontbuffer.h" 8 8 + #include "xe_bo.h" 9 9 + #include "xe_pxp.h" 9 10 10 11 bool intel_bo_is_tiled(struct drm_gem_object *obj) 11 12 { ··· 28 27 bool intel_bo_is_protected(struct drm_gem_object *obj) 29 28 { 30 29 return xe_bo_is_protected(gem_to_xe_bo(obj)); 30 30 + } 31 31 + 32 32 + int intel_bo_key_check(struct drm_gem_object *obj) 33 33 + { 34 34 + return xe_pxp_obj_key_check(obj); 31 35 } 32 36 33 37 int intel_bo_fb_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)

+26 -2

drivers/gpu/drm/xe/display/xe_display.c

reviewed

··· 17 17 #include <drm/intel/display_parent_interface.h> 18 18 #include <uapi/drm/xe_drm.h> 19 19 20 20 - #include "soc/intel_dram.h" 21 20 #include "intel_acpi.h" 22 21 #include "intel_audio.h" 23 22 #include "intel_bw.h" ··· 28 29 #include "intel_dmc.h" 29 30 #include "intel_dmc_wl.h" 30 31 #include "intel_dp.h" 32 32 + #include "intel_dram.h" 31 33 #include "intel_encoder.h" 32 34 #include "intel_fbdev.h" 33 35 #include "intel_hdcp.h" ··· 36 36 #include "intel_opregion.h" 37 37 #include "skl_watermark.h" 38 38 #include "xe_display_rpm.h" 39 39 + #include "xe_hdcp_gsc.h" 39 40 #include "xe_module.h" 41 41 + #include "xe_panic.h" 42 42 + #include "xe_stolen.h" 40 43 41 44 /* Ensure drm and display members are placed properly. */ 42 45 INTEL_DISPLAY_MEMBER_STATIC_ASSERT(struct xe_device, drm, display); ··· 125 122 * Fill the dram structure to get the system dram info. This will be 126 123 * used for memory latency calculation. 127 124 */ 128 128 - err = intel_dram_detect(xe); 125 125 + err = intel_dram_detect(display); 129 126 if (err) 130 127 goto err_opregion; 131 128 ··· 519 516 intel_display_device_remove(display); 520 517 } 521 518 519 519 + static bool irq_enabled(struct drm_device *drm) 520 520 + { 521 521 + struct xe_device *xe = to_xe_device(drm); 522 522 + 523 523 + return atomic_read(&xe->irq.enabled); 524 524 + } 525 525 + 526 526 + static void irq_synchronize(struct drm_device *drm) 527 527 + { 528 528 + synchronize_irq(to_pci_dev(drm->dev)->irq); 529 529 + } 530 530 + 531 531 + static const struct intel_display_irq_interface xe_display_irq_interface = { 532 532 + .enabled = irq_enabled, 533 533 + .synchronize = irq_synchronize, 534 534 + }; 535 535 + 522 536 static const struct intel_display_parent_interface parent = { 537 537 + .hdcp = &xe_display_hdcp_interface, 538 538 + .irq = &xe_display_irq_interface, 539 539 + .panic = &xe_display_panic_interface, 523 540 .rpm = &xe_display_rpm_interface, 541 541 + .stolen = &xe_display_stolen_interface, 524 542 }; 525 543 526 544 /**

-16

drivers/gpu/drm/xe/display/xe_display_misc.c

reviewed

··· 1 1 - // SPDX-License-Identifier: MIT 2 2 - /* 3 3 - * Copyright © 2023 Intel Corporation 4 4 - */ 5 5 - 6 6 - #include "intel_display_types.h" 7 7 - 8 8 - struct pci_dev; 9 9 - 10 10 - unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode); 11 11 - 12 12 - unsigned int intel_gmch_vga_set_decode(struct pci_dev *pdev, bool enable_decode) 13 13 - { 14 14 - /* ToDo: Implement the actual handling of vga decode */ 15 15 - return 0; 16 16 - }

+3

drivers/gpu/drm/xe/display/xe_display_rpm.c

reviewed

··· 9 9 #include "xe_device_types.h" 10 10 #include "xe_pm.h" 11 11 12 12 + /* -ENOENT means we got the ref, but there's no tracking */ 13 13 + #define INTEL_WAKEREF_DEF ERR_PTR(-ENOENT) 14 14 + 12 15 static struct ref_tracker *xe_display_rpm_get(const struct drm_device *drm) 13 16 { 14 17 return xe_pm_runtime_resume_and_get(to_xe_device(drm)) ? INTEL_WAKEREF_DEF : NULL;

+29 -20

drivers/gpu/drm/xe/display/xe_dsb_buffer.c

reviewed

··· 3 3 * Copyright 2023, Intel Corporation. 4 4 */ 5 5 6 6 - #include "i915_vma.h" 7 7 - #include "intel_display_types.h" 8 6 #include "intel_dsb_buffer.h" 9 7 #include "xe_bo.h" 10 8 #include "xe_device.h" 11 9 #include "xe_device_types.h" 12 10 11 11 + struct intel_dsb_buffer { 12 12 + u32 *cmd_buf; 13 13 + struct xe_bo *bo; 14 14 + size_t buf_size; 15 15 + }; 16 16 + 13 17 u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf) 14 18 { 15 15 - return xe_bo_ggtt_addr(dsb_buf->vma->bo); 19 19 + return xe_bo_ggtt_addr(dsb_buf->bo); 16 20 } 17 21 18 22 void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val) 19 23 { 20 20 - iosys_map_wr(&dsb_buf->vma->bo->vmap, idx * 4, u32, val); 24 24 + iosys_map_wr(&dsb_buf->bo->vmap, idx * 4, u32, val); 21 25 } 22 26 23 27 u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx) 24 28 { 25 25 - return iosys_map_rd(&dsb_buf->vma->bo->vmap, idx * 4, u32); 29 29 + return iosys_map_rd(&dsb_buf->bo->vmap, idx * 4, u32); 26 30 } 27 31 28 32 void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size) 29 33 { 30 34 WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf)); 31 35 32 32 - iosys_map_memset(&dsb_buf->vma->bo->vmap, idx * 4, val, size); 36 36 + iosys_map_memset(&dsb_buf->bo->vmap, idx * 4, val, size); 33 37 } 34 38 35 35 - bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size) 39 39 + struct intel_dsb_buffer *intel_dsb_buffer_create(struct drm_device *drm, size_t size) 36 40 { 37 37 - struct xe_device *xe = to_xe_device(crtc->base.dev); 41 41 + struct xe_device *xe = to_xe_device(drm); 42 42 + struct intel_dsb_buffer *dsb_buf; 38 43 struct xe_bo *obj; 39 39 - struct i915_vma *vma; 44 44 + int ret; 40 45 41 41 - vma = kzalloc(sizeof(*vma), GFP_KERNEL); 42 42 - if (!vma) 43 43 - return false; 46 46 + dsb_buf = kzalloc(sizeof(*dsb_buf), GFP_KERNEL); 47 47 + if (!dsb_buf) 48 48 + return ERR_PTR(-ENOMEM); 44 49 45 50 /* Set scanout flag for WC mapping */ 46 51 obj = xe_bo_create_pin_map_novm(xe, xe_device_get_root_tile(xe), ··· 54 49 XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) | 55 50 XE_BO_FLAG_SCANOUT | XE_BO_FLAG_GGTT, false); 56 51 if (IS_ERR(obj)) { 57 57 - kfree(vma); 58 58 - return false; 52 52 + ret = PTR_ERR(obj); 53 53 + goto err_pin_map; 59 54 } 60 55 61 61 - vma->bo = obj; 62 62 - dsb_buf->vma = vma; 56 56 + dsb_buf->bo = obj; 63 57 dsb_buf->buf_size = size; 64 58 65 65 - return true; 59 59 + return dsb_buf; 60 60 + 61 61 + err_pin_map: 62 62 + kfree(dsb_buf); 63 63 + 64 64 + return ERR_PTR(ret); 66 65 } 67 66 68 67 void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf) 69 68 { 70 70 - xe_bo_unpin_map_no_vm(dsb_buf->vma->bo); 71 71 - kfree(dsb_buf->vma); 69 69 + xe_bo_unpin_map_no_vm(dsb_buf->bo); 70 70 + kfree(dsb_buf); 72 71 } 73 72 74 73 void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf) 75 74 { 76 76 - struct xe_device *xe = dsb_buf->vma->bo->tile->xe; 75 75 + struct xe_device *xe = dsb_buf->bo->tile->xe; 77 76 78 77 /* 79 78 * The memory barrier here is to ensure coherency of DSB vs MMIO,

+18 -9

drivers/gpu/drm/xe/display/xe_hdcp_gsc.c

reviewed

··· 3 3 * Copyright 2023, Intel Corporation. 4 4 */ 5 5 6 6 - #include <drm/drm_print.h> 7 7 - #include <drm/intel/i915_hdcp_interface.h> 8 6 #include <linux/delay.h> 9 7 8 8 + #include <drm/drm_print.h> 9 9 + #include <drm/intel/display_parent_interface.h> 10 10 + #include <drm/intel/i915_hdcp_interface.h> 11 11 + 10 12 #include "abi/gsc_command_header_abi.h" 11 11 - #include "intel_hdcp_gsc.h" 12 13 #include "xe_bo.h" 13 14 #include "xe_device.h" 14 15 #include "xe_device_types.h" 15 16 #include "xe_force_wake.h" 16 17 #include "xe_gsc_proxy.h" 17 18 #include "xe_gsc_submit.h" 19 19 + #include "xe_hdcp_gsc.h" 18 20 #include "xe_map.h" 19 21 #include "xe_pm.h" 20 22 #include "xe_uc_fw.h" ··· 32 30 33 31 #define HDCP_GSC_HEADER_SIZE sizeof(struct intel_gsc_mtl_header) 34 32 35 35 - bool intel_hdcp_gsc_check_status(struct drm_device *drm) 33 33 + static bool intel_hdcp_gsc_check_status(struct drm_device *drm) 36 34 { 37 35 struct xe_device *xe = to_xe_device(drm); 38 36 struct xe_tile *tile = xe_device_get_root_tile(xe); ··· 98 96 return ret; 99 97 } 100 98 101 101 - struct intel_hdcp_gsc_context *intel_hdcp_gsc_context_alloc(struct drm_device *drm) 99 99 + static struct intel_hdcp_gsc_context *intel_hdcp_gsc_context_alloc(struct drm_device *drm) 102 100 { 103 101 struct xe_device *xe = to_xe_device(drm); 104 102 struct intel_hdcp_gsc_context *gsc_context; ··· 122 120 return gsc_context; 123 121 } 124 122 125 125 - void intel_hdcp_gsc_context_free(struct intel_hdcp_gsc_context *gsc_context) 123 123 + static void intel_hdcp_gsc_context_free(struct intel_hdcp_gsc_context *gsc_context) 126 124 { 127 125 if (!gsc_context) 128 126 return; ··· 157 155 return ret; 158 156 } 159 157 160 160 - ssize_t intel_hdcp_gsc_msg_send(struct intel_hdcp_gsc_context *gsc_context, 161 161 - void *msg_in, size_t msg_in_len, 162 162 - void *msg_out, size_t msg_out_len) 158 158 + static ssize_t intel_hdcp_gsc_msg_send(struct intel_hdcp_gsc_context *gsc_context, 159 159 + void *msg_in, size_t msg_in_len, 160 160 + void *msg_out, size_t msg_out_len) 163 161 { 164 162 struct xe_device *xe = gsc_context->xe; 165 163 const size_t max_msg_size = PAGE_SIZE - HDCP_GSC_HEADER_SIZE; ··· 213 211 xe_pm_runtime_put(xe); 214 212 return ret; 215 213 } 214 214 + 215 215 + const struct intel_display_hdcp_interface xe_display_hdcp_interface = { 216 216 + .gsc_msg_send = intel_hdcp_gsc_msg_send, 217 217 + .gsc_check_status = intel_hdcp_gsc_check_status, 218 218 + .gsc_context_alloc = intel_hdcp_gsc_context_alloc, 219 219 + .gsc_context_free = intel_hdcp_gsc_context_free, 220 220 + };

+9

drivers/gpu/drm/xe/display/xe_hdcp_gsc.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #ifndef __XE_HDCP_GSC_H__ 5 5 + #define __XE_HDCP_GSC_H__ 6 6 + 7 7 + extern const struct intel_display_hdcp_interface xe_display_hdcp_interface; 8 8 + 9 9 + #endif

+9 -7

drivers/gpu/drm/xe/display/xe_panic.c

reviewed

··· 3 3 4 4 #include <drm/drm_cache.h> 5 5 #include <drm/drm_panic.h> 6 6 + #include <drm/intel/display_parent_interface.h> 6 7 7 8 #include "intel_display_types.h" 8 9 #include "intel_fb.h" 9 9 - #include "intel_panic.h" 10 10 #include "xe_bo.h" 11 11 + #include "xe_panic.h" 11 12 #include "xe_res_cursor.h" 12 13 13 14 struct intel_panic { ··· 75 74 iosys_map_wr(&panic->vmap, offset, u32, color); 76 75 } 77 76 78 78 - struct intel_panic *intel_panic_alloc(void) 77 77 + static struct intel_panic *xe_panic_alloc(void) 79 78 { 80 79 struct intel_panic *panic; 81 80 ··· 84 83 return panic; 85 84 } 86 85 87 87 - int intel_panic_setup(struct intel_panic *panic, struct drm_scanout_buffer *sb) 86 86 + static int xe_panic_setup(struct intel_panic *panic, struct drm_scanout_buffer *sb) 88 87 { 89 88 struct intel_framebuffer *fb = (struct intel_framebuffer *)sb->private; 90 89 struct xe_bo *bo = gem_to_xe_bo(intel_fb_bo(&fb->base)); ··· 97 96 return 0; 98 97 } 99 98 100 100 - void intel_panic_finish(struct intel_panic *panic) 101 101 - { 102 102 - xe_panic_kunmap(panic); 103 103 - } 99 99 + const struct intel_display_panic_interface xe_display_panic_interface = { 100 100 + .alloc = xe_panic_alloc, 101 101 + .setup = xe_panic_setup, 102 102 + .finish = xe_panic_kunmap, 103 103 + };

+9

drivers/gpu/drm/xe/display/xe_panic.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #ifndef __XE_PANIC_H__ 5 5 + #define __XE_PANIC_H__ 6 6 + 7 7 + extern const struct intel_display_panic_interface xe_display_panic_interface; 8 8 + 9 9 + #endif

+4 -2

drivers/gpu/drm/xe/display/xe_plane_initial.c

reviewed

··· 58 58 const struct intel_crtc_state *crtc_state = 59 59 to_intel_crtc_state(crtc->base.state); 60 60 61 61 - if (!crtc_state->uapi.active) 61 61 + if (!crtc_state->hw.active) 62 62 continue; 63 63 64 64 if (!plane_state->ggtt_vma) ··· 290 290 struct intel_crtc *crtc; 291 291 292 292 for_each_intel_crtc(display->drm, crtc) { 293 293 + const struct intel_crtc_state *crtc_state = 294 294 + to_intel_crtc_state(crtc->base.state); 293 295 struct intel_initial_plane_config *plane_config = 294 296 &plane_configs[crtc->pipe]; 295 297 296 296 - if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 298 298 + if (!crtc_state->hw.active) 297 299 continue; 298 300 299 301 /*

+26 -36

drivers/gpu/drm/xe/display/xe_stolen.c

reviewed

··· 1 1 // SPDX-License-Identifier: MIT 2 2 /* Copyright © 2025 Intel Corporation */ 3 3 4 4 - #include "gem/i915_gem_stolen.h" 4 4 + #include <drm/intel/display_parent_interface.h> 5 5 + 5 6 #include "xe_res_cursor.h" 7 7 + #include "xe_stolen.h" 6 8 #include "xe_ttm_stolen_mgr.h" 7 9 #include "xe_validation.h" 8 10 ··· 13 11 struct xe_bo *bo; 14 12 }; 15 13 16 16 - int i915_gem_stolen_insert_node_in_range(struct intel_stolen_node *node, u64 size, 17 17 - unsigned int align, u64 start, u64 end) 14 14 + static int xe_stolen_insert_node_in_range(struct intel_stolen_node *node, u64 size, 15 15 + unsigned int align, u64 start, u64 end) 18 16 { 19 17 struct xe_device *xe = node->xe; 20 18 ··· 43 41 return err; 44 42 } 45 43 46 46 - int i915_gem_stolen_insert_node(struct intel_stolen_node *node, u64 size, unsigned int align) 47 47 - { 48 48 - /* Not used on xe */ 49 49 - WARN_ON(1); 50 50 - 51 51 - return -ENODEV; 52 52 - } 53 53 - 54 54 - void i915_gem_stolen_remove_node(struct intel_stolen_node *node) 44 44 + static void xe_stolen_remove_node(struct intel_stolen_node *node) 55 45 { 56 46 xe_bo_unpin_map_no_vm(node->bo); 57 47 node->bo = NULL; 58 48 } 59 49 60 60 - bool i915_gem_stolen_initialized(struct drm_device *drm) 50 50 + static bool xe_stolen_initialized(struct drm_device *drm) 61 51 { 62 52 struct xe_device *xe = to_xe_device(drm); 63 53 64 54 return ttm_manager_type(&xe->ttm, XE_PL_STOLEN); 65 55 } 66 56 67 67 - bool i915_gem_stolen_node_allocated(const struct intel_stolen_node *node) 57 57 + static bool xe_stolen_node_allocated(const struct intel_stolen_node *node) 68 58 { 69 59 return node->bo; 70 60 } 71 61 72 72 - u32 i915_gem_stolen_node_offset(struct intel_stolen_node *node) 62 62 + static u64 xe_stolen_node_offset(const struct intel_stolen_node *node) 73 63 { 74 64 struct xe_res_cursor res; 75 65 ··· 69 75 return res.start; 70 76 } 71 77 72 72 - /* Used for < gen4. These are not supported by Xe */ 73 73 - u64 i915_gem_stolen_area_address(struct drm_device *drm) 74 74 - { 75 75 - WARN_ON(1); 76 76 - 77 77 - return 0; 78 78 - } 79 79 - 80 80 - /* Used for gen9 specific WA. Gen9 is not supported by Xe */ 81 81 - u64 i915_gem_stolen_area_size(struct drm_device *drm) 82 82 - { 83 83 - WARN_ON(1); 84 84 - 85 85 - return 0; 86 86 - } 87 87 - 88 88 - u64 i915_gem_stolen_node_address(struct intel_stolen_node *node) 78 78 + static u64 xe_stolen_node_address(const struct intel_stolen_node *node) 89 79 { 90 80 struct xe_device *xe = node->xe; 91 81 92 92 - return xe_ttm_stolen_gpu_offset(xe) + i915_gem_stolen_node_offset(node); 82 82 + return xe_ttm_stolen_gpu_offset(xe) + xe_stolen_node_offset(node); 93 83 } 94 84 95 95 - u64 i915_gem_stolen_node_size(const struct intel_stolen_node *node) 85 85 + static u64 xe_stolen_node_size(const struct intel_stolen_node *node) 96 86 { 97 87 return node->bo->ttm.base.size; 98 88 } 99 89 100 100 - struct intel_stolen_node *i915_gem_stolen_node_alloc(struct drm_device *drm) 90 90 + static struct intel_stolen_node *xe_stolen_node_alloc(struct drm_device *drm) 101 91 { 102 92 struct xe_device *xe = to_xe_device(drm); 103 93 struct intel_stolen_node *node; ··· 95 117 return node; 96 118 } 97 119 98 98 - void i915_gem_stolen_node_free(const struct intel_stolen_node *node) 120 120 + static void xe_stolen_node_free(const struct intel_stolen_node *node) 99 121 { 100 122 kfree(node); 101 123 } 124 124 + 125 125 + const struct intel_display_stolen_interface xe_display_stolen_interface = { 126 126 + .insert_node_in_range = xe_stolen_insert_node_in_range, 127 127 + .remove_node = xe_stolen_remove_node, 128 128 + .initialized = xe_stolen_initialized, 129 129 + .node_allocated = xe_stolen_node_allocated, 130 130 + .node_offset = xe_stolen_node_offset, 131 131 + .node_address = xe_stolen_node_address, 132 132 + .node_size = xe_stolen_node_size, 133 133 + .node_alloc = xe_stolen_node_alloc, 134 134 + .node_free = xe_stolen_node_free, 135 135 + };

+9

drivers/gpu/drm/xe/display/xe_stolen.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* Copyright © 2025 Intel Corporation */ 3 3 + 4 4 + #ifndef __XE_STOLEN_H__ 5 5 + #define __XE_STOLEN_H__ 6 6 + 7 7 + extern const struct intel_display_stolen_interface xe_display_stolen_interface; 8 8 + 9 9 + #endif

-8

drivers/gpu/drm/xe/xe_device_types.h

reviewed

··· 35 35 #define TEST_VM_OPS_ERROR 36 36 #endif 37 37 38 38 - struct dram_info; 39 38 struct intel_display; 40 39 struct intel_dg_nvm_dev; 41 40 struct xe_ggtt; ··· 647 648 * drm_i915_private during build. After cleanup these should go away, 648 649 * migrating to the right sub-structs 649 650 */ 650 650 - const struct dram_info *dram_info; 651 651 - 652 652 - /* 653 653 - * edram size in MB. 654 654 - * Cannot be determined by PCIID. You must always read a register. 655 655 - */ 656 656 - u32 edram_size_mb; 657 651 658 652 struct intel_uncore { 659 653 spinlock_t lock;

+3

include/drm/display/drm_dp_helper.h

reviewed

··· 206 206 207 207 /* DP/eDP DSC support */ 208 208 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 209 209 + u32 drm_dp_dsc_slice_count_to_mask(int slice_count); 210 210 + u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 211 211 + bool is_edp); 209 212 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 210 213 bool is_edp); 211 214 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);

+87

include/drm/intel/display_parent_interface.h

reviewed

··· 6 6 7 7 #include <linux/types.h> 8 8 9 9 + struct dma_fence; 9 10 struct drm_device; 11 11 + struct drm_scanout_buffer; 12 12 + struct intel_hdcp_gsc_context; 13 13 + struct intel_panic; 14 14 + struct intel_stolen_node; 10 15 struct ref_tracker; 16 16 + 17 17 + /* Keep struct definitions sorted */ 18 18 + 19 19 + struct intel_display_hdcp_interface { 20 20 + ssize_t (*gsc_msg_send)(struct intel_hdcp_gsc_context *gsc_context, 21 21 + void *msg_in, size_t msg_in_len, 22 22 + void *msg_out, size_t msg_out_len); 23 23 + bool (*gsc_check_status)(struct drm_device *drm); 24 24 + struct intel_hdcp_gsc_context *(*gsc_context_alloc)(struct drm_device *drm); 25 25 + void (*gsc_context_free)(struct intel_hdcp_gsc_context *gsc_context); 26 26 + }; 27 27 + 28 28 + struct intel_display_irq_interface { 29 29 + bool (*enabled)(struct drm_device *drm); 30 30 + void (*synchronize)(struct drm_device *drm); 31 31 + }; 32 32 + 33 33 + struct intel_display_panic_interface { 34 34 + struct intel_panic *(*alloc)(void); 35 35 + int (*setup)(struct intel_panic *panic, struct drm_scanout_buffer *sb); 36 36 + void (*finish)(struct intel_panic *panic); 37 37 + }; 38 38 + 39 39 + struct intel_display_pc8_interface { 40 40 + void (*block)(struct drm_device *drm); 41 41 + void (*unblock)(struct drm_device *drm); 42 42 + }; 11 43 12 44 struct intel_display_rpm_interface { 13 45 struct ref_tracker *(*get)(const struct drm_device *drm); ··· 57 25 void (*assert_unblock)(const struct drm_device *drm); 58 26 }; 59 27 28 28 + struct intel_display_rps_interface { 29 29 + void (*boost_if_not_started)(struct dma_fence *fence); 30 30 + void (*mark_interactive)(struct drm_device *drm, bool interactive); 31 31 + void (*ilk_irq_handler)(struct drm_device *drm); 32 32 + }; 33 33 + 34 34 + struct intel_display_stolen_interface { 35 35 + int (*insert_node_in_range)(struct intel_stolen_node *node, u64 size, 36 36 + unsigned int align, u64 start, u64 end); 37 37 + int (*insert_node)(struct intel_stolen_node *node, u64 size, unsigned int align); /* Optional */ 38 38 + void (*remove_node)(struct intel_stolen_node *node); 39 39 + bool (*initialized)(struct drm_device *drm); 40 40 + bool (*node_allocated)(const struct intel_stolen_node *node); 41 41 + u64 (*node_offset)(const struct intel_stolen_node *node); 42 42 + u64 (*area_address)(struct drm_device *drm); /* Optional */ 43 43 + u64 (*area_size)(struct drm_device *drm); /* Optional */ 44 44 + u64 (*node_address)(const struct intel_stolen_node *node); 45 45 + u64 (*node_size)(const struct intel_stolen_node *node); 46 46 + struct intel_stolen_node *(*node_alloc)(struct drm_device *drm); 47 47 + void (*node_free)(const struct intel_stolen_node *node); 48 48 + }; 49 49 + 60 50 /** 61 51 * struct intel_display_parent_interface - services parent driver provides to display 62 52 * ··· 92 38 * check the optional pointers. 93 39 */ 94 40 struct intel_display_parent_interface { 41 41 + /** @hdcp: HDCP GSC interface */ 42 42 + const struct intel_display_hdcp_interface *hdcp; 43 43 + 44 44 + /** @irq: IRQ interface */ 45 45 + const struct intel_display_irq_interface *irq; 46 46 + 47 47 + /** @panic: Panic interface */ 48 48 + const struct intel_display_panic_interface *panic; 49 49 + 50 50 + /** @pc8: PC8 interface. Optional. */ 51 51 + const struct intel_display_pc8_interface *pc8; 52 52 + 95 53 /** @rpm: Runtime PM functions */ 96 54 const struct intel_display_rpm_interface *rpm; 55 55 + 56 56 + /** @rps: RPS interface. Optional. */ 57 57 + const struct intel_display_rps_interface *rps; 58 58 + 59 59 + /** @stolen: Stolen memory. */ 60 60 + const struct intel_display_stolen_interface *stolen; 61 61 + 62 62 + /* Generic independent functions */ 63 63 + struct { 64 64 + /** @fence_priority_display: Set display priority. Optional. */ 65 65 + void (*fence_priority_display)(struct dma_fence *fence); 66 66 + 67 67 + /** @has_auxccs: Are AuxCCS formats supported by the parent. Optional. */ 68 68 + bool (*has_auxccs)(struct drm_device *drm); 69 69 + 70 70 + /** @has_fenced_regions: Support legacy fencing? Optional. */ 71 71 + bool (*has_fenced_regions)(struct drm_device *drm); 72 72 + 73 73 + /** @vgpu_active: Is vGPU active? Optional. */ 74 74 + bool (*vgpu_active)(struct drm_device *drm); 75 75 + }; 97 76 }; 98 77 99 78 #endif