Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'irq_urgent_for_v5.17_rc2_p2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Borislav Petkov:
- Drop an unused private data field in the AIC driver
- Various fixes to the realtek-rtl driver
- Make the GICv3 ITS driver compile again in !SMP configurations
- Force reset of the GICv3 ITSs at probe time to avoid issues during kexec
- Yet another kfree/bitmap_free conversion
- Various DT updates (Renesas, SiFive)
* tag 'irq_urgent_for_v5.17_rc2_p2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
dt-bindings: interrupt-controller: sifive,plic: Group interrupt tuples
dt-bindings: interrupt-controller: sifive,plic: Fix number of interrupts
dt-bindings: irqchip: renesas-irqc: Add R-Car V3U support
irqchip/gic-v3-its: Reset each ITS's BASERn register before probe
irqchip/gic-v3-its: Fix build for !SMP
irqchip/loongson-pch-ms: Use bitmap_free() to free bitmap
irqchip/realtek-rtl: Service all pending interrupts
irqchip/realtek-rtl: Fix off-by-one in routing
irqchip/realtek-rtl: Map control data to virq
irqchip/apple-aic: Drop unused ipi_hwirq field
+121
-36
+1
Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml
+1
Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.yaml
+6
-6
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+6
-6
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
···
62
62
63
63
interrupts-extended:
64
64
minItems: 1
65
+
maxItems: 15872
65
66
description:
66
67
Specifies which contexts are connected to the PLIC, with "-1" specifying
67
68
that a context is not present. Each node pointed to should be a
···
91
90
#interrupt-cells = <1>;
92
91
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
93
92
interrupt-controller;
94
-
interrupts-extended = <
95
-
&cpu0_intc 11
96
-
&cpu1_intc 11 &cpu1_intc 9
97
-
&cpu2_intc 11 &cpu2_intc 9
98
-
&cpu3_intc 11 &cpu3_intc 9
99
-
&cpu4_intc 11 &cpu4_intc 9>;
93
+
interrupts-extended = <&cpu0_intc 11>,
94
+
<&cpu1_intc 11>, <&cpu1_intc 9>,
95
+
<&cpu2_intc 11>, <&cpu2_intc 9>,
96
+
<&cpu3_intc 11>, <&cpu3_intc 9>,
97
+
<&cpu4_intc 11>, <&cpu4_intc 9>;
100
98
reg = <0xc000000 0x4000000>;
101
99
riscv,ndev = <10>;
102
100
};
-1
drivers/irqchip/irq-apple-aic.c
-1
drivers/irqchip/irq-apple-aic.c
+101
-22
drivers/irqchip/irq-gic-v3-its.c
+101
-22
drivers/irqchip/irq-gic-v3-its.c
···
4856
4856
.resume = its_restore_enable,
4857
4857
};
4858
4858
4859
+
static void __init __iomem *its_map_one(struct resource *res, int *err)
4860
+
{
4861
+
void __iomem *its_base;
4862
+
u32 val;
4863
+
4864
+
its_base = ioremap(res->start, SZ_64K);
4865
+
if (!its_base) {
4866
+
pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
4867
+
*err = -ENOMEM;
4868
+
return NULL;
4869
+
}
4870
+
4871
+
val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
4872
+
if (val != 0x30 && val != 0x40) {
4873
+
pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
4874
+
*err = -ENODEV;
4875
+
goto out_unmap;
4876
+
}
4877
+
4878
+
*err = its_force_quiescent(its_base);
4879
+
if (*err) {
4880
+
pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
4881
+
goto out_unmap;
4882
+
}
4883
+
4884
+
return its_base;
4885
+
4886
+
out_unmap:
4887
+
iounmap(its_base);
4888
+
return NULL;
4889
+
}
4890
+
4859
4891
static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
4860
4892
{
4861
4893
struct irq_domain *inner_domain;
···
4995
4963
{
4996
4964
struct its_node *its;
4997
4965
void __iomem *its_base;
4998
-
u32 val, ctlr;
4999
4966
u64 baser, tmp, typer;
5000
4967
struct page *page;
4968
+
u32 ctlr;
5001
4969
int err;
5002
4970
5003
-
its_base = ioremap(res->start, SZ_64K);
5004
-
if (!its_base) {
5005
-
pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
5006
-
return -ENOMEM;
5007
-
}
5008
-
5009
-
val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
5010
-
if (val != 0x30 && val != 0x40) {
5011
-
pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
5012
-
err = -ENODEV;
5013
-
goto out_unmap;
5014
-
}
5015
-
5016
-
err = its_force_quiescent(its_base);
5017
-
if (err) {
5018
-
pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
5019
-
goto out_unmap;
5020
-
}
4971
+
its_base = its_map_one(res, &err);
4972
+
if (!its_base)
4973
+
return err;
5021
4974
5022
4975
pr_info("ITS %pR\n", res);
5023
4976
···
5258
5241
5259
5242
out:
5260
5243
/* Last CPU being brought up gets to issue the cleanup */
5261
-
if (cpumask_equal(&cpus_booted_once_mask, cpu_possible_mask))
5244
+
if (!IS_ENABLED(CONFIG_SMP) ||
5245
+
cpumask_equal(&cpus_booted_once_mask, cpu_possible_mask))
5262
5246
schedule_work(&rdist_memreserve_cpuhp_cleanup_work);
5263
5247
5264
5248
gic_data_rdist()->flags |= RD_LOCAL_MEMRESERVE_DONE;
5265
5249
return ret;
5250
+
}
5251
+
5252
+
/* Mark all the BASER registers as invalid before they get reprogrammed */
5253
+
static int __init its_reset_one(struct resource *res)
5254
+
{
5255
+
void __iomem *its_base;
5256
+
int err, i;
5257
+
5258
+
its_base = its_map_one(res, &err);
5259
+
if (!its_base)
5260
+
return err;
5261
+
5262
+
for (i = 0; i < GITS_BASER_NR_REGS; i++)
5263
+
gits_write_baser(0, its_base + GITS_BASER + (i << 3));
5264
+
5265
+
iounmap(its_base);
5266
+
return 0;
5266
5267
}
5267
5268
5268
5269
static const struct of_device_id its_device_id[] = {
···
5292
5257
{
5293
5258
struct device_node *np;
5294
5259
struct resource res;
5260
+
5261
+
/*
5262
+
* Make sure *all* the ITS are reset before we probe any, as
5263
+
* they may be sharing memory. If any of the ITS fails to
5264
+
* reset, don't even try to go any further, as this could
5265
+
* result in something even worse.
5266
+
*/
5267
+
for (np = of_find_matching_node(node, its_device_id); np;
5268
+
np = of_find_matching_node(np, its_device_id)) {
5269
+
int err;
5270
+
5271
+
if (!of_device_is_available(np) ||
5272
+
!of_property_read_bool(np, "msi-controller") ||
5273
+
of_address_to_resource(np, 0, &res))
5274
+
continue;
5275
+
5276
+
err = its_reset_one(&res);
5277
+
if (err)
5278
+
return err;
5279
+
}
5295
5280
5296
5281
for (np = of_find_matching_node(node, its_device_id); np;
5297
5282
np = of_find_matching_node(np, its_device_id)) {
···
5475
5420
return err;
5476
5421
}
5477
5422
5423
+
static int __init its_acpi_reset(union acpi_subtable_headers *header,
5424
+
const unsigned long end)
5425
+
{
5426
+
struct acpi_madt_generic_translator *its_entry;
5427
+
struct resource res;
5428
+
5429
+
its_entry = (struct acpi_madt_generic_translator *)header;
5430
+
res = (struct resource) {
5431
+
.start = its_entry->base_address,
5432
+
.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1,
5433
+
.flags = IORESOURCE_MEM,
5434
+
};
5435
+
5436
+
return its_reset_one(&res);
5437
+
}
5438
+
5478
5439
static void __init its_acpi_probe(void)
5479
5440
{
5480
5441
acpi_table_parse_srat_its();
5481
-
acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5482
-
gic_acpi_parse_madt_its, 0);
5442
+
/*
5443
+
* Make sure *all* the ITS are reset before we probe any, as
5444
+
* they may be sharing memory. If any of the ITS fails to
5445
+
* reset, don't even try to go any further, as this could
5446
+
* result in something even worse.
5447
+
*/
5448
+
if (acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5449
+
its_acpi_reset, 0) > 0)
5450
+
acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5451
+
gic_acpi_parse_madt_its, 0);
5483
5452
acpi_its_srat_maps_free();
5484
5453
}
5485
5454
#else
+1
-1
drivers/irqchip/irq-loongson-pch-msi.c
+1
-1
drivers/irqchip/irq-loongson-pch-msi.c
+12
-6
drivers/irqchip/irq-realtek-rtl.c
+12
-6
drivers/irqchip/irq-realtek-rtl.c
···
62
62
63
63
static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
64
64
{
65
-
irq_set_chip_and_handler(hw, &realtek_ictl_irq, handle_level_irq);
65
+
irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq);
66
66
67
67
return 0;
68
68
}
···
76
76
{
77
77
struct irq_chip *chip = irq_desc_get_chip(desc);
78
78
struct irq_domain *domain;
79
-
unsigned int pending;
79
+
unsigned long pending;
80
+
unsigned int soc_int;
80
81
81
82
chained_irq_enter(chip, desc);
82
83
pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));
84
+
83
85
if (unlikely(!pending)) {
84
86
spurious_interrupt();
85
87
goto out;
86
88
}
89
+
87
90
domain = irq_desc_get_handler_data(desc);
88
-
generic_handle_domain_irq(domain, __ffs(pending));
91
+
for_each_set_bit(soc_int, &pending, 32)
92
+
generic_handle_domain_irq(domain, soc_int);
89
93
90
94
out:
91
95
chained_irq_exit(chip, desc);
···
99
95
* SoC interrupts are cascaded to MIPS CPU interrupts according to the
100
96
* interrupt-map in the device tree. Each SoC interrupt gets 4 bits for
101
97
* the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts
102
-
* thus go into 4 IRRs.
98
+
* thus go into 4 IRRs. A routing value of '0' means the interrupt is left
99
+
* disconnected. Routing values {1..15} connect to output lines {0..14}.
103
100
*/
104
101
static int __init map_interrupts(struct device_node *node, struct irq_domain *domain)
105
102
{
···
139
134
of_node_put(cpu_ictl);
140
135
141
136
cpu_int = be32_to_cpup(imap + 2);
142
-
if (cpu_int > 7)
137
+
if (cpu_int > 7 || cpu_int < 2)
143
138
return -EINVAL;
144
139
145
140
if (!(mips_irqs_set & BIT(cpu_int))) {
···
148
143
mips_irqs_set |= BIT(cpu_int);
149
144
}
150
145
151
-
regs[(soc_int * 4) / 32] |= cpu_int << (soc_int * 4) % 32;
146
+
/* Use routing values (1..6) for CPU interrupts (2..7) */
147
+
regs[(soc_int * 4) / 32] |= (cpu_int - 1) << (soc_int * 4) % 32;
152
148
imap += 3;
153
149
}
154
150