Merge branch '10g-qxgmii-for-aqr412c-felix-dsa-and-lynx-pcs-driver'

+4

drivers/net/dsa/ocelot/felix.c

··· 1153 1153 1154 1154 __set_bit(ocelot->ports[port]->phy_mode, 1155 1155 config->supported_interfaces); 1156 + if (ocelot->ports[port]->phy_mode == PHY_INTERFACE_MODE_USXGMII) 1157 + __set_bit(PHY_INTERFACE_MODE_10G_QXGMII, 1158 + config->supported_interfaces); 1156 1159 } 1157 1160 1158 1161 static void felix_phylink_mac_config(struct phylink_config *config, ··· 1362 1359 [PHY_INTERFACE_MODE_SGMII] = OCELOT_PORT_MODE_SGMII, 1363 1360 [PHY_INTERFACE_MODE_QSGMII] = OCELOT_PORT_MODE_QSGMII, 1364 1361 [PHY_INTERFACE_MODE_USXGMII] = OCELOT_PORT_MODE_USXGMII, 1362 + [PHY_INTERFACE_MODE_10G_QXGMII] = OCELOT_PORT_MODE_10G_QXGMII, 1365 1363 [PHY_INTERFACE_MODE_1000BASEX] = OCELOT_PORT_MODE_1000BASEX, 1366 1364 [PHY_INTERFACE_MODE_2500BASEX] = OCELOT_PORT_MODE_2500BASEX, 1367 1365 };

+2 -1

drivers/net/dsa/ocelot/felix.h

··· 12 12 #define OCELOT_PORT_MODE_SGMII BIT(1) 13 13 #define OCELOT_PORT_MODE_QSGMII BIT(2) 14 14 #define OCELOT_PORT_MODE_2500BASEX BIT(3) 15 - #define OCELOT_PORT_MODE_USXGMII BIT(4) 15 + #define OCELOT_PORT_MODE_USXGMII BIT(4) /* compatibility */ 16 16 #define OCELOT_PORT_MODE_1000BASEX BIT(5) 17 + #define OCELOT_PORT_MODE_10G_QXGMII BIT(6) 17 18 18 19 struct device_node; 19 20

+2 -1

drivers/net/dsa/ocelot/felix_vsc9959.c

··· 34 34 OCELOT_PORT_MODE_QSGMII | \ 35 35 OCELOT_PORT_MODE_1000BASEX | \ 36 36 OCELOT_PORT_MODE_2500BASEX | \ 37 - OCELOT_PORT_MODE_USXGMII) 37 + OCELOT_PORT_MODE_USXGMII | \ 38 + OCELOT_PORT_MODE_10G_QXGMII) 38 39 39 40 static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = { 40 41 VSC9959_PORT_MODE_SERDES,

+9 -2

drivers/net/pcs/pcs-lynx.c

··· 49 49 return LINK_INBAND_DISABLE; 50 50 51 51 case PHY_INTERFACE_MODE_USXGMII: 52 + case PHY_INTERFACE_MODE_10G_QXGMII: 52 53 return LINK_INBAND_ENABLE; 53 54 54 55 default: ··· 116 115 lynx_pcs_get_state_2500basex(lynx->mdio, state); 117 116 break; 118 117 case PHY_INTERFACE_MODE_USXGMII: 118 + case PHY_INTERFACE_MODE_10G_QXGMII: 119 119 lynx_pcs_get_state_usxgmii(lynx->mdio, state); 120 120 break; 121 121 case PHY_INTERFACE_MODE_10GBASER: ··· 172 170 } 173 171 174 172 static int lynx_pcs_config_usxgmii(struct mdio_device *pcs, 173 + phy_interface_t interface, 175 174 const unsigned long *advertising, 176 175 unsigned int neg_mode) 177 176 { ··· 180 177 int addr = pcs->addr; 181 178 182 179 if (neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) { 183 - dev_err(&pcs->dev, "USXGMII only supports in-band AN for now\n"); 180 + dev_err(&pcs->dev, "%s only supports in-band AN for now\n", 181 + phy_modes(interface)); 184 182 return -EOPNOTSUPP; 185 183 } 186 184 ··· 212 208 } 213 209 break; 214 210 case PHY_INTERFACE_MODE_USXGMII: 215 - return lynx_pcs_config_usxgmii(lynx->mdio, advertising, 211 + case PHY_INTERFACE_MODE_10G_QXGMII: 212 + return lynx_pcs_config_usxgmii(lynx->mdio, ifmode, advertising, 216 213 neg_mode); 217 214 case PHY_INTERFACE_MODE_10GBASER: 218 215 /* Nothing to do here for 10GBASER */ ··· 322 317 lynx_pcs_link_up_2500basex(lynx->mdio, neg_mode, speed, duplex); 323 318 break; 324 319 case PHY_INTERFACE_MODE_USXGMII: 320 + case PHY_INTERFACE_MODE_10G_QXGMII: 325 321 /* At the moment, only in-band AN is supported for USXGMII 326 322 * so nothing to do in link_up 327 323 */ ··· 347 341 PHY_INTERFACE_MODE_2500BASEX, 348 342 PHY_INTERFACE_MODE_10GBASER, 349 343 PHY_INTERFACE_MODE_USXGMII, 344 + PHY_INTERFACE_MODE_10G_QXGMII, 350 345 }; 351 346 352 347 static struct phylink_pcs *lynx_pcs_create(struct mdio_device *mdio)

+25

drivers/net/phy/aquantia/aquantia.h

··· 55 55 #define VEND1_GLOBAL_CFG_SERDES_MODE_SGMII 3 56 56 #define VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII 4 57 57 #define VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G 6 58 + #define VEND1_GLOBAL_CFG_AUTONEG_ENA BIT(3) 58 59 #define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7) 59 60 #define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0 60 61 #define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1 ··· 153 152 154 153 #define AQR_MAX_LEDS 3 155 154 155 + /* Custom driver definitions for constructing a single variable out of 156 + * aggregate firmware build information. These do not represent hardware 157 + * fields. 158 + */ 159 + #define AQR_FW_FINGERPRINT_MAJOR GENMASK_ULL(63, 56) 160 + #define AQR_FW_FINGERPRINT_MINOR GENMASK_ULL(55, 48) 161 + #define AQR_FW_FINGERPRINT_BUILD_ID GENMASK_ULL(47, 40) 162 + #define AQR_FW_FINGERPRINT_PROV_ID GENMASK_ULL(39, 32) 163 + #define AQR_FW_FINGERPRINT_MISC_ID GENMASK_ULL(31, 16) 164 + #define AQR_FW_FINGERPRINT_MISC_VER GENMASK_ULL(15, 0) 165 + #define AQR_FW_FINGERPRINT(major, minor, build_id, prov_id, misc_id, misc_ver) \ 166 + (FIELD_PREP(AQR_FW_FINGERPRINT_MAJOR, major) | \ 167 + FIELD_PREP(AQR_FW_FINGERPRINT_MINOR, minor) | \ 168 + FIELD_PREP(AQR_FW_FINGERPRINT_BUILD_ID, build_id) | \ 169 + FIELD_PREP(AQR_FW_FINGERPRINT_PROV_ID, prov_id) | \ 170 + FIELD_PREP(AQR_FW_FINGERPRINT_MISC_ID, misc_id) | \ 171 + FIELD_PREP(AQR_FW_FINGERPRINT_MISC_VER, misc_ver)) 172 + 173 + /* 10G-QXGMII firmware for NXP SPF-30841 riser board (AQR412C) */ 174 + #define AQR_G3_V4_3_C_AQR_NXP_SPF_30841_MUSX_ID40019_VER1198 \ 175 + AQR_FW_FINGERPRINT(4, 3, 0xc, 1, 40019, 1198) 176 + 156 177 struct aqr107_hw_stat { 157 178 const char *name; 158 179 int reg; ··· 225 202 226 203 struct aqr107_priv { 227 204 u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; 205 + u64 fingerprint; 228 206 unsigned long leds_active_low; 229 207 unsigned long leds_active_high; 230 208 bool wait_on_global_cfg; ··· 239 215 #endif 240 216 241 217 int aqr_firmware_load(struct phy_device *phydev); 218 + int aqr_firmware_read_fingerprint(struct phy_device *phydev); 242 219 243 220 int aqr_phy_led_blink_set(struct phy_device *phydev, u8 index, 244 221 unsigned long *delay_on,

+158 -17

drivers/net/phy/aquantia/aquantia_main.c

··· 35 35 #define PHY_ID_AQR115C 0x31c31c33 36 36 #define PHY_ID_AQR813 0x31c31cb2 37 37 38 + #define MDIO_PHYXS_VEND_PROV2 0xc441 39 + #define MDIO_PHYXS_VEND_PROV2_USX_AN BIT(3) 40 + 38 41 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 39 42 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 40 43 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 ··· 87 84 88 85 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 89 86 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 87 + 88 + #define PMAPMD_FW_MISC_ID 0xc41d 89 + #define PMAPMD_FW_MISC_VER 0xc41e 90 90 91 91 #define PMAPMD_RSVD_VEND_PROV 0xe400 92 92 #define PMAPMD_RSVD_VEND_PROV_MDI_CONF GENMASK(1, 0) ··· 512 506 return 0; 513 507 } 514 508 509 + /* Quad port PHYs like AQR412(C) have 4 system interfaces, but they can also be 510 + * used with a single system interface over which all 4 ports are multiplexed 511 + * (10G-QXGMII). To the MDIO registers, this mode is indistinguishable from 512 + * USXGMII (which implies a single 10G port). 513 + * 514 + * To not rely solely on the device tree, we allow the regular system interface 515 + * detection to work as usual, but we replace USXGMII with 10G-QXGMII based on 516 + * the specific fingerprint of firmware images that are known to be for MUSX. 517 + */ 518 + static phy_interface_t aqr_translate_interface(struct phy_device *phydev, 519 + phy_interface_t interface) 520 + { 521 + struct aqr107_priv *priv = phydev->priv; 522 + 523 + if (phy_id_compare(phydev->drv->phy_id, PHY_ID_AQR412C, phydev->drv->phy_id_mask) && 524 + priv->fingerprint == AQR_G3_V4_3_C_AQR_NXP_SPF_30841_MUSX_ID40019_VER1198 && 525 + interface == PHY_INTERFACE_MODE_USXGMII) 526 + return PHY_INTERFACE_MODE_10G_QXGMII; 527 + 528 + return interface; 529 + } 530 + 515 531 static int aqr_gen1_read_status(struct phy_device *phydev) 516 532 { 533 + phy_interface_t interface; 517 534 int ret; 518 535 int val; 519 536 ··· 562 533 563 534 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 564 535 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 565 - phydev->interface = PHY_INTERFACE_MODE_10GKR; 536 + interface = PHY_INTERFACE_MODE_10GKR; 566 537 break; 567 538 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 568 - phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 539 + interface = PHY_INTERFACE_MODE_1000BASEKX; 569 540 break; 570 541 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 571 - phydev->interface = PHY_INTERFACE_MODE_10GBASER; 542 + interface = PHY_INTERFACE_MODE_10GBASER; 572 543 break; 573 544 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 574 - phydev->interface = PHY_INTERFACE_MODE_USXGMII; 545 + interface = PHY_INTERFACE_MODE_USXGMII; 575 546 break; 576 547 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 577 - phydev->interface = PHY_INTERFACE_MODE_XAUI; 548 + interface = PHY_INTERFACE_MODE_XAUI; 578 549 break; 579 550 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 580 - phydev->interface = PHY_INTERFACE_MODE_SGMII; 551 + interface = PHY_INTERFACE_MODE_SGMII; 581 552 break; 582 553 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 583 - phydev->interface = PHY_INTERFACE_MODE_RXAUI; 554 + interface = PHY_INTERFACE_MODE_RXAUI; 584 555 break; 585 556 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 586 - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 557 + interface = PHY_INTERFACE_MODE_2500BASEX; 587 558 break; 588 559 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF: 589 560 default: 590 561 phydev->link = false; 591 - phydev->interface = PHY_INTERFACE_MODE_NA; 562 + interface = PHY_INTERFACE_MODE_NA; 592 563 break; 593 564 } 565 + 566 + phydev->interface = aqr_translate_interface(phydev, interface); 594 567 595 568 /* Read rate from vendor register */ 596 569 return aqr_gen1_read_rate(phydev); ··· 705 674 return ret; 706 675 } 707 676 708 - static void aqr107_chip_info(struct phy_device *phydev) 677 + static int aqr_build_fingerprint(struct phy_device *phydev) 709 678 { 710 679 u8 fw_major, fw_minor, build_id, prov_id; 680 + struct aqr107_priv *priv = phydev->priv; 681 + u16 misc_id, misc_ver; 711 682 int val; 712 683 713 684 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 714 685 if (val < 0) 715 - return; 686 + return val; 716 687 717 688 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 718 689 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 719 690 720 691 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 721 692 if (val < 0) 722 - return; 693 + return val; 723 694 724 695 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 725 696 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 726 697 727 - phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 728 - fw_major, fw_minor, build_id, prov_id); 698 + val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_FW_MISC_ID); 699 + if (val < 0) 700 + return val; 701 + 702 + misc_id = val; 703 + 704 + val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_FW_MISC_VER); 705 + if (val < 0) 706 + return val; 707 + 708 + misc_ver = val; 709 + 710 + priv->fingerprint = AQR_FW_FINGERPRINT(fw_major, fw_minor, build_id, 711 + prov_id, misc_id, misc_ver); 712 + 713 + phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u, Misc ID %u, Version %u\n", 714 + fw_major, fw_minor, build_id, prov_id, misc_id, misc_ver); 715 + 716 + return 0; 729 717 } 730 718 731 719 static int aqr107_config_mdi(struct phy_device *phydev) ··· 782 732 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 783 733 phydev->interface != PHY_INTERFACE_MODE_XGMII && 784 734 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 735 + phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII && 785 736 phydev->interface != PHY_INTERFACE_MODE_10GKR && 786 737 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 787 738 phydev->interface != PHY_INTERFACE_MODE_XAUI && ··· 793 742 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 794 743 795 744 ret = aqr_wait_reset_complete(phydev); 796 - if (!ret) 797 - aqr107_chip_info(phydev); 745 + if (!ret) { 746 + /* The PHY might work without a firmware image, so only build a 747 + * fingerprint if the firmware was initialized. 748 + */ 749 + ret = aqr_build_fingerprint(phydev); 750 + if (ret) 751 + return ret; 752 + } 798 753 799 754 ret = aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 800 755 if (ret) ··· 877 820 break; 878 821 } 879 822 880 - syscfg->interface = interface; 823 + syscfg->interface = aqr_translate_interface(phydev, interface); 881 824 882 825 switch (rate_adapt) { 883 826 case VEND1_GLOBAL_CFG_RATE_ADAPT_NONE: ··· 894 837 rate_adapt); 895 838 break; 896 839 } 840 + 841 + phydev_dbg(phydev, 842 + "Media speed %d uses host interface %s with %s\n", 843 + syscfg->speed, phy_modes(syscfg->interface), 844 + syscfg->rate_adapt == AQR_RATE_ADAPT_NONE ? "no rate adaptation" : 845 + syscfg->rate_adapt == AQR_RATE_ADAPT_PAUSE ? "rate adaptation through flow control" : 846 + syscfg->rate_adapt == AQR_RATE_ADAPT_USX ? "rate adaptation through symbol replication" : 847 + "unrecognized rate adaptation type"); 897 848 } 898 849 899 850 return 0; ··· 1113 1048 return aqr_gen1_wait_processor_intensive_op(phydev); 1114 1049 } 1115 1050 1051 + static unsigned int aqr_gen2_inband_caps(struct phy_device *phydev, 1052 + phy_interface_t interface) 1053 + { 1054 + if (interface == PHY_INTERFACE_MODE_SGMII || 1055 + interface == PHY_INTERFACE_MODE_USXGMII || 1056 + interface == PHY_INTERFACE_MODE_10G_QXGMII) 1057 + return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE; 1058 + 1059 + return 0; 1060 + } 1061 + 1062 + static int aqr_gen2_config_inband(struct phy_device *phydev, unsigned int modes) 1063 + { 1064 + struct aqr107_priv *priv = phydev->priv; 1065 + 1066 + if (phydev->interface == PHY_INTERFACE_MODE_USXGMII || 1067 + phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) { 1068 + u16 set = 0; 1069 + 1070 + if (modes == LINK_INBAND_ENABLE) 1071 + set = MDIO_PHYXS_VEND_PROV2_USX_AN; 1072 + 1073 + return phy_modify_mmd(phydev, MDIO_MMD_PHYXS, 1074 + MDIO_PHYXS_VEND_PROV2, 1075 + MDIO_PHYXS_VEND_PROV2_USX_AN, set); 1076 + } 1077 + 1078 + for (int i = 0; i < AQR_NUM_GLOBAL_CFG; i++) { 1079 + struct aqr_global_syscfg *syscfg = &priv->global_cfg[i]; 1080 + u16 set = 0; 1081 + int err; 1082 + 1083 + if (syscfg->interface != phydev->interface) 1084 + continue; 1085 + 1086 + if (modes == LINK_INBAND_ENABLE) 1087 + set = VEND1_GLOBAL_CFG_AUTONEG_ENA; 1088 + 1089 + err = phy_modify_mmd(phydev, MDIO_MMD_VEND1, 1090 + aqr_global_cfg_regs[i].reg, 1091 + VEND1_GLOBAL_CFG_AUTONEG_ENA, set); 1092 + if (err) 1093 + return err; 1094 + } 1095 + 1096 + return 0; 1097 + } 1098 + 1116 1099 static int aqr107_probe(struct phy_device *phydev) 1117 1100 { 1118 1101 int ret; ··· 1239 1126 .led_hw_control_set = aqr_phy_led_hw_control_set, 1240 1127 .led_hw_control_get = aqr_phy_led_hw_control_get, 1241 1128 .led_polarity_set = aqr_phy_led_polarity_set, 1129 + .inband_caps = aqr_gen2_inband_caps, 1130 + .config_inband = aqr_gen2_config_inband, 1242 1131 }, 1243 1132 { 1244 1133 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), ··· 1266 1151 .led_hw_control_set = aqr_phy_led_hw_control_set, 1267 1152 .led_hw_control_get = aqr_phy_led_hw_control_get, 1268 1153 .led_polarity_set = aqr_phy_led_polarity_set, 1154 + .inband_caps = aqr_gen2_inband_caps, 1155 + .config_inband = aqr_gen2_config_inband, 1269 1156 }, 1270 1157 { 1271 1158 PHY_ID_MATCH_MODEL(PHY_ID_AQR111), ··· 1293 1176 .led_hw_control_set = aqr_phy_led_hw_control_set, 1294 1177 .led_hw_control_get = aqr_phy_led_hw_control_get, 1295 1178 .led_polarity_set = aqr_phy_led_polarity_set, 1179 + .inband_caps = aqr_gen2_inband_caps, 1180 + .config_inband = aqr_gen2_config_inband, 1296 1181 }, 1297 1182 { 1298 1183 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0), ··· 1320 1201 .led_hw_control_set = aqr_phy_led_hw_control_set, 1321 1202 .led_hw_control_get = aqr_phy_led_hw_control_get, 1322 1203 .led_polarity_set = aqr_phy_led_polarity_set, 1204 + .inband_caps = aqr_gen2_inband_caps, 1205 + .config_inband = aqr_gen2_config_inband, 1323 1206 }, 1324 1207 { 1325 1208 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), ··· 1330 1209 .config_intr = aqr_config_intr, 1331 1210 .handle_interrupt = aqr_handle_interrupt, 1332 1211 .read_status = aqr_read_status, 1212 + .inband_caps = aqr_gen2_inband_caps, 1213 + .config_inband = aqr_gen2_config_inband, 1333 1214 }, 1334 1215 { 1335 1216 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), ··· 1356 1233 .led_hw_control_set = aqr_phy_led_hw_control_set, 1357 1234 .led_hw_control_get = aqr_phy_led_hw_control_get, 1358 1235 .led_polarity_set = aqr_phy_led_polarity_set, 1236 + .inband_caps = aqr_gen2_inband_caps, 1237 + .config_inband = aqr_gen2_config_inband, 1359 1238 }, 1360 1239 { 1361 1240 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), ··· 1377 1252 .get_strings = aqr107_get_strings, 1378 1253 .get_stats = aqr107_get_stats, 1379 1254 .link_change_notify = aqr107_link_change_notify, 1255 + .inband_caps = aqr_gen2_inband_caps, 1256 + .config_inband = aqr_gen2_config_inband, 1380 1257 }, 1381 1258 { 1382 1259 PHY_ID_MATCH_MODEL(PHY_ID_AQR412C), ··· 1398 1271 .get_strings = aqr107_get_strings, 1399 1272 .get_stats = aqr107_get_stats, 1400 1273 .link_change_notify = aqr107_link_change_notify, 1274 + .inband_caps = aqr_gen2_inband_caps, 1275 + .config_inband = aqr_gen2_config_inband, 1401 1276 }, 1402 1277 { 1403 1278 PHY_ID_MATCH_MODEL(PHY_ID_AQR113), ··· 1424 1295 .led_hw_control_set = aqr_phy_led_hw_control_set, 1425 1296 .led_hw_control_get = aqr_phy_led_hw_control_get, 1426 1297 .led_polarity_set = aqr_phy_led_polarity_set, 1298 + .inband_caps = aqr_gen2_inband_caps, 1299 + .config_inband = aqr_gen2_config_inband, 1427 1300 }, 1428 1301 { 1429 1302 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), ··· 1450 1319 .led_hw_control_set = aqr_phy_led_hw_control_set, 1451 1320 .led_hw_control_get = aqr_phy_led_hw_control_get, 1452 1321 .led_polarity_set = aqr_phy_led_polarity_set, 1322 + .inband_caps = aqr_gen2_inband_caps, 1323 + .config_inband = aqr_gen2_config_inband, 1453 1324 }, 1454 1325 { 1455 1326 PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), ··· 1477 1344 .led_hw_control_set = aqr_phy_led_hw_control_set, 1478 1345 .led_hw_control_get = aqr_phy_led_hw_control_get, 1479 1346 .led_polarity_set = aqr_phy_led_polarity_set, 1347 + .inband_caps = aqr_gen2_inband_caps, 1348 + .config_inband = aqr_gen2_config_inband, 1480 1349 }, 1481 1350 { 1482 1351 PHY_ID_MATCH_MODEL(PHY_ID_AQR115), ··· 1504 1369 .led_hw_control_set = aqr_phy_led_hw_control_set, 1505 1370 .led_hw_control_get = aqr_phy_led_hw_control_get, 1506 1371 .led_polarity_set = aqr_phy_led_polarity_set, 1372 + .inband_caps = aqr_gen2_inband_caps, 1373 + .config_inband = aqr_gen2_config_inband, 1507 1374 }, 1508 1375 { 1509 1376 PHY_ID_MATCH_MODEL(PHY_ID_AQR115C), ··· 1531 1394 .led_hw_control_set = aqr_phy_led_hw_control_set, 1532 1395 .led_hw_control_get = aqr_phy_led_hw_control_get, 1533 1396 .led_polarity_set = aqr_phy_led_polarity_set, 1397 + .inband_caps = aqr_gen2_inband_caps, 1398 + .config_inband = aqr_gen2_config_inband, 1534 1399 }, 1535 1400 { 1536 1401 PHY_ID_MATCH_MODEL(PHY_ID_AQR813), ··· 1557 1418 .led_hw_control_set = aqr_phy_led_hw_control_set, 1558 1419 .led_hw_control_get = aqr_phy_led_hw_control_get, 1559 1420 .led_polarity_set = aqr_phy_led_polarity_set, 1421 + .inband_caps = aqr_gen2_inband_caps, 1422 + .config_inband = aqr_gen2_config_inband, 1560 1423 }, 1561 1424 }; 1562 1425

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