tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux into master

Pull i2c fixes from Wolfram Sang:
"Again some driver bugfixes and some documentation fixes"

* 'i2c/for-current' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
i2c: i2c-qcom-geni: Fix DMA transfer race
i2c: rcar: always clear ICSAR to avoid side effects
MAINTAINERS: i2c: at91: handover maintenance to Codrin Ciubotariu
i2c: drop duplicated word in the header file
i2c: cadence: Clear HOLD bit at correct time in Rx path
Revert "i2c: cadence: Fix the hold bit setting"

Linus Torvalds c615035b b85bcb78

+21 -20
+1 -1
MAINTAINERS
··· 11241 11241 F: drivers/crypto/atmel-ecc.* 11242 11242 11243 11243 MICROCHIP I2C DRIVER 11244 - M: Ludovic Desroches <ludovic.desroches@microchip.com> 11244 + M: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> 11245 11245 L: linux-i2c@vger.kernel.org 11246 11246 S: Supported 11247 11247 F: drivers/i2c/busses/i2c-at91-*.c
+12 -16
drivers/i2c/busses/i2c-cadence.c
··· 421 421 /* Read data if receive data valid is set */ 422 422 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & 423 423 CDNS_I2C_SR_RXDV) { 424 - /* 425 - * Clear hold bit that was set for FIFO control if 426 - * RX data left is less than FIFO depth, unless 427 - * repeated start is selected. 428 - */ 429 - if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) && 430 - !id->bus_hold_flag) 431 - cdns_i2c_clear_bus_hold(id); 432 - 433 424 if (id->recv_count > 0) { 434 425 *(id->p_recv_buf)++ = 435 426 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 436 427 id->recv_count--; 437 428 id->curr_recv_count--; 429 + 430 + /* 431 + * Clear hold bit that was set for FIFO control 432 + * if RX data left is less than or equal to 433 + * FIFO DEPTH unless repeated start is selected 434 + */ 435 + if (id->recv_count <= CDNS_I2C_FIFO_DEPTH && 436 + !id->bus_hold_flag) 437 + cdns_i2c_clear_bus_hold(id); 438 + 438 439 } else { 439 440 dev_err(id->adap.dev.parent, 440 441 "xfer_size reg rollover. xfer aborted!\n"); ··· 595 594 * Check for the message size against FIFO depth and set the 596 595 * 'hold bus' bit if it is greater than FIFO depth. 597 596 */ 598 - if ((id->recv_count > CDNS_I2C_FIFO_DEPTH) || id->bus_hold_flag) 597 + if (id->recv_count > CDNS_I2C_FIFO_DEPTH) 599 598 ctrl_reg |= CDNS_I2C_CR_HOLD; 600 - else 601 - ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD; 602 599 603 600 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 604 601 ··· 653 654 * Check for the message size against FIFO depth and set the 654 655 * 'hold bus' bit if it is greater than FIFO depth. 655 656 */ 656 - if ((id->send_count > CDNS_I2C_FIFO_DEPTH) || id->bus_hold_flag) 657 + if (id->send_count > CDNS_I2C_FIFO_DEPTH) 657 658 ctrl_reg |= CDNS_I2C_CR_HOLD; 658 - else 659 - ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD; 660 - 661 659 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 662 660 663 661 /* Clear the interrupts in interrupt status register. */
+4 -2
drivers/i2c/busses/i2c-qcom-geni.c
··· 367 367 geni_se_select_mode(se, GENI_SE_FIFO); 368 368 369 369 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); 370 - geni_se_setup_m_cmd(se, I2C_READ, m_param); 371 370 372 371 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) { 373 372 geni_se_select_mode(se, GENI_SE_FIFO); 374 373 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 375 374 dma_buf = NULL; 376 375 } 376 + 377 + geni_se_setup_m_cmd(se, I2C_READ, m_param); 377 378 378 379 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 379 380 if (!time_left) ··· 409 408 geni_se_select_mode(se, GENI_SE_FIFO); 410 409 411 410 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); 412 - geni_se_setup_m_cmd(se, I2C_WRITE, m_param); 413 411 414 412 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) { 415 413 geni_se_select_mode(se, GENI_SE_FIFO); 416 414 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 417 415 dma_buf = NULL; 418 416 } 417 + 418 + geni_se_setup_m_cmd(se, I2C_WRITE, m_param); 419 419 420 420 if (!dma_buf) /* Get FIFO IRQ */ 421 421 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
+3
drivers/i2c/busses/i2c-rcar.c
··· 868 868 /* disable irqs and ensure none is running before clearing ptr */ 869 869 rcar_i2c_write(priv, ICSIER, 0); 870 870 rcar_i2c_write(priv, ICSCR, 0); 871 + rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 871 872 872 873 synchronize_irq(priv->irq); 873 874 priv->slave = NULL; ··· 969 968 ret = rcar_i2c_clock_calculate(priv); 970 969 if (ret < 0) 971 970 goto out_pm_put; 971 + 972 + rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */ 972 973 973 974 if (priv->devtype == I2C_RCAR_GEN3) { 974 975 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+1 -1
include/linux/i2c.h
··· 56 56 * on a bus (or read from them). Apart from two basic transfer functions to 57 57 * transmit one message at a time, a more complex version can be used to 58 58 * transmit an arbitrary number of messages without interruption. 59 - * @count must be be less than 64k since msg.len is u16. 59 + * @count must be less than 64k since msg.len is u16. 60 60 */ 61 61 int i2c_transfer_buffer_flags(const struct i2c_client *client, 62 62 char *buf, int count, u16 flags);