Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'xtensa-next-20130508' of git://github.com/czankel/xtensa-linux
Pull xtensa updates from Chris Zankel:
"Support for the latest MMU architecture that allows for a larger
accessible memory region, and various bug-fixes"
* tag 'xtensa-next-20130508' of git://github.com/czankel/xtensa-linux:
xtensa: Switch to asm-generic/linkage.h
xtensa: fix redboot load address
xtensa: ISS: fix timer_lock usage in rs_open
xtensa: disable IRQs while IRQ handler is running
xtensa: enable lockdep support
xtensa: fix arch_irqs_disabled_flags implementation
xtensa: add irq flags trace support
xtensa: provide custom CALLER_ADDR* implementations
xtensa: add stacktrace support
xtensa: clean up stpill_registers
xtensa: don't use a7 in simcalls
xtensa: don't attempt to use unconfigured timers
xtensa: provide default platform_pcibios_init implementation
xtensa: remove KCORE_ELF again
xtensa: document MMUv3 setup sequence
xtensa: add MMU v3 support
xtensa: fix ibreakenable register update
xtensa: fix oprofile building as module
+820
-255
+46
Documentation/xtensa/mmu.txt
+46
Documentation/xtensa/mmu.txt
···
1
+
MMUv3 initialization sequence.
2
+
3
+
The code in the initialize_mmu macro sets up MMUv3 memory mapping
4
+
identically to MMUv2 fixed memory mapping. Depending on
5
+
CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX symbol this code is
6
+
located in one of the following address ranges:
7
+
8
+
0xF0000000..0xFFFFFFFF (will keep same address in MMU v2 layout;
9
+
typically ROM)
10
+
0x00000000..0x07FFFFFF (system RAM; this code is actually linked
11
+
at 0xD0000000..0xD7FFFFFF [cached]
12
+
or 0xD8000000..0xDFFFFFFF [uncached];
13
+
in any case, initially runs elsewhere
14
+
than linked, so have to be careful)
15
+
16
+
The code has the following assumptions:
17
+
This code fragment is run only on an MMU v3.
18
+
TLBs are in their reset state.
19
+
ITLBCFG and DTLBCFG are zero (reset state).
20
+
RASID is 0x04030201 (reset state).
21
+
PS.RING is zero (reset state).
22
+
LITBASE is zero (reset state, PC-relative literals); required to be PIC.
23
+
24
+
TLB setup proceeds along the following steps.
25
+
26
+
Legend:
27
+
VA = virtual address (two upper nibbles of it);
28
+
PA = physical address (two upper nibbles of it);
29
+
pc = physical range that contains this code;
30
+
31
+
After step 2, we jump to virtual address in 0x40000000..0x5fffffff
32
+
that corresponds to next instruction to execute in this code.
33
+
After step 4, we jump to intended (linked) address of this code.
34
+
35
+
Step 0 Step1 Step 2 Step3 Step 4 Step5
36
+
============ ===== ============ ===== ============ =====
37
+
VA PA PA VA PA PA VA PA PA
38
+
------ -- -- ------ -- -- ------ -- --
39
+
E0..FF -> E0 -> E0 E0..FF -> E0 F0..FF -> F0 -> F0
40
+
C0..DF -> C0 -> C0 C0..DF -> C0 E0..EF -> F0 -> F0
41
+
A0..BF -> A0 -> A0 A0..BF -> A0 D8..DF -> 00 -> 00
42
+
80..9F -> 80 -> 80 80..9F -> 80 D0..D7 -> 00 -> 00
43
+
60..7F -> 60 -> 60 60..7F -> 60
44
+
40..5F -> 40 40..5F -> pc -> pc 40..5F -> pc
45
+
20..3F -> 20 -> 20 20..3F -> 20
46
+
00..1F -> 00 -> 00 00..1F -> 00
+39
-18
arch/xtensa/Kconfig
+39
-18
arch/xtensa/Kconfig
···
1
-
config FRAME_POINTER
2
-
def_bool n
3
-
4
1
config ZONE_DMA
5
2
def_bool y
6
3
7
4
config XTENSA
8
5
def_bool y
6
+
select ARCH_WANT_FRAME_POINTERS
9
7
select HAVE_IDE
10
8
select GENERIC_ATOMIC64
11
9
select HAVE_GENERIC_HARDIRQS
···
46
48
47
49
source "init/Kconfig"
48
50
source "kernel/Kconfig.freezer"
51
+
52
+
config LOCKDEP_SUPPORT
53
+
def_bool y
54
+
55
+
config STACKTRACE_SUPPORT
56
+
def_bool y
57
+
58
+
config TRACE_IRQFLAGS_SUPPORT
59
+
def_bool y
49
60
50
61
config MMU
51
62
def_bool n
···
106
99
bool "Math emulation"
107
100
help
108
101
Can we use information of configuration file?
102
+
103
+
config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
104
+
bool "Initialize Xtensa MMU inside the Linux kernel code"
105
+
default y
106
+
help
107
+
Earlier version initialized the MMU in the exception vector
108
+
before jumping to _startup in head.S and had an advantage that
109
+
it was possible to place a software breakpoint at 'reset' and
110
+
then enter your normal kernel breakpoints once the MMU was mapped
111
+
to the kernel mappings (0XC0000000).
112
+
113
+
This unfortunately doesn't work for U-Boot and likley also wont
114
+
work for using KEXEC to have a hot kernel ready for doing a
115
+
KDUMP.
116
+
117
+
So now the MMU is initialized in head.S but it's necessary to
118
+
use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
119
+
xt-gdb can't place a Software Breakpoint in the 0XD region prior
120
+
to mapping the MMU and after mapping even if the area of low memory
121
+
was mapped gdb wouldn't remove the breakpoint on hitting it as the
122
+
PC wouldn't match. Since Hardware Breakpoints are recommended for
123
+
Linux configurations it seems reasonable to just assume they exist
124
+
and leave this older mechanism for unfortunate souls that choose
125
+
not to follow Tensilica's recommendation.
126
+
127
+
Selecting this will cause U-Boot to set the KERNEL Load and Entry
128
+
address at 0x00003000 instead of the mapped std of 0xD0003000.
129
+
130
+
If in doubt, say Y.
109
131
110
132
endmenu
111
133
···
284
248
endmenu
285
249
286
250
menu "Executable file formats"
287
-
288
-
# only elf supported
289
-
config KCORE_ELF
290
-
def_bool y
291
-
depends on PROC_FS
292
-
help
293
-
If you enabled support for /proc file system then the file
294
-
/proc/kcore will contain the kernel core image in ELF format. This
295
-
can be used in gdb:
296
-
297
-
$ cd /usr/src/linux ; gdb vmlinux /proc/kcore
298
-
299
-
This is especially useful if you have compiled the kernel with the
300
-
"-g" option to preserve debugging information. It is mainly used
301
-
for examining kernel data structures on the live kernel.
302
251
303
252
source "fs/Kconfig.binfmt"
304
253
+1
arch/xtensa/boot/boot-elf/Makefile
+1
arch/xtensa/boot/boot-elf/Makefile
+26
-38
arch/xtensa/boot/boot-elf/boot.lds.S
+26
-38
arch/xtensa/boot/boot-elf/boot.lds.S
···
1
-
#include <variant/core.h>
1
+
/*
2
+
* linux/arch/xtensa/boot/boot-elf/boot.lds.S
3
+
*
4
+
* Copyright (C) 2008 - 2013 by Tensilica Inc.
5
+
*
6
+
* Chris Zankel <chris@zankel.net>
7
+
* Marc Gauthier <marc@tensilica.com
8
+
* Pete Delaney <piet@tensilica.com>
9
+
*
10
+
* This program is free software; you can redistribute it and/or modify
11
+
* it under the terms of the GNU General Public License version 2 as
12
+
* published by the Free Software Foundation.
13
+
*/
14
+
15
+
#include <asm/vectors.h>
2
16
OUTPUT_ARCH(xtensa)
3
17
ENTRY(_ResetVector)
4
18
5
19
SECTIONS
6
20
{
7
-
.start 0xD0000000 : { *(.start) }
8
-
9
-
.text 0xD0000000:
21
+
.ResetVector.text XCHAL_RESET_VECTOR_VADDR :
10
22
{
11
-
__reloc_start = . ;
12
-
_text_start = . ;
13
-
*(.literal .text.literal .text)
14
-
_text_end = . ;
23
+
*(.ResetVector.text)
15
24
}
16
25
17
-
.rodata ALIGN(0x04):
18
-
{
19
-
*(.rodata)
20
-
*(.rodata1)
21
-
}
22
-
23
-
.data ALIGN(0x04):
24
-
{
25
-
*(.data)
26
-
*(.data1)
27
-
*(.sdata)
28
-
*(.sdata2)
29
-
*(.got.plt)
30
-
*(.got)
31
-
*(.dynamic)
32
-
}
33
-
34
-
__reloc_end = . ;
35
-
36
-
. = ALIGN(0x10);
37
-
__image_load = . ;
38
-
.image 0xd0001000:
26
+
.image KERNELOFFSET: AT (LOAD_MEMORY_ADDRESS)
39
27
{
40
28
_image_start = .;
41
29
*(image)
42
30
. = (. + 3) & ~ 3;
43
31
_image_end = . ;
44
32
}
45
-
46
33
47
34
.bss ((LOADADDR(.image) + SIZEOF(.image) + 3) & ~ 3):
48
35
{
···
40
53
*(.bss)
41
54
__bss_end = .;
42
55
}
43
-
_end = .;
44
-
_param_start = .;
45
56
46
-
.ResetVector.text XCHAL_RESET_VECTOR_VADDR :
57
+
/*
58
+
* This is a remapped copy of the Reset Vector Code.
59
+
* It keeps gdb in sync with the PC after switching
60
+
* to the temporary mapping used while setting up
61
+
* the V2 MMU mappings for Linux.
62
+
*/
63
+
.ResetVector.remapped_text 0x46000000 (INFO):
47
64
{
48
-
*(.ResetVector.text)
65
+
*(.ResetVector.remapped_text)
49
66
}
50
-
51
-
52
-
PROVIDE (end = .);
53
67
}
+86
-15
arch/xtensa/boot/boot-elf/bootstrap.S
+86
-15
arch/xtensa/boot/boot-elf/bootstrap.S
···
1
+
/*
2
+
* arch/xtensa/boot/boot-elf/bootstrap.S
3
+
*
4
+
* Low-level exception handling
5
+
*
6
+
* This file is subject to the terms and conditions of the GNU General Public
7
+
* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*
10
+
* Copyright (C) 2004 - 2013 by Tensilica Inc.
11
+
*
12
+
* Chris Zankel <chris@zankel.net>
13
+
* Marc Gauthier <marc@tensilica.com>
14
+
* Piet Delaney <piet@tensilica.com>
15
+
*/
1
16
2
17
#include <asm/bootparam.h>
18
+
#include <asm/processor.h>
19
+
#include <asm/pgtable.h>
20
+
#include <asm/page.h>
21
+
#include <asm/cacheasm.h>
22
+
#include <asm/initialize_mmu.h>
23
+
#include <linux/linkage.h>
3
24
4
-
5
-
/* ResetVector
6
-
*/
7
-
.section .ResetVector.text, "ax"
25
+
.section .ResetVector.text, "ax"
8
26
.global _ResetVector
27
+
.global reset
28
+
9
29
_ResetVector:
10
-
_j reset
30
+
_j _SetupMMU
31
+
32
+
.begin no-absolute-literals
33
+
.literal_position
34
+
11
35
.align 4
12
36
RomInitAddr:
13
-
.word 0xd0001000
37
+
#if defined(CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) && \
38
+
XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
39
+
.word 0x00003000
40
+
#else
41
+
.word 0xd0003000
42
+
#endif
14
43
RomBootParam:
15
44
.word _bootparam
45
+
_bootparam:
46
+
.short BP_TAG_FIRST
47
+
.short 4
48
+
.long BP_VERSION
49
+
.short BP_TAG_LAST
50
+
.short 0
51
+
.long 0
52
+
53
+
.align 4
54
+
_SetupMMU:
55
+
movi a0, 0
56
+
wsr a0, windowbase
57
+
rsync
58
+
movi a0, 1
59
+
wsr a0, windowstart
60
+
rsync
61
+
movi a0, 0x1F
62
+
wsr a0, ps
63
+
rsync
64
+
65
+
Offset = _SetupMMU - _ResetVector
66
+
67
+
#ifndef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
68
+
initialize_mmu
69
+
#endif
70
+
71
+
.end no-absolute-literals
72
+
73
+
rsil a0, XCHAL_DEBUGLEVEL-1
74
+
rsync
16
75
reset:
17
76
l32r a0, RomInitAddr
18
77
l32r a2, RomBootParam
···
80
21
jx a0
81
22
82
23
.align 4
83
-
.section .bootstrap.data, "aw"
84
24
85
-
.globl _bootparam
86
-
_bootparam:
87
-
.short BP_TAG_FIRST
88
-
.short 4
89
-
.long BP_VERSION
90
-
.short BP_TAG_LAST
91
-
.short 0
92
-
.long 0
25
+
.section .ResetVector.remapped_text, "x"
26
+
.global _RemappedResetVector
27
+
28
+
/* Do org before literals */
29
+
.org 0
30
+
31
+
_RemappedResetVector:
32
+
.begin no-absolute-literals
33
+
.literal_position
34
+
35
+
_j _RemappedSetupMMU
36
+
37
+
/* Position Remapped code at the same location as the original code */
38
+
. = _RemappedResetVector + Offset
39
+
40
+
_RemappedSetupMMU:
41
+
#ifndef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
42
+
initialize_mmu
43
+
#endif
44
+
45
+
.end no-absolute-literals
+1
-1
arch/xtensa/boot/boot-redboot/boot.ld
+1
-1
arch/xtensa/boot/boot-redboot/boot.ld
+5
-1
arch/xtensa/boot/boot-uboot/Makefile
+5
-1
arch/xtensa/boot/boot-uboot/Makefile
+1
arch/xtensa/include/asm/Kbuild
+1
arch/xtensa/include/asm/Kbuild
+33
-1
arch/xtensa/include/asm/ftrace.h
+33
-1
arch/xtensa/include/asm/ftrace.h
···
1
-
/* empty */
1
+
/*
2
+
* arch/xtensa/include/asm/ftrace.h
3
+
*
4
+
* This file is subject to the terms and conditions of the GNU General Public
5
+
* License. See the file "COPYING" in the main directory of this archive
6
+
* for more details.
7
+
*
8
+
* Copyright (C) 2013 Tensilica Inc.
9
+
*/
10
+
#ifndef _XTENSA_FTRACE_H
11
+
#define _XTENSA_FTRACE_H
12
+
13
+
#include <asm/processor.h>
14
+
15
+
#define HAVE_ARCH_CALLER_ADDR
16
+
#define CALLER_ADDR0 ({ unsigned long a0, a1; \
17
+
__asm__ __volatile__ ( \
18
+
"mov %0, a0\n" \
19
+
"mov %1, a1\n" \
20
+
: "=r"(a0), "=r"(a1) : : ); \
21
+
MAKE_PC_FROM_RA(a0, a1); })
22
+
#ifdef CONFIG_FRAME_POINTER
23
+
extern unsigned long return_address(unsigned level);
24
+
#define CALLER_ADDR1 return_address(1)
25
+
#define CALLER_ADDR2 return_address(2)
26
+
#define CALLER_ADDR3 return_address(3)
27
+
#else
28
+
#define CALLER_ADDR1 (0)
29
+
#define CALLER_ADDR2 (0)
30
+
#define CALLER_ADDR3 (0)
31
+
#endif
32
+
33
+
#endif /* _XTENSA_FTRACE_H */
+107
arch/xtensa/include/asm/initialize_mmu.h
+107
arch/xtensa/include/asm/initialize_mmu.h
···
23
23
#ifndef _XTENSA_INITIALIZE_MMU_H
24
24
#define _XTENSA_INITIALIZE_MMU_H
25
25
26
+
#include <asm/pgtable.h>
27
+
#include <asm/vectors.h>
28
+
26
29
#ifdef __ASSEMBLY__
27
30
28
31
#define XTENSA_HWVERSION_RC_2009_0 230000
···
50
47
#endif /* XCHAL_HAVE_S32C1I &&
51
48
* (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
52
49
*/
50
+
51
+
#if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
52
+
/*
53
+
* Have MMU v3
54
+
*/
55
+
56
+
#if !XCHAL_HAVE_VECBASE
57
+
# error "MMU v3 requires reloc vectors"
58
+
#endif
59
+
60
+
movi a1, 0
61
+
_call0 1f
62
+
_j 2f
63
+
64
+
.align 4
65
+
1: movi a2, 0x10000000
66
+
movi a3, 0x18000000
67
+
add a2, a2, a0
68
+
9: bgeu a2, a3, 9b /* PC is out of the expected range */
69
+
70
+
/* Step 1: invalidate mapping at 0x40000000..0x5FFFFFFF. */
71
+
72
+
movi a2, 0x40000006
73
+
idtlb a2
74
+
iitlb a2
75
+
isync
76
+
77
+
/* Step 2: map 0x40000000..0x47FFFFFF to paddr containing this code
78
+
* and jump to the new mapping.
79
+
*/
80
+
#define CA_BYPASS (_PAGE_CA_BYPASS | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
81
+
#define CA_WRITEBACK (_PAGE_CA_WB | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
82
+
83
+
srli a3, a0, 27
84
+
slli a3, a3, 27
85
+
addi a3, a3, CA_BYPASS
86
+
addi a7, a2, -1
87
+
wdtlb a3, a7
88
+
witlb a3, a7
89
+
isync
90
+
91
+
slli a4, a0, 5
92
+
srli a4, a4, 5
93
+
addi a5, a2, -6
94
+
add a4, a4, a5
95
+
jx a4
96
+
97
+
/* Step 3: unmap everything other than current area.
98
+
* Start at 0x60000000, wrap around, and end with 0x20000000
99
+
*/
100
+
2: movi a4, 0x20000000
101
+
add a5, a2, a4
102
+
3: idtlb a5
103
+
iitlb a5
104
+
add a5, a5, a4
105
+
bne a5, a2, 3b
106
+
107
+
/* Step 4: Setup MMU with the old V2 mappings. */
108
+
movi a6, 0x01000000
109
+
wsr a6, ITLBCFG
110
+
wsr a6, DTLBCFG
111
+
isync
112
+
113
+
movi a5, 0xd0000005
114
+
movi a4, CA_WRITEBACK
115
+
wdtlb a4, a5
116
+
witlb a4, a5
117
+
118
+
movi a5, 0xd8000005
119
+
movi a4, CA_BYPASS
120
+
wdtlb a4, a5
121
+
witlb a4, a5
122
+
123
+
movi a5, 0xe0000006
124
+
movi a4, 0xf0000000 + CA_WRITEBACK
125
+
wdtlb a4, a5
126
+
witlb a4, a5
127
+
128
+
movi a5, 0xf0000006
129
+
movi a4, 0xf0000000 + CA_BYPASS
130
+
wdtlb a4, a5
131
+
witlb a4, a5
132
+
133
+
isync
134
+
135
+
/* Jump to self, using MMU v2 mappings. */
136
+
movi a4, 1f
137
+
jx a4
138
+
139
+
1:
140
+
movi a2, VECBASE_RESET_VADDR
141
+
wsr a2, vecbase
142
+
143
+
/* Step 5: remove temporary mapping. */
144
+
idtlb a7
145
+
iitlb a7
146
+
isync
147
+
148
+
movi a0, 0
149
+
wsr a0, ptevaddr
150
+
rsync
151
+
152
+
#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
153
+
XCHAL_HAVE_SPANNING_WAY */
53
154
54
155
.endm
55
156
+4
-1
arch/xtensa/include/asm/irqflags.h
+4
-1
arch/xtensa/include/asm/irqflags.h
···
47
47
48
48
static inline bool arch_irqs_disabled_flags(unsigned long flags)
49
49
{
50
-
return (flags & 0xf) != 0;
50
+
#if XCHAL_EXCM_LEVEL < LOCKLEVEL || (1 << PS_EXCM_BIT) < LOCKLEVEL
51
+
#error "XCHAL_EXCM_LEVEL and 1<<PS_EXCM_BIT must be no less than LOCKLEVEL"
52
+
#endif
53
+
return (flags & (PS_INTLEVEL_MASK | (1 << PS_EXCM_BIT))) >= LOCKLEVEL;
51
54
}
52
55
53
56
static inline bool arch_irqs_disabled(void)
-16
arch/xtensa/include/asm/linkage.h
-16
arch/xtensa/include/asm/linkage.h
···
1
-
/*
2
-
* include/asm-xtensa/linkage.h
3
-
*
4
-
* This file is subject to the terms and conditions of the GNU General Public
5
-
* License. See the file "COPYING" in the main directory of this archive
6
-
* for more details.
7
-
*
8
-
* Copyright (C) 2001 - 2005 Tensilica Inc.
9
-
*/
10
-
11
-
#ifndef _XTENSA_LINKAGE_H
12
-
#define _XTENSA_LINKAGE_H
13
-
14
-
/* Nothing to do here ... */
15
-
16
-
#endif /* _XTENSA_LINKAGE_H */
+36
arch/xtensa/include/asm/stacktrace.h
+36
arch/xtensa/include/asm/stacktrace.h
···
1
+
/*
2
+
* arch/xtensa/include/asm/stacktrace.h
3
+
*
4
+
* This file is subject to the terms and conditions of the GNU General Public
5
+
* License. See the file "COPYING" in the main directory of this archive
6
+
* for more details.
7
+
*
8
+
* Copyright (C) 2001 - 2013 Tensilica Inc.
9
+
*/
10
+
#ifndef _XTENSA_STACKTRACE_H
11
+
#define _XTENSA_STACKTRACE_H
12
+
13
+
#include <linux/sched.h>
14
+
15
+
struct stackframe {
16
+
unsigned long pc;
17
+
unsigned long sp;
18
+
};
19
+
20
+
static __always_inline unsigned long *stack_pointer(struct task_struct *task)
21
+
{
22
+
unsigned long *sp;
23
+
24
+
if (!task || task == current)
25
+
__asm__ __volatile__ ("mov %0, a1\n" : "=a"(sp));
26
+
else
27
+
sp = (unsigned long *)task->thread.sp;
28
+
29
+
return sp;
30
+
}
31
+
32
+
void walk_stackframe(unsigned long *sp,
33
+
int (*fn)(struct stackframe *frame, void *data),
34
+
void *data);
35
+
36
+
#endif /* _XTENSA_STACKTRACE_H */
+6
-3
arch/xtensa/include/asm/timex.h
+6
-3
arch/xtensa/include/asm/timex.h
···
19
19
#define _INTLEVEL(x) XCHAL_INT ## x ## _LEVEL
20
20
#define INTLEVEL(x) _INTLEVEL(x)
21
21
22
-
#if INTLEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
22
+
#if XCHAL_NUM_TIMERS > 0 && \
23
+
INTLEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
23
24
# define LINUX_TIMER 0
24
25
# define LINUX_TIMER_INT XCHAL_TIMER0_INTERRUPT
25
-
#elif INTLEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
26
+
#elif XCHAL_NUM_TIMERS > 1 && \
27
+
INTLEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
26
28
# define LINUX_TIMER 1
27
29
# define LINUX_TIMER_INT XCHAL_TIMER1_INTERRUPT
28
-
#elif INTLEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
30
+
#elif XCHAL_NUM_TIMERS > 2 && \
31
+
INTLEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
29
32
# define LINUX_TIMER 2
30
33
# define LINUX_TIMER_INT XCHAL_TIMER2_INTERRUPT
31
34
#else
+2
-3
arch/xtensa/include/asm/traps.h
+2
-3
arch/xtensa/include/asm/traps.h
···
22
22
23
23
static inline void spill_registers(void)
24
24
{
25
-
unsigned int a0, ps;
26
25
27
26
__asm__ __volatile__ (
28
-
"movi a14, " __stringify(PS_EXCM_BIT | LOCKLEVEL) "\n\t"
27
+
"movi a14, "__stringify((1 << PS_EXCM_BIT) | LOCKLEVEL)"\n\t"
29
28
"mov a12, a0\n\t"
30
29
"rsr a13, sar\n\t"
31
30
"xsr a14, ps\n\t"
···
34
35
"mov a0, a12\n\t"
35
36
"wsr a13, sar\n\t"
36
37
"wsr a14, ps\n\t"
37
-
: : "a" (&a0), "a" (&ps)
38
+
: :
38
39
#if defined(CONFIG_FRAME_POINTER)
39
40
: "a2", "a3", "a4", "a11", "a12", "a13", "a14", "a15",
40
41
#else
+125
arch/xtensa/include/asm/vectors.h
+125
arch/xtensa/include/asm/vectors.h
···
1
+
/*
2
+
* arch/xtensa/include/asm/xchal_vaddr_remap.h
3
+
*
4
+
* Xtensa macros for MMU V3 Support. Deals with re-mapping the Virtual
5
+
* Memory Addresses from "Virtual == Physical" to their prevvious V2 MMU
6
+
* mappings (KSEG at 0xD0000000 and KIO at 0XF0000000).
7
+
*
8
+
* This file is subject to the terms and conditions of the GNU General Public
9
+
* License. See the file "COPYING" in the main directory of this archive
10
+
* for more details.
11
+
*
12
+
* Copyright (C) 2008 - 2012 Tensilica Inc.
13
+
*
14
+
* Pete Delaney <piet@tensilica.com>
15
+
* Marc Gauthier <marc@tensilica.com
16
+
*/
17
+
18
+
#ifndef _XTENSA_VECTORS_H
19
+
#define _XTENSA_VECTORS_H
20
+
21
+
#include <variant/core.h>
22
+
23
+
#if defined(CONFIG_MMU)
24
+
25
+
/* Will Become VECBASE */
26
+
#define VIRTUAL_MEMORY_ADDRESS 0xD0000000
27
+
28
+
/* Image Virtual Start Address */
29
+
#define KERNELOFFSET 0xD0003000
30
+
31
+
#if defined(XCHAL_HAVE_PTP_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
32
+
/* MMU v3 - XCHAL_HAVE_PTP_MMU == 1 */
33
+
#define PHYSICAL_MEMORY_ADDRESS 0x00000000
34
+
#define LOAD_MEMORY_ADDRESS 0x00003000
35
+
#else
36
+
/* MMU V2 - XCHAL_HAVE_PTP_MMU == 0 */
37
+
#define PHYSICAL_MEMORY_ADDRESS 0xD0000000
38
+
#define LOAD_MEMORY_ADDRESS 0xD0003000
39
+
#endif
40
+
41
+
#else /* !defined(CONFIG_MMU) */
42
+
/* MMU Not being used - Virtual == Physical */
43
+
44
+
/* VECBASE */
45
+
#define VIRTUAL_MEMORY_ADDRESS 0x00002000
46
+
47
+
/* Location of the start of the kernel text, _start */
48
+
#define KERNELOFFSET 0x00003000
49
+
#define PHYSICAL_MEMORY_ADDRESS 0x00000000
50
+
51
+
/* Loaded just above possibly live vectors */
52
+
#define LOAD_MEMORY_ADDRESS 0x00003000
53
+
54
+
#endif /* CONFIG_MMU */
55
+
56
+
#define XC_VADDR(offset) (VIRTUAL_MEMORY_ADDRESS + offset)
57
+
#define XC_PADDR(offset) (PHYSICAL_MEMORY_ADDRESS + offset)
58
+
59
+
/* Used to set VECBASE register */
60
+
#define VECBASE_RESET_VADDR VIRTUAL_MEMORY_ADDRESS
61
+
62
+
#define RESET_VECTOR_VECOFS (XCHAL_RESET_VECTOR_VADDR - \
63
+
VECBASE_RESET_VADDR)
64
+
#define RESET_VECTOR_VADDR XC_VADDR(RESET_VECTOR_VECOFS)
65
+
66
+
#define RESET_VECTOR1_VECOFS (XCHAL_RESET_VECTOR1_VADDR - \
67
+
VECBASE_RESET_VADDR)
68
+
#define RESET_VECTOR1_VADDR XC_VADDR(RESET_VECTOR1_VECOFS)
69
+
70
+
#if XCHAL_HAVE_VECBASE
71
+
72
+
#define USER_VECTOR_VADDR XC_VADDR(XCHAL_USER_VECOFS)
73
+
#define KERNEL_VECTOR_VADDR XC_VADDR(XCHAL_KERNEL_VECOFS)
74
+
#define DOUBLEEXC_VECTOR_VADDR XC_VADDR(XCHAL_DOUBLEEXC_VECOFS)
75
+
#define WINDOW_VECTORS_VADDR XC_VADDR(XCHAL_WINDOW_OF4_VECOFS)
76
+
#define INTLEVEL2_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL2_VECOFS)
77
+
#define INTLEVEL3_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL3_VECOFS)
78
+
#define INTLEVEL4_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL4_VECOFS)
79
+
#define INTLEVEL5_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL5_VECOFS)
80
+
#define INTLEVEL6_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL6_VECOFS)
81
+
82
+
#define DEBUG_VECTOR_VADDR XC_VADDR(XCHAL_DEBUG_VECOFS)
83
+
84
+
#undef XCHAL_NMI_VECTOR_VADDR
85
+
#define XCHAL_NMI_VECTOR_VADDR XC_VADDR(XCHAL_NMI_VECOFS)
86
+
87
+
#undef XCHAL_INTLEVEL7_VECTOR_VADDR
88
+
#define XCHAL_INTLEVEL7_VECTOR_VADDR XC_VADDR(XCHAL_INTLEVEL7_VECOFS)
89
+
90
+
/*
91
+
* These XCHAL_* #defines from varian/core.h
92
+
* are not valid to use with V3 MMU. Non-XCHAL
93
+
* constants are defined above and should be used.
94
+
*/
95
+
#undef XCHAL_VECBASE_RESET_VADDR
96
+
#undef XCHAL_RESET_VECTOR0_VADDR
97
+
#undef XCHAL_USER_VECTOR_VADDR
98
+
#undef XCHAL_KERNEL_VECTOR_VADDR
99
+
#undef XCHAL_DOUBLEEXC_VECTOR_VADDR
100
+
#undef XCHAL_WINDOW_VECTORS_VADDR
101
+
#undef XCHAL_INTLEVEL2_VECTOR_VADDR
102
+
#undef XCHAL_INTLEVEL3_VECTOR_VADDR
103
+
#undef XCHAL_INTLEVEL4_VECTOR_VADDR
104
+
#undef XCHAL_INTLEVEL5_VECTOR_VADDR
105
+
#undef XCHAL_INTLEVEL6_VECTOR_VADDR
106
+
#undef XCHAL_DEBUG_VECTOR_VADDR
107
+
#undef XCHAL_NMI_VECTOR_VADDR
108
+
#undef XCHAL_INTLEVEL7_VECTOR_VADDR
109
+
110
+
#else
111
+
112
+
#define USER_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR
113
+
#define KERNEL_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR
114
+
#define DOUBLEEXC_VECTOR_VADDR XCHAL_DOUBLEEXC_VECTOR_VADDR
115
+
#define WINDOW_VECTORS_VADDR XCHAL_WINDOW_VECTORS_VADDR
116
+
#define INTLEVEL2_VECTOR_VADDR XCHAL_INTLEVEL2_VECTOR_VADDR
117
+
#define INTLEVEL3_VECTOR_VADDR XCHAL_INTLEVEL3_VECTOR_VADDR
118
+
#define INTLEVEL4_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
119
+
#define INTLEVEL5_VECTOR_VADDR XCHAL_INTLEVEL5_VECTOR_VADDR
120
+
#define INTLEVEL6_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
121
+
#define DEBUG_VECTOR_VADDR XCHAL_DEBUG_VECTOR_VADDR
122
+
123
+
#endif
124
+
125
+
#endif /* _XTENSA_VECTORS_H */
+5
-3
arch/xtensa/kernel/Makefile
+5
-3
arch/xtensa/kernel/Makefile
···
4
4
5
5
extra-y := head.o vmlinux.lds
6
6
7
-
obj-y := align.o entry.o irq.o coprocessor.o process.o ptrace.o \
8
-
setup.o signal.o syscall.o time.o traps.o vectors.o platform.o \
9
-
pci-dma.o
7
+
obj-y := align.o coprocessor.o entry.o irq.o pci-dma.o platform.o process.o \
8
+
ptrace.o setup.o signal.o stacktrace.o syscall.o time.o traps.o \
9
+
vectors.o
10
10
11
11
obj-$(CONFIG_KGDB) += xtensa-stub.o
12
12
obj-$(CONFIG_PCI) += pci.o
13
13
obj-$(CONFIG_MODULES) += xtensa_ksyms.o module.o
14
+
15
+
AFLAGS_head.o += -mtext-section-literals
14
16
15
17
# In the Xtensa architecture, assembly generates literals which must always
16
18
# precede the L32R instruction with a relative offset less than 256 kB.
+44
-42
arch/xtensa/kernel/entry.S
+44
-42
arch/xtensa/kernel/entry.S
···
354
354
* so we can allow exceptions and interrupts (*) again.
355
355
* Set PS(EXCM = 0, UM = 0, RING = 0, OWB = 0, WOE = 1, INTLEVEL = X)
356
356
*
357
-
* (*) We only allow interrupts of higher priority than current IRQ
357
+
* (*) We only allow interrupts if they were previously enabled and
358
+
* we're not handling an IRQ
358
359
*/
359
360
360
361
rsr a3, ps
361
-
addi a0, a0, -4
362
-
movi a2, 1
362
+
addi a0, a0, -EXCCAUSE_LEVEL1_INTERRUPT
363
+
movi a2, LOCKLEVEL
363
364
extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
364
365
# a3 = PS.INTLEVEL
365
-
movnez a2, a3, a3 # a2 = 1: level-1, > 1: high priority
366
-
moveqz a3, a2, a0 # a3 = IRQ level iff interrupt
366
+
moveqz a3, a2, a0 # a3 = LOCKLEVEL iff interrupt
367
367
movi a2, 1 << PS_WOE_BIT
368
368
or a3, a3, a2
369
369
rsr a0, exccause
···
389
389
390
390
save_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT
391
391
392
+
#ifdef CONFIG_TRACE_IRQFLAGS
393
+
l32i a4, a1, PT_DEPC
394
+
/* Double exception means we came here with an exception
395
+
* while PS.EXCM was set, i.e. interrupts disabled.
396
+
*/
397
+
bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
398
+
l32i a4, a1, PT_EXCCAUSE
399
+
bnei a4, EXCCAUSE_LEVEL1_INTERRUPT, 1f
400
+
/* We came here with an interrupt means interrupts were enabled
401
+
* and we've just disabled them.
402
+
*/
403
+
movi a4, trace_hardirqs_off
404
+
callx4 a4
405
+
1:
406
+
#endif
407
+
392
408
/* Go to second-level dispatcher. Set up parameters to pass to the
393
409
* exception handler and call the exception handler.
394
410
*/
···
423
407
.global common_exception_return
424
408
common_exception_return:
425
409
410
+
#ifdef CONFIG_TRACE_IRQFLAGS
411
+
l32i a4, a1, PT_DEPC
412
+
/* Double exception means we came here with an exception
413
+
* while PS.EXCM was set, i.e. interrupts disabled.
414
+
*/
415
+
bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
416
+
l32i a4, a1, PT_EXCCAUSE
417
+
bnei a4, EXCCAUSE_LEVEL1_INTERRUPT, 1f
418
+
/* We came here with an interrupt means interrupts were enabled
419
+
* and we'll reenable them on return.
420
+
*/
421
+
movi a4, trace_hardirqs_on
422
+
callx4 a4
423
+
1:
424
+
#endif
425
+
426
426
/* Jump if we are returning from kernel exceptions. */
427
427
428
428
1: l32i a3, a1, PT_PS
429
429
_bbci.l a3, PS_UM_BIT, 4f
430
+
431
+
rsil a2, 0
430
432
431
433
/* Specific to a user exception exit:
432
434
* We need to check some flags for signal handling and rescheduling,
···
686
652
687
653
l32i a0, a1, PT_DEPC
688
654
l32i a3, a1, PT_AREG3
689
-
_bltui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
690
-
691
-
wsr a0, depc
692
655
l32i a2, a1, PT_AREG2
693
-
l32i a0, a1, PT_AREG0
694
-
l32i a1, a1, PT_AREG1
695
-
rfde
656
+
_bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
696
657
697
-
1:
698
658
/* Restore a0...a3 and return */
699
659
700
-
rsr a0, ps
701
-
extui a2, a0, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
702
-
movi a0, 2f
703
-
slli a2, a2, 4
704
-
add a0, a2, a0
705
-
l32i a2, a1, PT_AREG2
706
-
jx a0
707
-
708
-
.macro irq_exit_level level
709
-
.align 16
710
-
.if XCHAL_EXCM_LEVEL >= \level
711
-
l32i a0, a1, PT_PC
712
-
wsr a0, epc\level
713
-
l32i a0, a1, PT_AREG0
714
-
l32i a1, a1, PT_AREG1
715
-
rfi \level
716
-
.endif
717
-
.endm
718
-
719
-
.align 16
720
-
2:
721
660
l32i a0, a1, PT_AREG0
722
661
l32i a1, a1, PT_AREG1
723
662
rfe
724
663
725
-
.align 16
726
-
/* no rfi for level-1 irq, handled by rfe above*/
727
-
nop
728
-
729
-
irq_exit_level 2
730
-
irq_exit_level 3
731
-
irq_exit_level 4
732
-
irq_exit_level 5
733
-
irq_exit_level 6
664
+
1: wsr a0, depc
665
+
l32i a0, a1, PT_AREG0
666
+
l32i a1, a1, PT_AREG1
667
+
rfde
734
668
735
669
ENDPROC(kernel_exception)
736
670
+29
-10
arch/xtensa/kernel/head.S
+29
-10
arch/xtensa/kernel/head.S
···
48
48
*/
49
49
50
50
__HEAD
51
+
.begin no-absolute-literals
52
+
51
53
ENTRY(_start)
52
54
53
-
_j 2f
55
+
/* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
56
+
wsr a2, excsave1
57
+
_j _SetupMMU
58
+
54
59
.align 4
55
-
1: .word _startup
56
-
2: l32r a0, 1b
60
+
.literal_position
61
+
.Lstartup:
62
+
.word _startup
63
+
64
+
.align 4
65
+
.global _SetupMMU
66
+
_SetupMMU:
67
+
Offset = _SetupMMU - _start
68
+
69
+
#ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
70
+
initialize_mmu
71
+
#endif
72
+
.end no-absolute-literals
73
+
74
+
l32r a0, .Lstartup
57
75
jx a0
58
76
59
77
ENDPROC(_start)
60
78
61
-
.section .init.text, "ax"
79
+
__INIT
80
+
.literal_position
62
81
63
82
ENTRY(_startup)
64
83
···
85
66
86
67
movi a0, LOCKLEVEL
87
68
wsr a0, ps
88
-
89
-
/* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
90
-
91
-
wsr a2, excsave1
92
69
93
70
/* Start with a fresh windowbase and windowstart. */
94
71
···
101
86
/* Clear debugging registers. */
102
87
103
88
#if XCHAL_HAVE_DEBUG
89
+
#if XCHAL_NUM_IBREAK > 0
104
90
wsr a0, ibreakenable
91
+
#endif
105
92
wsr a0, icount
106
93
movi a1, 15
107
94
wsr a0, icountlevel
···
173
156
174
157
isync
175
158
176
-
initialize_mmu
177
-
178
159
/* Unpack data sections
179
160
*
180
161
* The linker script used to build the Linux kernel image
···
220
205
221
206
___flush_dcache_all a2 a3
222
207
#endif
208
+
memw
209
+
isync
210
+
___invalidate_icache_all a2 a3
211
+
isync
223
212
224
213
/* Setup stack and enable window exceptions (keep irqs disabled) */
225
214
+1
arch/xtensa/kernel/platform.c
+1
arch/xtensa/kernel/platform.c
···
36
36
_F(void, idle, (void), { __asm__ __volatile__ ("waiti 0" ::: "memory"); });
37
37
_F(void, heartbeat, (void), { });
38
38
_F(int, pcibios_fixup, (void), { return 0; });
39
+
_F(void, pcibios_init, (void), { });
39
40
40
41
#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
41
42
_F(void, calibrate_ccount, (void),
+120
arch/xtensa/kernel/stacktrace.c
+120
arch/xtensa/kernel/stacktrace.c
···
1
+
/*
2
+
* arch/xtensa/kernel/stacktrace.c
3
+
*
4
+
* This file is subject to the terms and conditions of the GNU General Public
5
+
* License. See the file "COPYING" in the main directory of this archive
6
+
* for more details.
7
+
*
8
+
* Copyright (C) 2001 - 2013 Tensilica Inc.
9
+
*/
10
+
#include <linux/export.h>
11
+
#include <linux/sched.h>
12
+
#include <linux/stacktrace.h>
13
+
14
+
#include <asm/stacktrace.h>
15
+
#include <asm/traps.h>
16
+
17
+
void walk_stackframe(unsigned long *sp,
18
+
int (*fn)(struct stackframe *frame, void *data),
19
+
void *data)
20
+
{
21
+
unsigned long a0, a1;
22
+
unsigned long sp_end;
23
+
24
+
a1 = (unsigned long)sp;
25
+
sp_end = ALIGN(a1, THREAD_SIZE);
26
+
27
+
spill_registers();
28
+
29
+
while (a1 < sp_end) {
30
+
struct stackframe frame;
31
+
32
+
sp = (unsigned long *)a1;
33
+
34
+
a0 = *(sp - 4);
35
+
a1 = *(sp - 3);
36
+
37
+
if (a1 <= (unsigned long)sp)
38
+
break;
39
+
40
+
frame.pc = MAKE_PC_FROM_RA(a0, a1);
41
+
frame.sp = a1;
42
+
43
+
if (fn(&frame, data))
44
+
return;
45
+
}
46
+
}
47
+
48
+
#ifdef CONFIG_STACKTRACE
49
+
50
+
struct stack_trace_data {
51
+
struct stack_trace *trace;
52
+
unsigned skip;
53
+
};
54
+
55
+
static int stack_trace_cb(struct stackframe *frame, void *data)
56
+
{
57
+
struct stack_trace_data *trace_data = data;
58
+
struct stack_trace *trace = trace_data->trace;
59
+
60
+
if (trace_data->skip) {
61
+
--trace_data->skip;
62
+
return 0;
63
+
}
64
+
if (!kernel_text_address(frame->pc))
65
+
return 0;
66
+
67
+
trace->entries[trace->nr_entries++] = frame->pc;
68
+
return trace->nr_entries >= trace->max_entries;
69
+
}
70
+
71
+
void save_stack_trace_tsk(struct task_struct *task, struct stack_trace *trace)
72
+
{
73
+
struct stack_trace_data trace_data = {
74
+
.trace = trace,
75
+
.skip = trace->skip,
76
+
};
77
+
walk_stackframe(stack_pointer(task), stack_trace_cb, &trace_data);
78
+
}
79
+
EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
80
+
81
+
void save_stack_trace(struct stack_trace *trace)
82
+
{
83
+
save_stack_trace_tsk(current, trace);
84
+
}
85
+
EXPORT_SYMBOL_GPL(save_stack_trace);
86
+
87
+
#endif
88
+
89
+
#ifdef CONFIG_FRAME_POINTER
90
+
91
+
struct return_addr_data {
92
+
unsigned long addr;
93
+
unsigned skip;
94
+
};
95
+
96
+
static int return_address_cb(struct stackframe *frame, void *data)
97
+
{
98
+
struct return_addr_data *r = data;
99
+
100
+
if (r->skip) {
101
+
--r->skip;
102
+
return 0;
103
+
}
104
+
if (!kernel_text_address(frame->pc))
105
+
return 0;
106
+
r->addr = frame->pc;
107
+
return 1;
108
+
}
109
+
110
+
unsigned long return_address(unsigned level)
111
+
{
112
+
struct return_addr_data r = {
113
+
.skip = level + 1,
114
+
};
115
+
walk_stackframe(stack_pointer(NULL), return_address_cb, &r);
116
+
return r.addr;
117
+
}
118
+
EXPORT_SYMBOL(return_address);
119
+
120
+
#endif
+21
-46
arch/xtensa/kernel/traps.c
+21
-46
arch/xtensa/kernel/traps.c
···
11
11
*
12
12
* Essentially rewritten for the Xtensa architecture port.
13
13
*
14
-
* Copyright (C) 2001 - 2005 Tensilica Inc.
14
+
* Copyright (C) 2001 - 2013 Tensilica Inc.
15
15
*
16
16
* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
17
17
* Chris Zankel <chris@zankel.net>
···
32
32
#include <linux/delay.h>
33
33
#include <linux/hardirq.h>
34
34
35
+
#include <asm/stacktrace.h>
35
36
#include <asm/ptrace.h>
36
37
#include <asm/timex.h>
37
38
#include <asm/uaccess.h>
···
196
195
197
196
/*
198
197
* IRQ handler.
199
-
* PS.INTLEVEL is the current IRQ priority level.
200
198
*/
201
199
202
200
extern void do_IRQ(int, struct pt_regs *);
···
212
212
XCHAL_INTLEVEL6_MASK,
213
213
XCHAL_INTLEVEL7_MASK,
214
214
};
215
-
unsigned level = get_sr(ps) & PS_INTLEVEL_MASK;
216
-
217
-
if (WARN_ON_ONCE(level >= ARRAY_SIZE(int_level_mask)))
218
-
return;
219
215
220
216
for (;;) {
221
217
unsigned intread = get_sr(interrupt);
222
218
unsigned intenable = get_sr(intenable);
223
-
unsigned int_at_level = intread & intenable &
224
-
int_level_mask[level];
219
+
unsigned int_at_level = intread & intenable;
220
+
unsigned level;
225
221
226
-
if (!int_at_level)
222
+
for (level = LOCKLEVEL; level > 0; --level) {
223
+
if (int_at_level & int_level_mask[level]) {
224
+
int_at_level &= int_level_mask[level];
225
+
break;
226
+
}
227
+
}
228
+
229
+
if (level == 0)
227
230
return;
228
231
229
232
/*
···
407
404
regs->syscall);
408
405
}
409
406
410
-
static __always_inline unsigned long *stack_pointer(struct task_struct *task)
407
+
static int show_trace_cb(struct stackframe *frame, void *data)
411
408
{
412
-
unsigned long *sp;
413
-
414
-
if (!task || task == current)
415
-
__asm__ __volatile__ ("mov %0, a1\n" : "=a"(sp));
416
-
else
417
-
sp = (unsigned long *)task->thread.sp;
418
-
419
-
return sp;
409
+
if (kernel_text_address(frame->pc)) {
410
+
printk(" [<%08lx>] ", frame->pc);
411
+
print_symbol("%s\n", frame->pc);
412
+
}
413
+
return 0;
420
414
}
421
415
422
416
void show_trace(struct task_struct *task, unsigned long *sp)
423
417
{
424
-
unsigned long a0, a1, pc;
425
-
unsigned long sp_start, sp_end;
426
-
427
-
if (sp)
428
-
a1 = (unsigned long)sp;
429
-
else
430
-
a1 = (unsigned long)stack_pointer(task);
431
-
432
-
sp_start = a1 & ~(THREAD_SIZE-1);
433
-
sp_end = sp_start + THREAD_SIZE;
418
+
if (!sp)
419
+
sp = stack_pointer(task);
434
420
435
421
printk("Call Trace:");
436
422
#ifdef CONFIG_KALLSYMS
437
423
printk("\n");
438
424
#endif
439
-
spill_registers();
440
-
441
-
while (a1 > sp_start && a1 < sp_end) {
442
-
sp = (unsigned long*)a1;
443
-
444
-
a0 = *(sp - 4);
445
-
a1 = *(sp - 3);
446
-
447
-
if (a1 <= (unsigned long) sp)
448
-
break;
449
-
450
-
pc = MAKE_PC_FROM_RA(a0, a1);
451
-
452
-
if (kernel_text_address(pc)) {
453
-
printk(" [<%08lx>] ", pc);
454
-
print_symbol("%s\n", pc);
455
-
}
456
-
}
425
+
walk_stackframe(sp, show_trace_cb, NULL);
457
426
printk("\n");
458
427
}
459
428
+9
-7
arch/xtensa/kernel/vectors.S
+9
-7
arch/xtensa/kernel/vectors.S
···
50
50
#include <asm/processor.h>
51
51
#include <asm/page.h>
52
52
#include <asm/thread_info.h>
53
+
#include <asm/vectors.h>
53
54
54
55
#define WINDOW_VECTORS_SIZE 0x180
55
56
···
221
220
222
221
xsr a0, depc # get DEPC, save a0
223
222
224
-
movi a3, XCHAL_WINDOW_VECTORS_VADDR
223
+
movi a3, WINDOW_VECTORS_VADDR
225
224
_bltu a0, a3, .Lfixup
226
225
addi a3, a3, WINDOW_VECTORS_SIZE
227
226
_bgeu a0, a3, .Lfixup
···
386
385
.if XCHAL_EXCM_LEVEL >= \level
387
386
.section .Level\level\()InterruptVector.text, "ax"
388
387
ENTRY(_Level\level\()InterruptVector)
389
-
wsr a0, epc1
388
+
wsr a0, excsave2
390
389
rsr a0, epc\level
391
-
xsr a0, epc1
390
+
wsr a0, epc1
391
+
movi a0, EXCCAUSE_LEVEL1_INTERRUPT
392
+
wsr a0, exccause
393
+
rsr a0, eps\level
392
394
# branch to user or kernel vector
393
395
j _SimulateUserKernelVectorException
394
396
.endif
···
443
439
*/
444
440
.align 4
445
441
_SimulateUserKernelVectorException:
446
-
wsr a0, excsave2
447
-
movi a0, 4 # LEVEL1_INTERRUPT cause
448
-
wsr a0, exccause
449
-
rsr a0, ps
442
+
addi a0, a0, (1 << PS_EXCM_BIT)
443
+
wsr a0, ps
450
444
bbsi.l a0, PS_UM_BIT, 1f # branch if user mode
451
445
rsr a0, excsave2 # restore a0
452
446
j _KernelExceptionVector # simulate kernel vector exception
+32
-16
arch/xtensa/kernel/vmlinux.lds.S
+32
-16
arch/xtensa/kernel/vmlinux.lds.S
···
18
18
#include <asm/page.h>
19
19
#include <asm/thread_info.h>
20
20
21
+
#include <asm/vectors.h>
21
22
#include <variant/core.h>
22
23
#include <platform/hardware.h>
23
24
OUTPUT_ARCH(xtensa)
···
31
30
#endif
32
31
33
32
#ifndef KERNELOFFSET
34
-
#define KERNELOFFSET 0xd0001000
33
+
#define KERNELOFFSET 0xd0003000
35
34
#endif
36
35
37
36
/* Note: In the following macros, it would be nice to specify only the
···
186
185
187
186
SECTION_VECTOR (_WindowVectors_text,
188
187
.WindowVectors.text,
189
-
XCHAL_WINDOW_VECTORS_VADDR, 4,
188
+
WINDOW_VECTORS_VADDR, 4,
190
189
.dummy)
191
190
SECTION_VECTOR (_DebugInterruptVector_literal,
192
191
.DebugInterruptVector.literal,
193
-
XCHAL_DEBUG_VECTOR_VADDR - 4,
192
+
DEBUG_VECTOR_VADDR - 4,
194
193
SIZEOF(.WindowVectors.text),
195
194
.WindowVectors.text)
196
195
SECTION_VECTOR (_DebugInterruptVector_text,
197
196
.DebugInterruptVector.text,
198
-
XCHAL_DEBUG_VECTOR_VADDR,
197
+
DEBUG_VECTOR_VADDR,
199
198
4,
200
199
.DebugInterruptVector.literal)
201
200
#undef LAST
···
203
202
#if XCHAL_EXCM_LEVEL >= 2
204
203
SECTION_VECTOR (_Level2InterruptVector_text,
205
204
.Level2InterruptVector.text,
206
-
XCHAL_INTLEVEL2_VECTOR_VADDR,
205
+
INTLEVEL2_VECTOR_VADDR,
207
206
SIZEOF(LAST), LAST)
208
207
# undef LAST
209
208
# define LAST .Level2InterruptVector.text
···
211
210
#if XCHAL_EXCM_LEVEL >= 3
212
211
SECTION_VECTOR (_Level3InterruptVector_text,
213
212
.Level3InterruptVector.text,
214
-
XCHAL_INTLEVEL3_VECTOR_VADDR,
213
+
INTLEVEL3_VECTOR_VADDR,
215
214
SIZEOF(LAST), LAST)
216
215
# undef LAST
217
216
# define LAST .Level3InterruptVector.text
···
219
218
#if XCHAL_EXCM_LEVEL >= 4
220
219
SECTION_VECTOR (_Level4InterruptVector_text,
221
220
.Level4InterruptVector.text,
222
-
XCHAL_INTLEVEL4_VECTOR_VADDR,
221
+
INTLEVEL4_VECTOR_VADDR,
223
222
SIZEOF(LAST), LAST)
224
223
# undef LAST
225
224
# define LAST .Level4InterruptVector.text
···
227
226
#if XCHAL_EXCM_LEVEL >= 5
228
227
SECTION_VECTOR (_Level5InterruptVector_text,
229
228
.Level5InterruptVector.text,
230
-
XCHAL_INTLEVEL5_VECTOR_VADDR,
229
+
INTLEVEL5_VECTOR_VADDR,
231
230
SIZEOF(LAST), LAST)
232
231
# undef LAST
233
232
# define LAST .Level5InterruptVector.text
···
235
234
#if XCHAL_EXCM_LEVEL >= 6
236
235
SECTION_VECTOR (_Level6InterruptVector_text,
237
236
.Level6InterruptVector.text,
238
-
XCHAL_INTLEVEL6_VECTOR_VADDR,
237
+
INTLEVEL6_VECTOR_VADDR,
239
238
SIZEOF(LAST), LAST)
240
239
# undef LAST
241
240
# define LAST .Level6InterruptVector.text
242
241
#endif
243
242
SECTION_VECTOR (_KernelExceptionVector_literal,
244
243
.KernelExceptionVector.literal,
245
-
XCHAL_KERNEL_VECTOR_VADDR - 4,
244
+
KERNEL_VECTOR_VADDR - 4,
246
245
SIZEOF(LAST), LAST)
247
246
#undef LAST
248
247
SECTION_VECTOR (_KernelExceptionVector_text,
249
248
.KernelExceptionVector.text,
250
-
XCHAL_KERNEL_VECTOR_VADDR,
249
+
KERNEL_VECTOR_VADDR,
251
250
4,
252
251
.KernelExceptionVector.literal)
253
252
SECTION_VECTOR (_UserExceptionVector_literal,
254
253
.UserExceptionVector.literal,
255
-
XCHAL_USER_VECTOR_VADDR - 4,
254
+
USER_VECTOR_VADDR - 4,
256
255
SIZEOF(.KernelExceptionVector.text),
257
256
.KernelExceptionVector.text)
258
257
SECTION_VECTOR (_UserExceptionVector_text,
259
258
.UserExceptionVector.text,
260
-
XCHAL_USER_VECTOR_VADDR,
259
+
USER_VECTOR_VADDR,
261
260
4,
262
261
.UserExceptionVector.literal)
263
262
SECTION_VECTOR (_DoubleExceptionVector_literal,
264
263
.DoubleExceptionVector.literal,
265
-
XCHAL_DOUBLEEXC_VECTOR_VADDR - 16,
264
+
DOUBLEEXC_VECTOR_VADDR - 16,
266
265
SIZEOF(.UserExceptionVector.text),
267
266
.UserExceptionVector.text)
268
267
SECTION_VECTOR (_DoubleExceptionVector_text,
269
268
.DoubleExceptionVector.text,
270
-
XCHAL_DOUBLEEXC_VECTOR_VADDR,
269
+
DOUBLEEXC_VECTOR_VADDR,
271
270
32,
272
271
.DoubleExceptionVector.literal)
273
272
···
285
284
. = ALIGN(0x10);
286
285
.bootstrap : { *(.bootstrap.literal .bootstrap.text .bootstrap.data) }
287
286
288
-
.ResetVector.text XCHAL_RESET_VECTOR_VADDR :
287
+
.ResetVector.text RESET_VECTOR_VADDR :
289
288
{
290
289
*(.ResetVector.text)
291
290
}
291
+
292
+
293
+
/*
294
+
* This is a remapped copy of the Secondary Reset Vector Code.
295
+
* It keeps gdb in sync with the PC after switching
296
+
* to the temporary mapping used while setting up
297
+
* the V2 MMU mappings for Linux.
298
+
*
299
+
* Only debug information about this section is put in the kernel image.
300
+
*/
301
+
.SecondaryResetVector.remapped_text 0x46000000 (INFO):
302
+
{
303
+
*(.SecondaryResetVector.remapped_text)
304
+
}
305
+
292
306
293
307
.xt.lit : { *(.xt.lit) }
294
308
.xt.prop : { *(.xt.prop) }
+5
arch/xtensa/kernel/xtensa_ksyms.c
+5
arch/xtensa/kernel/xtensa_ksyms.c
+9
-5
arch/xtensa/mm/mmu.c
+9
-5
arch/xtensa/mm/mmu.c
···
24
24
*/
25
25
void __init init_mmu(void)
26
26
{
27
-
/* Writing zeros to the <t>TLBCFG special registers ensure
28
-
* that valid values exist in the register. For existing
29
-
* PGSZID<w> fields, zero selects the first element of the
30
-
* page-size array. For nonexistent PGSZID<w> fields, zero is
31
-
* the best value to write. Also, when changing PGSZID<w>
27
+
#if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY)
28
+
/*
29
+
* Writing zeros to the instruction and data TLBCFG special
30
+
* registers ensure that valid values exist in the register.
31
+
*
32
+
* For existing PGSZID<w> fields, zero selects the first element
33
+
* of the page-size array. For nonexistent PGSZID<w> fields,
34
+
* zero is the best value to write. Also, when changing PGSZID<w>
32
35
* fields, the corresponding TLB must be flushed.
33
36
*/
34
37
set_itlbcfg_register(0);
35
38
set_dtlbcfg_register(0);
39
+
#endif
36
40
flush_tlb_all();
37
41
38
42
/* Set rasid register to a known value. */
+1
-3
arch/xtensa/oprofile/backtrace.c
+1
-3
arch/xtensa/oprofile/backtrace.c
···
132
132
pc = MAKE_PC_FROM_RA(a0, pc);
133
133
134
134
/* Add the PC to the trace. */
135
-
if (kernel_text_address(pc))
136
-
oprofile_add_trace(pc);
137
-
135
+
oprofile_add_trace(pc);
138
136
if (pc == (unsigned long) &common_exception_return) {
139
137
regs = (struct pt_regs *)a1;
140
138
if (user_mode(regs)) {
+5
-7
arch/xtensa/platforms/iss/console.c
+5
-7
arch/xtensa/platforms/iss/console.c
···
56
56
static int rs_open(struct tty_struct *tty, struct file * filp)
57
57
{
58
58
tty->port = &serial_port;
59
-
spin_lock(&timer_lock);
59
+
spin_lock_bh(&timer_lock);
60
60
if (tty->count == 1) {
61
61
setup_timer(&serial_timer, rs_poll,
62
62
(unsigned long)&serial_port);
63
63
mod_timer(&serial_timer, jiffies + SERIAL_TIMER_VALUE);
64
64
}
65
-
spin_unlock(&timer_lock);
65
+
spin_unlock_bh(&timer_lock);
66
66
67
67
return 0;
68
68
}
···
99
99
static void rs_poll(unsigned long priv)
100
100
{
101
101
struct tty_port *port = (struct tty_port *)priv;
102
-
struct timeval tv = { .tv_sec = 0, .tv_usec = 0 };
103
102
int i = 0;
104
103
unsigned char c;
105
104
106
105
spin_lock(&timer_lock);
107
106
108
-
while (__simc(SYS_select_one, 0, XTISS_SELECT_ONE_READ, (int)&tv,0,0)){
109
-
__simc (SYS_read, 0, (unsigned long)&c, 1, 0, 0);
107
+
while (simc_poll(0)) {
108
+
simc_read(0, &c, 1);
110
109
tty_insert_flip_char(port, c, TTY_NORMAL);
111
110
i++;
112
111
}
···
243
244
int len = strlen(s);
244
245
245
246
if (s != 0 && *s != 0)
246
-
__simc (SYS_write, 1, (unsigned long)s,
247
-
count < len ? count : len,0,0);
247
+
simc_write(1, s, count < len ? count : len);
248
248
}
249
249
250
250
static struct tty_driver* iss_console_device(struct console *c, int *index)
+13
-11
arch/xtensa/platforms/iss/include/platform/simcall.h
+13
-11
arch/xtensa/platforms/iss/include/platform/simcall.h
···
59
59
60
60
static int errno;
61
61
62
-
static inline int __simc(int a, int b, int c, int d, int e, int f)
62
+
static inline int __simc(int a, int b, int c, int d)
63
63
{
64
64
int ret;
65
65
register int a1 asm("a2") = a;
66
66
register int b1 asm("a3") = b;
67
67
register int c1 asm("a4") = c;
68
68
register int d1 asm("a5") = d;
69
-
register int e1 asm("a6") = e;
70
-
register int f1 asm("a7") = f;
71
69
__asm__ __volatile__ (
72
70
"simcall\n"
73
71
"mov %0, a2\n"
74
72
"mov %1, a3\n"
75
73
: "=a" (ret), "=a" (errno), "+r"(a1), "+r"(b1)
76
-
: "r"(c1), "r"(d1), "r"(e1), "r"(f1)
74
+
: "r"(c1), "r"(d1)
77
75
: "memory");
78
76
return ret;
79
77
}
80
78
81
79
static inline int simc_open(const char *file, int flags, int mode)
82
80
{
83
-
return __simc(SYS_open, (int) file, flags, mode, 0, 0);
81
+
return __simc(SYS_open, (int) file, flags, mode);
84
82
}
85
83
86
84
static inline int simc_close(int fd)
87
85
{
88
-
return __simc(SYS_close, fd, 0, 0, 0, 0);
86
+
return __simc(SYS_close, fd, 0, 0);
89
87
}
90
88
91
89
static inline int simc_ioctl(int fd, int request, void *arg)
92
90
{
93
-
return __simc(SYS_ioctl, fd, request, (int) arg, 0, 0);
91
+
return __simc(SYS_ioctl, fd, request, (int) arg);
94
92
}
95
93
96
94
static inline int simc_read(int fd, void *buf, size_t count)
97
95
{
98
-
return __simc(SYS_read, fd, (int) buf, count, 0, 0);
96
+
return __simc(SYS_read, fd, (int) buf, count);
99
97
}
100
98
101
99
static inline int simc_write(int fd, const void *buf, size_t count)
102
100
{
103
-
return __simc(SYS_write, fd, (int) buf, count, 0, 0);
101
+
return __simc(SYS_write, fd, (int) buf, count);
104
102
}
105
103
106
104
static inline int simc_poll(int fd)
107
105
{
108
106
struct timeval tv = { .tv_sec = 0, .tv_usec = 0 };
109
107
110
-
return __simc(SYS_select_one, fd, XTISS_SELECT_ONE_READ, (int)&tv,
111
-
0, 0);
108
+
return __simc(SYS_select_one, fd, XTISS_SELECT_ONE_READ, (int)&tv);
109
+
}
110
+
111
+
static inline int simc_lseek(int fd, uint32_t off, int whence)
112
+
{
113
+
return __simc(SYS_lseek, fd, off, whence);
112
114
}
113
115
114
116
#endif /* _XTENSA_PLATFORM_ISS_SIMCALL_H */
+2
-6
arch/xtensa/platforms/iss/setup.c
+2
-6
arch/xtensa/platforms/iss/setup.c
···
38
38
39
39
}
40
40
41
-
#ifdef CONFIG_PCI
42
-
void platform_pcibios_init(void)
43
-
{
44
-
}
45
-
#endif
46
-
47
41
void platform_halt(void)
48
42
{
49
43
pr_info(" ** Called platform_halt() **\n");
···
58
64
"wsr a2, icountlevel\n\t"
59
65
"movi a2, 0\n\t"
60
66
"wsr a2, icount\n\t"
67
+
#if XCHAL_NUM_IBREAK > 0
61
68
"wsr a2, ibreakenable\n\t"
69
+
#endif
62
70
"wsr a2, lcount\n\t"
63
71
"movi a2, 0x1f\n\t"
64
72
"wsr a2, ps\n\t"
+2
-2
arch/xtensa/platforms/iss/simdisk.c
+2
-2
arch/xtensa/platforms/iss/simdisk.c
···
85
85
while (nbytes > 0) {
86
86
unsigned long io;
87
87
88
-
__simc(SYS_lseek, dev->fd, offset, SEEK_SET, 0, 0);
88
+
simc_lseek(dev->fd, offset, SEEK_SET);
89
89
if (write)
90
90
io = simc_write(dev->fd, buffer, nbytes);
91
91
else
···
176
176
err = -ENODEV;
177
177
goto out;
178
178
}
179
-
dev->size = __simc(SYS_lseek, dev->fd, 0, SEEK_END, 0, 0);
179
+
dev->size = simc_lseek(dev->fd, 0, SEEK_END);
180
180
set_capacity(dev->gd, dev->size >> SECTOR_SHIFT);
181
181
dev->filename = filename;
182
182
pr_info("SIMDISK: %s=%s\n", dev->gd->disk_name, dev->filename);
+2
arch/xtensa/platforms/xt2000/setup.c
+2
arch/xtensa/platforms/xt2000/setup.c