tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"Back from holidays, found these in the cracks: one nouveau revert, one
vmwgfx locking fix and a bunch of exynos fixes"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
Revert "drm/nouveau/fifo/gk104: kick channels when deactivating them"
drm/vmwgfx: Fix execbuf locking issues
drm/exynos/fimc: fix runtime pm support
drm/exynos/mixer: always update INT_EN cache
drm/exynos/mixer: correct vsync configuration sequence
drm/exynos/mixer: fix interrupt clearing
drm/exynos/hdmi: fix edid memory leak
drm/exynos: gsc: fix wrong bitwise operation for swap detection

Linus Torvalds c6797654 7ddab733

+32 -36
-1
drivers/gpu/drm/exynos/exynos_drm_fimc.c
··· 1745 1745 spin_lock_init(&ctx->lock); 1746 1746 platform_set_drvdata(pdev, ctx); 1747 1747 1748 - pm_runtime_set_active(dev); 1749 1748 pm_runtime_enable(dev); 1750 1749 1751 1750 ret = exynos_drm_ippdrv_register(ippdrv);
+2 -4
drivers/gpu/drm/exynos/exynos_drm_gsc.c
··· 593 593 594 594 gsc_write(cfg, GSC_IN_CON); 595 595 596 - ctx->rotation = cfg & 597 - (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0; 596 + ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0; 598 597 *swap = ctx->rotation; 599 598 600 599 return 0; ··· 856 857 857 858 gsc_write(cfg, GSC_IN_CON); 858 859 859 - ctx->rotation = cfg & 860 - (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0; 860 + ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0; 861 861 *swap = ctx->rotation; 862 862 863 863 return 0;
+6 -1
drivers/gpu/drm/exynos/exynos_hdmi.c
··· 1064 1064 { 1065 1065 struct hdmi_context *hdata = ctx_from_connector(connector); 1066 1066 struct edid *edid; 1067 + int ret; 1067 1068 1068 1069 if (!hdata->ddc_adpt) 1069 1070 return -ENODEV; ··· 1080 1079 1081 1080 drm_mode_connector_update_edid_property(connector, edid); 1082 1081 1083 - return drm_add_edid_modes(connector, edid); 1082 + ret = drm_add_edid_modes(connector, edid); 1083 + 1084 + kfree(edid); 1085 + 1086 + return ret; 1084 1087 } 1085 1088 1086 1089 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
+14 -7
drivers/gpu/drm/exynos/exynos_mixer.c
··· 718 718 719 719 /* handling VSYNC */ 720 720 if (val & MXR_INT_STATUS_VSYNC) { 721 + /* vsync interrupt use different bit for read and clear */ 722 + val |= MXR_INT_CLEAR_VSYNC; 723 + val &= ~MXR_INT_STATUS_VSYNC; 724 + 721 725 /* interlace scan need to check shadow register */ 722 726 if (ctx->interlace) { 723 727 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0)); ··· 747 743 748 744 out: 749 745 /* clear interrupts */ 750 - if (~val & MXR_INT_EN_VSYNC) { 751 - /* vsync interrupt use different bit for read and clear */ 752 - val &= ~MXR_INT_EN_VSYNC; 753 - val |= MXR_INT_CLEAR_VSYNC; 754 - } 755 746 mixer_reg_write(res, MXR_INT_STATUS, val); 756 747 757 748 spin_unlock(&res->reg_slock); ··· 906 907 } 907 908 908 909 /* enable vsync interrupt */ 909 - mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC, 910 - MXR_INT_EN_VSYNC); 910 + mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); 911 + mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC); 911 912 912 913 return 0; 913 914 } ··· 917 918 struct mixer_context *mixer_ctx = crtc->ctx; 918 919 struct mixer_resources *res = &mixer_ctx->mixer_res; 919 920 921 + if (!mixer_ctx->powered) { 922 + mixer_ctx->int_en &= MXR_INT_EN_VSYNC; 923 + return; 924 + } 925 + 920 926 /* disable vsync interrupt */ 927 + mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); 921 928 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC); 922 929 } 923 930 ··· 1052 1047 1053 1048 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); 1054 1049 1050 + if (ctx->int_en & MXR_INT_EN_VSYNC) 1051 + mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); 1055 1052 mixer_reg_write(res, MXR_INT_EN, ctx->int_en); 1056 1053 mixer_win_reset(ctx); 1057 1054 }
+8 -21
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
··· 166 166 } 167 167 168 168 static int 169 - gk104_fifo_chan_kick(struct gk104_fifo_chan *chan) 170 - { 171 - struct nvkm_object *obj = (void *)chan; 172 - struct gk104_fifo_priv *priv = (void *)obj->engine; 173 - 174 - nv_wr32(priv, 0x002634, chan->base.chid); 175 - if (!nv_wait(priv, 0x002634, 0x100000, 0x000000)) { 176 - nv_error(priv, "channel %d [%s] kick timeout\n", 177 - chan->base.chid, nvkm_client_name(chan)); 178 - return -EBUSY; 179 - } 180 - 181 - return 0; 182 - } 183 - 184 - static int 185 169 gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, 186 170 struct nvkm_object *object) 187 171 { 188 172 struct nvkm_bar *bar = nvkm_bar(parent); 173 + struct gk104_fifo_priv *priv = (void *)parent->engine; 189 174 struct gk104_fifo_base *base = (void *)parent->parent; 190 175 struct gk104_fifo_chan *chan = (void *)parent; 191 176 u32 addr; 192 - int ret; 193 177 194 178 switch (nv_engidx(object->engine)) { 195 179 case NVDEV_ENGINE_SW : return 0; ··· 188 204 return -EINVAL; 189 205 } 190 206 191 - ret = gk104_fifo_chan_kick(chan); 192 - if (ret && suspend) 193 - return ret; 207 + nv_wr32(priv, 0x002634, chan->base.chid); 208 + if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { 209 + nv_error(priv, "channel %d [%s] kick timeout\n", 210 + chan->base.chid, nvkm_client_name(chan)); 211 + if (suspend) 212 + return -EBUSY; 213 + } 194 214 195 215 if (addr) { 196 216 nv_wo32(base, addr + 0x00, 0x00000000); ··· 319 331 gk104_fifo_runlist_update(priv, chan->engine); 320 332 } 321 333 322 - gk104_fifo_chan_kick(chan); 323 334 nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); 324 335 return nvkm_fifo_channel_fini(&chan->base, suspend); 325 336 }
+2 -2
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
··· 2492 2492 ret = ttm_eu_reserve_buffers(&ticket, &sw_context->validate_nodes, 2493 2493 true, NULL); 2494 2494 if (unlikely(ret != 0)) 2495 - goto out_err; 2495 + goto out_err_nores; 2496 2496 2497 2497 ret = vmw_validate_buffers(dev_priv, sw_context); 2498 2498 if (unlikely(ret != 0)) ··· 2536 2536 vmw_resource_relocations_free(&sw_context->res_relocations); 2537 2537 2538 2538 vmw_fifo_commit(dev_priv, command_size); 2539 + mutex_unlock(&dev_priv->binding_mutex); 2539 2540 2540 2541 vmw_query_bo_switch_commit(dev_priv, sw_context); 2541 2542 ret = vmw_execbuf_fence_commands(file_priv, dev_priv, ··· 2552 2551 DRM_ERROR("Fence submission error. Syncing.\n"); 2553 2552 2554 2553 vmw_resource_list_unreserve(&sw_context->resource_list, false); 2555 - mutex_unlock(&dev_priv->binding_mutex); 2556 2554 2557 2555 ttm_eu_fence_buffer_objects(&ticket, &sw_context->validate_nodes, 2558 2556 (void *) fence);