Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

+58 -62

drivers/gpu/drm/amd/amdgpu/amdgpu.h

··· 389 389 * Fences. 390 390 */ 391 391 struct amdgpu_fence_driver { 392 - struct amdgpu_ring *ring; 393 392 uint64_t gpu_addr; 394 393 volatile uint32_t *cpu_addr; 395 394 /* sync_seq is protected by ring emission lock */ ··· 397 398 bool initialized; 398 399 struct amdgpu_irq_src *irq_src; 399 400 unsigned irq_type; 400 - struct delayed_work lockup_work; 401 + struct timer_list fallback_timer; 401 402 wait_queue_head_t fence_queue; 402 403 }; 403 404 ··· 916 917 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 917 918 918 919 struct amdgpu_vm_pt { 919 - struct amdgpu_bo *bo; 920 - uint64_t addr; 920 + struct amdgpu_bo *bo; 921 + uint64_t addr; 921 922 }; 922 923 923 924 struct amdgpu_vm_id { ··· 925 926 uint64_t pd_gpu_addr; 926 927 /* last flushed PD/PT update */ 927 928 struct fence *flushed_updates; 928 - /* last use of vmid */ 929 - struct fence *last_id_use; 930 929 }; 931 930 932 931 struct amdgpu_vm { ··· 954 957 955 958 /* for id and flush management per ring */ 956 959 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 960 + /* for interval tree */ 961 + spinlock_t it_lock; 957 962 }; 958 963 959 964 struct amdgpu_vm_manager { 960 - struct fence *active[AMDGPU_NUM_VM]; 961 - uint32_t max_pfn; 965 + struct { 966 + struct fence *active; 967 + atomic_long_t owner; 968 + } ids[AMDGPU_NUM_VM]; 969 + 970 + uint32_t max_pfn; 962 971 /* number of VMIDs */ 963 - unsigned nvm; 972 + unsigned nvm; 964 973 /* vram base address for page table entry */ 965 - u64 vram_base_offset; 974 + u64 vram_base_offset; 966 975 /* is vm enabled? */ 967 - bool enabled; 968 - /* for hw to save the PD addr on suspend/resume */ 969 - uint32_t saved_table_addr[AMDGPU_NUM_VM]; 976 + bool enabled; 970 977 /* vm pte handling */ 971 978 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 972 979 struct amdgpu_ring *vm_pte_funcs_ring; 973 980 }; 981 + 982 + void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 983 + int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 984 + void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 985 + struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, 986 + struct amdgpu_vm *vm, 987 + struct list_head *head); 988 + int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 989 + struct amdgpu_sync *sync); 990 + void amdgpu_vm_flush(struct amdgpu_ring *ring, 991 + struct amdgpu_vm *vm, 992 + struct fence *updates); 993 + void amdgpu_vm_fence(struct amdgpu_device *adev, 994 + struct amdgpu_vm *vm, 995 + struct fence *fence); 996 + uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); 997 + int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 998 + struct amdgpu_vm *vm); 999 + int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 1000 + struct amdgpu_vm *vm); 1001 + int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1002 + struct amdgpu_sync *sync); 1003 + int amdgpu_vm_bo_update(struct amdgpu_device *adev, 1004 + struct amdgpu_bo_va *bo_va, 1005 + struct ttm_mem_reg *mem); 1006 + void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 1007 + struct amdgpu_bo *bo); 1008 + struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 1009 + struct amdgpu_bo *bo); 1010 + struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 1011 + struct amdgpu_vm *vm, 1012 + struct amdgpu_bo *bo); 1013 + int amdgpu_vm_bo_map(struct amdgpu_device *adev, 1014 + struct amdgpu_bo_va *bo_va, 1015 + uint64_t addr, uint64_t offset, 1016 + uint64_t size, uint32_t flags); 1017 + int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 1018 + struct amdgpu_bo_va *bo_va, 1019 + uint64_t addr); 1020 + void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 1021 + struct amdgpu_bo_va *bo_va); 1022 + int amdgpu_vm_free_job(struct amdgpu_job *job); 974 1023 975 1024 /* 976 1025 * context related structures ··· 1254 1211 /* relocations */ 1255 1212 struct amdgpu_bo_list_entry *vm_bos; 1256 1213 struct list_head validated; 1214 + struct fence *fence; 1257 1215 1258 1216 struct amdgpu_ib *ibs; 1259 1217 uint32_t num_ibs; ··· 1270 1226 struct amdgpu_device *adev; 1271 1227 struct amdgpu_ib *ibs; 1272 1228 uint32_t num_ibs; 1273 - struct mutex job_lock; 1229 + void *owner; 1274 1230 struct amdgpu_user_fence uf; 1275 1231 int (*free_job)(struct amdgpu_job *job); 1276 1232 }; ··· 2301 2257 bool amdgpu_card_posted(struct amdgpu_device *adev); 2302 2258 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2303 2259 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); 2304 - struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev, 2305 - struct drm_file *filp, 2306 - struct amdgpu_ctx *ctx, 2307 - struct amdgpu_ib *ibs, 2308 - uint32_t num_ibs); 2309 2260 2310 2261 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2311 2262 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, ··· 2357 2318 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2358 2319 unsigned long arg); 2359 2320 2360 - /* 2361 - * vm 2362 - */ 2363 - int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 2364 - void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 2365 - struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, 2366 - struct amdgpu_vm *vm, 2367 - struct list_head *head); 2368 - int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 2369 - struct amdgpu_sync *sync); 2370 - void amdgpu_vm_flush(struct amdgpu_ring *ring, 2371 - struct amdgpu_vm *vm, 2372 - struct fence *updates); 2373 - void amdgpu_vm_fence(struct amdgpu_device *adev, 2374 - struct amdgpu_vm *vm, 2375 - struct amdgpu_fence *fence); 2376 - uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); 2377 - int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 2378 - struct amdgpu_vm *vm); 2379 - int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 2380 - struct amdgpu_vm *vm); 2381 - int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, 2382 - struct amdgpu_vm *vm, struct amdgpu_sync *sync); 2383 - int amdgpu_vm_bo_update(struct amdgpu_device *adev, 2384 - struct amdgpu_bo_va *bo_va, 2385 - struct ttm_mem_reg *mem); 2386 - void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 2387 - struct amdgpu_bo *bo); 2388 - struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 2389 - struct amdgpu_bo *bo); 2390 - struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 2391 - struct amdgpu_vm *vm, 2392 - struct amdgpu_bo *bo); 2393 - int amdgpu_vm_bo_map(struct amdgpu_device *adev, 2394 - struct amdgpu_bo_va *bo_va, 2395 - uint64_t addr, uint64_t offset, 2396 - uint64_t size, uint32_t flags); 2397 - int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 2398 - struct amdgpu_bo_va *bo_va, 2399 - uint64_t addr); 2400 - void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 2401 - struct amdgpu_bo_va *bo_va); 2402 - int amdgpu_vm_free_job(struct amdgpu_job *job); 2403 2321 /* 2404 2322 * functions used by amdgpu_encoder.c 2405 2323 */

+72 -105

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

··· 127 127 return 0; 128 128 } 129 129 130 - struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev, 131 - struct drm_file *filp, 132 - struct amdgpu_ctx *ctx, 133 - struct amdgpu_ib *ibs, 134 - uint32_t num_ibs) 135 - { 136 - struct amdgpu_cs_parser *parser; 137 - int i; 138 - 139 - parser = kzalloc(sizeof(struct amdgpu_cs_parser), GFP_KERNEL); 140 - if (!parser) 141 - return NULL; 142 - 143 - parser->adev = adev; 144 - parser->filp = filp; 145 - parser->ctx = ctx; 146 - parser->ibs = ibs; 147 - parser->num_ibs = num_ibs; 148 - for (i = 0; i < num_ibs; i++) 149 - ibs[i].ctx = ctx; 150 - 151 - return parser; 152 - } 153 - 154 130 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) 155 131 { 156 132 union drm_amdgpu_cs *cs = data; ··· 439 463 return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages; 440 464 } 441 465 442 - static void amdgpu_cs_parser_fini_early(struct amdgpu_cs_parser *parser, int error, bool backoff) 466 + /** 467 + * cs_parser_fini() - clean parser states 468 + * @parser: parser structure holding parsing context. 469 + * @error: error number 470 + * 471 + * If error is set than unvalidate buffer, otherwise just free memory 472 + * used by parsing context. 473 + **/ 474 + static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) 443 475 { 476 + unsigned i; 477 + 444 478 if (!error) { 445 479 /* Sort the buffer list from the smallest to largest buffer, 446 480 * which affects the order of buffers in the LRU list. ··· 465 479 list_sort(NULL, &parser->validated, cmp_size_smaller_first); 466 480 467 481 ttm_eu_fence_buffer_objects(&parser->ticket, 468 - &parser->validated, 469 - &parser->ibs[parser->num_ibs-1].fence->base); 482 + &parser->validated, 483 + parser->fence); 470 484 } else if (backoff) { 471 485 ttm_eu_backoff_reservation(&parser->ticket, 472 486 &parser->validated); 473 487 } 474 - } 488 + fence_put(parser->fence); 475 489 476 - static void amdgpu_cs_parser_fini_late(struct amdgpu_cs_parser *parser) 477 - { 478 - unsigned i; 479 490 if (parser->ctx) 480 491 amdgpu_ctx_put(parser->ctx); 481 492 if (parser->bo_list) ··· 482 499 for (i = 0; i < parser->nchunks; i++) 483 500 drm_free_large(parser->chunks[i].kdata); 484 501 kfree(parser->chunks); 485 - if (!amdgpu_enable_scheduler) 486 - { 487 - if (parser->ibs) 488 - for (i = 0; i < parser->num_ibs; i++) 489 - amdgpu_ib_free(parser->adev, &parser->ibs[i]); 490 - kfree(parser->ibs); 491 - if (parser->uf.bo) 492 - drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base); 493 - } 494 - 495 - kfree(parser); 496 - } 497 - 498 - /** 499 - * cs_parser_fini() - clean parser states 500 - * @parser: parser structure holding parsing context. 501 - * @error: error number 502 - * 503 - * If error is set than unvalidate buffer, otherwise just free memory 504 - * used by parsing context. 505 - **/ 506 - static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff) 507 - { 508 - amdgpu_cs_parser_fini_early(parser, error, backoff); 509 - amdgpu_cs_parser_fini_late(parser); 502 + if (parser->ibs) 503 + for (i = 0; i < parser->num_ibs; i++) 504 + amdgpu_ib_free(parser->adev, &parser->ibs[i]); 505 + kfree(parser->ibs); 506 + if (parser->uf.bo) 507 + drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base); 510 508 } 511 509 512 510 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, ··· 574 610 } 575 611 576 612 r = amdgpu_bo_vm_update_pte(parser, vm); 577 - if (r) { 578 - goto out; 579 - } 580 - amdgpu_cs_sync_rings(parser); 581 - if (!amdgpu_enable_scheduler) 582 - r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs, 583 - parser->filp); 613 + if (!r) 614 + amdgpu_cs_sync_rings(parser); 584 615 585 - out: 586 616 return r; 587 617 } 588 618 ··· 786 828 union drm_amdgpu_cs *cs = data; 787 829 struct amdgpu_fpriv *fpriv = filp->driver_priv; 788 830 struct amdgpu_vm *vm = &fpriv->vm; 789 - struct amdgpu_cs_parser *parser; 831 + struct amdgpu_cs_parser parser = {}; 790 832 bool reserved_buffers = false; 791 833 int i, r; 792 834 793 835 if (!adev->accel_working) 794 836 return -EBUSY; 795 837 796 - parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0); 797 - if (!parser) 798 - return -ENOMEM; 799 - r = amdgpu_cs_parser_init(parser, data); 838 + parser.adev = adev; 839 + parser.filp = filp; 840 + 841 + r = amdgpu_cs_parser_init(&parser, data); 800 842 if (r) { 801 843 DRM_ERROR("Failed to initialize parser !\n"); 802 - amdgpu_cs_parser_fini(parser, r, false); 844 + amdgpu_cs_parser_fini(&parser, r, false); 803 845 r = amdgpu_cs_handle_lockup(adev, r); 804 846 return r; 805 847 } 806 848 mutex_lock(&vm->mutex); 807 - r = amdgpu_cs_parser_relocs(parser); 849 + r = amdgpu_cs_parser_relocs(&parser); 808 850 if (r == -ENOMEM) 809 851 DRM_ERROR("Not enough memory for command submission!\n"); 810 852 else if (r && r != -ERESTARTSYS) 811 853 DRM_ERROR("Failed to process the buffer list %d!\n", r); 812 854 else if (!r) { 813 855 reserved_buffers = true; 814 - r = amdgpu_cs_ib_fill(adev, parser); 856 + r = amdgpu_cs_ib_fill(adev, &parser); 815 857 } 816 858 817 859 if (!r) { 818 - r = amdgpu_cs_dependencies(adev, parser); 860 + r = amdgpu_cs_dependencies(adev, &parser); 819 861 if (r) 820 862 DRM_ERROR("Failed in the dependencies handling %d!\n", r); 821 863 } ··· 823 865 if (r) 824 866 goto out; 825 867 826 - for (i = 0; i < parser->num_ibs; i++) 827 - trace_amdgpu_cs(parser, i); 868 + for (i = 0; i < parser.num_ibs; i++) 869 + trace_amdgpu_cs(&parser, i); 828 870 829 - r = amdgpu_cs_ib_vm_chunk(adev, parser); 871 + r = amdgpu_cs_ib_vm_chunk(adev, &parser); 830 872 if (r) 831 873 goto out; 832 874 833 - if (amdgpu_enable_scheduler && parser->num_ibs) { 875 + if (amdgpu_enable_scheduler && parser.num_ibs) { 876 + struct amdgpu_ring * ring = parser.ibs->ring; 877 + struct amd_sched_fence *fence; 834 878 struct amdgpu_job *job; 835 - struct amdgpu_ring * ring = parser->ibs->ring; 879 + 836 880 job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL); 837 881 if (!job) { 838 882 r = -ENOMEM; 839 883 goto out; 840 884 } 885 + 841 886 job->base.sched = &ring->sched; 842 - job->base.s_entity = &parser->ctx->rings[ring->idx].entity; 843 - job->adev = parser->adev; 844 - job->ibs = parser->ibs; 845 - job->num_ibs = parser->num_ibs; 846 - job->base.owner = parser->filp; 847 - mutex_init(&job->job_lock); 887 + job->base.s_entity = &parser.ctx->rings[ring->idx].entity; 888 + job->adev = parser.adev; 889 + job->owner = parser.filp; 890 + job->free_job = amdgpu_cs_free_job; 891 + 892 + job->ibs = parser.ibs; 893 + job->num_ibs = parser.num_ibs; 894 + parser.ibs = NULL; 895 + parser.num_ibs = 0; 896 + 848 897 if (job->ibs[job->num_ibs - 1].user) { 849 - memcpy(&job->uf, &parser->uf, 850 - sizeof(struct amdgpu_user_fence)); 898 + job->uf = parser.uf; 851 899 job->ibs[job->num_ibs - 1].user = &job->uf; 900 + parser.uf.bo = NULL; 852 901 } 853 902 854 - job->free_job = amdgpu_cs_free_job; 855 - mutex_lock(&job->job_lock); 856 - r = amd_sched_entity_push_job(&job->base); 857 - if (r) { 858 - mutex_unlock(&job->job_lock); 903 + fence = amd_sched_fence_create(job->base.s_entity, 904 + parser.filp); 905 + if (!fence) { 906 + r = -ENOMEM; 859 907 amdgpu_cs_free_job(job); 860 908 kfree(job); 861 909 goto out; 862 910 } 863 - cs->out.handle = 864 - amdgpu_ctx_add_fence(parser->ctx, ring, 865 - &job->base.s_fence->base); 866 - parser->ibs[parser->num_ibs - 1].sequence = cs->out.handle; 911 + job->base.s_fence = fence; 912 + parser.fence = fence_get(&fence->base); 867 913 868 - list_sort(NULL, &parser->validated, cmp_size_smaller_first); 869 - ttm_eu_fence_buffer_objects(&parser->ticket, 870 - &parser->validated, 871 - &job->base.s_fence->base); 914 + cs->out.handle = amdgpu_ctx_add_fence(parser.ctx, ring, 915 + &fence->base); 916 + job->ibs[job->num_ibs - 1].sequence = cs->out.handle; 872 917 873 - mutex_unlock(&job->job_lock); 874 - amdgpu_cs_parser_fini_late(parser); 875 - mutex_unlock(&vm->mutex); 876 - return 0; 918 + trace_amdgpu_cs_ioctl(job); 919 + amd_sched_entity_push_job(&job->base); 920 + 921 + } else { 922 + struct amdgpu_fence *fence; 923 + 924 + r = amdgpu_ib_schedule(adev, parser.num_ibs, parser.ibs, 925 + parser.filp); 926 + fence = parser.ibs[parser.num_ibs - 1].fence; 927 + parser.fence = fence_get(&fence->base); 928 + cs->out.handle = parser.ibs[parser.num_ibs - 1].sequence; 877 929 } 878 930 879 - cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence; 880 931 out: 881 - amdgpu_cs_parser_fini(parser, r, reserved_buffers); 932 + amdgpu_cs_parser_fini(&parser, r, reserved_buffers); 882 933 mutex_unlock(&vm->mutex); 883 934 r = amdgpu_cs_handle_lockup(adev, r); 884 935 return r;

+55 -48

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

··· 47 47 * that the the relevant GPU caches have been flushed. 48 48 */ 49 49 50 + static struct kmem_cache *amdgpu_fence_slab; 51 + static atomic_t amdgpu_fence_slab_ref = ATOMIC_INIT(0); 52 + 50 53 /** 51 54 * amdgpu_fence_write - write a fence value 52 55 * ··· 88 85 } 89 86 90 87 /** 91 - * amdgpu_fence_schedule_check - schedule lockup check 92 - * 93 - * @ring: pointer to struct amdgpu_ring 94 - * 95 - * Queues a delayed work item to check for lockups. 96 - */ 97 - static void amdgpu_fence_schedule_check(struct amdgpu_ring *ring) 98 - { 99 - /* 100 - * Do not reset the timer here with mod_delayed_work, 101 - * this can livelock in an interaction with TTM delayed destroy. 102 - */ 103 - queue_delayed_work(system_power_efficient_wq, 104 - &ring->fence_drv.lockup_work, 105 - AMDGPU_FENCE_JIFFIES_TIMEOUT); 106 - } 107 - 108 - /** 109 88 * amdgpu_fence_emit - emit a fence on the requested ring 110 89 * 111 90 * @ring: ring the fence is associated with ··· 103 118 struct amdgpu_device *adev = ring->adev; 104 119 105 120 /* we are protected by the ring emission mutex */ 106 - *fence = kmalloc(sizeof(struct amdgpu_fence), GFP_KERNEL); 121 + *fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 107 122 if ((*fence) == NULL) { 108 123 return -ENOMEM; 109 124 } ··· 117 132 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, 118 133 (*fence)->seq, 119 134 AMDGPU_FENCE_FLAG_INT); 120 - trace_amdgpu_fence_emit(ring->adev->ddev, ring->idx, (*fence)->seq); 121 135 return 0; 136 + } 137 + 138 + /** 139 + * amdgpu_fence_schedule_fallback - schedule fallback check 140 + * 141 + * @ring: pointer to struct amdgpu_ring 142 + * 143 + * Start a timer as fallback to our interrupts. 144 + */ 145 + static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring) 146 + { 147 + mod_timer(&ring->fence_drv.fallback_timer, 148 + jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT); 122 149 } 123 150 124 151 /** ··· 199 202 } while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq); 200 203 201 204 if (seq < last_emitted) 202 - amdgpu_fence_schedule_check(ring); 205 + amdgpu_fence_schedule_fallback(ring); 203 206 204 207 return wake; 205 - } 206 - 207 - /** 208 - * amdgpu_fence_check_lockup - check for hardware lockup 209 - * 210 - * @work: delayed work item 211 - * 212 - * Checks for fence activity and if there is none probe 213 - * the hardware if a lockup occured. 214 - */ 215 - static void amdgpu_fence_check_lockup(struct work_struct *work) 216 - { 217 - struct amdgpu_fence_driver *fence_drv; 218 - struct amdgpu_ring *ring; 219 - 220 - fence_drv = container_of(work, struct amdgpu_fence_driver, 221 - lockup_work.work); 222 - ring = fence_drv->ring; 223 - 224 - if (amdgpu_fence_activity(ring)) 225 - wake_up_all(&ring->fence_drv.fence_queue); 226 208 } 227 209 228 210 /** ··· 217 241 { 218 242 if (amdgpu_fence_activity(ring)) 219 243 wake_up_all(&ring->fence_drv.fence_queue); 244 + } 245 + 246 + /** 247 + * amdgpu_fence_fallback - fallback for hardware interrupts 248 + * 249 + * @work: delayed work item 250 + * 251 + * Checks for fence activity. 252 + */ 253 + static void amdgpu_fence_fallback(unsigned long arg) 254 + { 255 + struct amdgpu_ring *ring = (void *)arg; 256 + 257 + amdgpu_fence_process(ring); 220 258 } 221 259 222 260 /** ··· 280 290 if (atomic64_read(&ring->fence_drv.last_seq) >= seq) 281 291 return 0; 282 292 283 - amdgpu_fence_schedule_check(ring); 293 + amdgpu_fence_schedule_fallback(ring); 284 294 wait_event(ring->fence_drv.fence_queue, ( 285 295 (signaled = amdgpu_fence_seq_signaled(ring, seq)))); 286 296 ··· 481 491 atomic64_set(&ring->fence_drv.last_seq, 0); 482 492 ring->fence_drv.initialized = false; 483 493 484 - INIT_DELAYED_WORK(&ring->fence_drv.lockup_work, 485 - amdgpu_fence_check_lockup); 486 - ring->fence_drv.ring = ring; 494 + setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 495 + (unsigned long)ring); 487 496 488 497 init_waitqueue_head(&ring->fence_drv.fence_queue); 489 498 ··· 525 536 */ 526 537 int amdgpu_fence_driver_init(struct amdgpu_device *adev) 527 538 { 539 + if (atomic_inc_return(&amdgpu_fence_slab_ref) == 1) { 540 + amdgpu_fence_slab = kmem_cache_create( 541 + "amdgpu_fence", sizeof(struct amdgpu_fence), 0, 542 + SLAB_HWCACHE_ALIGN, NULL); 543 + if (!amdgpu_fence_slab) 544 + return -ENOMEM; 545 + } 528 546 if (amdgpu_debugfs_fence_init(adev)) 529 547 dev_err(adev->dev, "fence debugfs file creation failed\n"); 530 548 ··· 550 554 { 551 555 int i, r; 552 556 557 + if (atomic_dec_and_test(&amdgpu_fence_slab_ref)) 558 + kmem_cache_destroy(amdgpu_fence_slab); 553 559 mutex_lock(&adev->ring_lock); 554 560 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 555 561 struct amdgpu_ring *ring = adev->rings[i]; 562 + 556 563 if (!ring || !ring->fence_drv.initialized) 557 564 continue; 558 565 r = amdgpu_fence_wait_empty(ring); ··· 567 568 amdgpu_irq_put(adev, ring->fence_drv.irq_src, 568 569 ring->fence_drv.irq_type); 569 570 amd_sched_fini(&ring->sched); 571 + del_timer_sync(&ring->fence_drv.fallback_timer); 570 572 ring->fence_drv.initialized = false; 571 573 } 572 574 mutex_unlock(&adev->ring_lock); ··· 751 751 fence->fence_wake.func = amdgpu_fence_check_signaled; 752 752 __add_wait_queue(&ring->fence_drv.fence_queue, &fence->fence_wake); 753 753 fence_get(f); 754 - amdgpu_fence_schedule_check(ring); 754 + if (!timer_pending(&ring->fence_drv.fallback_timer)) 755 + amdgpu_fence_schedule_fallback(ring); 755 756 FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); 756 757 return true; 758 + } 759 + 760 + static void amdgpu_fence_release(struct fence *f) 761 + { 762 + struct amdgpu_fence *fence = to_amdgpu_fence(f); 763 + kmem_cache_free(amdgpu_fence_slab, fence); 757 764 } 758 765 759 766 const struct fence_ops amdgpu_fence_ops = { ··· 769 762 .enable_signaling = amdgpu_fence_enable_signaling, 770 763 .signaled = amdgpu_fence_is_signaled, 771 764 .wait = fence_default_wait, 772 - .release = NULL, 765 + .release = amdgpu_fence_release, 773 766 }; 774 767 775 768 /*

+21 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

··· 483 483 if (domain == AMDGPU_GEM_DOMAIN_CPU) 484 484 goto error_unreserve; 485 485 } 486 + r = amdgpu_vm_update_page_directory(adev, bo_va->vm); 487 + if (r) 488 + goto error_unreserve; 486 489 487 490 r = amdgpu_vm_clear_freed(adev, bo_va->vm); 488 491 if (r) ··· 515 512 struct amdgpu_fpriv *fpriv = filp->driver_priv; 516 513 struct amdgpu_bo *rbo; 517 514 struct amdgpu_bo_va *bo_va; 515 + struct ttm_validate_buffer tv, tv_pd; 516 + struct ww_acquire_ctx ticket; 517 + struct list_head list, duplicates; 518 518 uint32_t invalid_flags, va_flags = 0; 519 519 int r = 0; 520 520 ··· 555 549 return -ENOENT; 556 550 mutex_lock(&fpriv->vm.mutex); 557 551 rbo = gem_to_amdgpu_bo(gobj); 558 - r = amdgpu_bo_reserve(rbo, false); 552 + INIT_LIST_HEAD(&list); 553 + INIT_LIST_HEAD(&duplicates); 554 + tv.bo = &rbo->tbo; 555 + tv.shared = true; 556 + list_add(&tv.head, &list); 557 + 558 + if (args->operation == AMDGPU_VA_OP_MAP) { 559 + tv_pd.bo = &fpriv->vm.page_directory->tbo; 560 + tv_pd.shared = true; 561 + list_add(&tv_pd.head, &list); 562 + } 563 + r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 559 564 if (r) { 560 565 mutex_unlock(&fpriv->vm.mutex); 561 566 drm_gem_object_unreference_unlocked(gobj); ··· 575 558 576 559 bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); 577 560 if (!bo_va) { 578 - amdgpu_bo_unreserve(rbo); 561 + ttm_eu_backoff_reservation(&ticket, &list); 562 + drm_gem_object_unreference_unlocked(gobj); 579 563 mutex_unlock(&fpriv->vm.mutex); 580 564 return -ENOENT; 581 565 } ··· 599 581 default: 600 582 break; 601 583 } 602 - 584 + ttm_eu_backoff_reservation(&ticket, &list); 603 585 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)) 604 586 amdgpu_gem_va_update_vm(adev, bo_va, args->operation); 605 587 mutex_unlock(&fpriv->vm.mutex);

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

··· 62 62 int r; 63 63 64 64 if (size) { 65 - r = amdgpu_sa_bo_new(adev, &adev->ring_tmp_bo, 65 + r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 66 66 &ib->sa_bo, size, 256); 67 67 if (r) { 68 68 dev_err(adev->dev, "failed to get a new IB (%d)\n", r); ··· 216 216 } 217 217 218 218 if (ib->vm) 219 - amdgpu_vm_fence(adev, ib->vm, ib->fence); 219 + amdgpu_vm_fence(adev, ib->vm, &ib->fence->base); 220 220 221 221 amdgpu_ring_unlock_commit(ring); 222 222 return 0;

+3 -4

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

··· 189 189 struct amdgpu_sa_manager *sa_manager); 190 190 int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev, 191 191 struct amdgpu_sa_manager *sa_manager); 192 - int amdgpu_sa_bo_new(struct amdgpu_device *adev, 193 - struct amdgpu_sa_manager *sa_manager, 194 - struct amdgpu_sa_bo **sa_bo, 195 - unsigned size, unsigned align); 192 + int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, 193 + struct amdgpu_sa_bo **sa_bo, 194 + unsigned size, unsigned align); 196 195 void amdgpu_sa_bo_free(struct amdgpu_device *adev, 197 196 struct amdgpu_sa_bo **sa_bo, 198 197 struct fence *fence);

+1 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c

··· 311 311 return false; 312 312 } 313 313 314 - int amdgpu_sa_bo_new(struct amdgpu_device *adev, 315 - struct amdgpu_sa_manager *sa_manager, 314 + int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, 316 315 struct amdgpu_sa_bo **sa_bo, 317 316 unsigned size, unsigned align) 318 317 {

+12 -18

drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c

··· 26 26 #include <linux/sched.h> 27 27 #include <drm/drmP.h> 28 28 #include "amdgpu.h" 29 + #include "amdgpu_trace.h" 29 30 30 31 static struct fence *amdgpu_sched_dependency(struct amd_sched_job *sched_job) 31 32 { ··· 45 44 return NULL; 46 45 } 47 46 job = to_amdgpu_job(sched_job); 48 - mutex_lock(&job->job_lock); 49 - r = amdgpu_ib_schedule(job->adev, 50 - job->num_ibs, 51 - job->ibs, 52 - job->base.owner); 47 + trace_amdgpu_sched_run_job(job); 48 + r = amdgpu_ib_schedule(job->adev, job->num_ibs, job->ibs, job->owner); 53 49 if (r) { 54 50 DRM_ERROR("Error scheduling IBs (%d)\n", r); 55 51 goto err; ··· 59 61 if (job->free_job) 60 62 job->free_job(job); 61 63 62 - mutex_unlock(&job->job_lock); 63 - fence_put(&job->base.s_fence->base); 64 64 kfree(job); 65 65 return fence ? &fence->base : NULL; 66 66 } ··· 84 88 return -ENOMEM; 85 89 job->base.sched = &ring->sched; 86 90 job->base.s_entity = &adev->kernel_ctx.rings[ring->idx].entity; 91 + job->base.s_fence = amd_sched_fence_create(job->base.s_entity, owner); 92 + if (!job->base.s_fence) { 93 + kfree(job); 94 + return -ENOMEM; 95 + } 96 + *f = fence_get(&job->base.s_fence->base); 97 + 87 98 job->adev = adev; 88 99 job->ibs = ibs; 89 100 job->num_ibs = num_ibs; 90 - job->base.owner = owner; 91 - mutex_init(&job->job_lock); 101 + job->owner = owner; 92 102 job->free_job = free_job; 93 - mutex_lock(&job->job_lock); 94 - r = amd_sched_entity_push_job(&job->base); 95 - if (r) { 96 - mutex_unlock(&job->job_lock); 97 - kfree(job); 98 - return r; 99 - } 100 - *f = fence_get(&job->base.s_fence->base); 101 - mutex_unlock(&job->job_lock); 103 + amd_sched_entity_push_job(&job->base); 102 104 } else { 103 105 r = amdgpu_ib_schedule(adev, num_ibs, ibs, owner); 104 106 if (r)

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c

··· 40 40 if (*semaphore == NULL) { 41 41 return -ENOMEM; 42 42 } 43 - r = amdgpu_sa_bo_new(adev, &adev->ring_tmp_bo, 43 + r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, 44 44 &(*semaphore)->sa_bo, 8, 8); 45 45 if (r) { 46 46 kfree(*semaphore);

+8 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c

··· 302 302 return -EINVAL; 303 303 } 304 304 305 - if (amdgpu_enable_scheduler || !amdgpu_enable_semaphores || 306 - (count >= AMDGPU_NUM_SYNCS)) { 305 + if (amdgpu_enable_scheduler || !amdgpu_enable_semaphores) { 306 + r = fence_wait(&fence->base, true); 307 + if (r) 308 + return r; 309 + continue; 310 + } 311 + 312 + if (count >= AMDGPU_NUM_SYNCS) { 307 313 /* not enough room, wait manually */ 308 314 r = fence_wait(&fence->base, false); 309 315 if (r)

+51 -43

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

··· 48 48 __entry->fences) 49 49 ); 50 50 51 + TRACE_EVENT(amdgpu_cs_ioctl, 52 + TP_PROTO(struct amdgpu_job *job), 53 + TP_ARGS(job), 54 + TP_STRUCT__entry( 55 + __field(struct amdgpu_device *, adev) 56 + __field(struct amd_sched_job *, sched_job) 57 + __field(struct amdgpu_ib *, ib) 58 + __field(struct fence *, fence) 59 + __field(char *, ring_name) 60 + __field(u32, num_ibs) 61 + ), 62 + 63 + TP_fast_assign( 64 + __entry->adev = job->adev; 65 + __entry->sched_job = &job->base; 66 + __entry->ib = job->ibs; 67 + __entry->fence = &job->base.s_fence->base; 68 + __entry->ring_name = job->ibs[0].ring->name; 69 + __entry->num_ibs = job->num_ibs; 70 + ), 71 + TP_printk("adev=%p, sched_job=%p, first ib=%p, sched fence=%p, ring name:%s, num_ibs:%u", 72 + __entry->adev, __entry->sched_job, __entry->ib, 73 + __entry->fence, __entry->ring_name, __entry->num_ibs) 74 + ); 75 + 76 + TRACE_EVENT(amdgpu_sched_run_job, 77 + TP_PROTO(struct amdgpu_job *job), 78 + TP_ARGS(job), 79 + TP_STRUCT__entry( 80 + __field(struct amdgpu_device *, adev) 81 + __field(struct amd_sched_job *, sched_job) 82 + __field(struct amdgpu_ib *, ib) 83 + __field(struct fence *, fence) 84 + __field(char *, ring_name) 85 + __field(u32, num_ibs) 86 + ), 87 + 88 + TP_fast_assign( 89 + __entry->adev = job->adev; 90 + __entry->sched_job = &job->base; 91 + __entry->ib = job->ibs; 92 + __entry->fence = &job->base.s_fence->base; 93 + __entry->ring_name = job->ibs[0].ring->name; 94 + __entry->num_ibs = job->num_ibs; 95 + ), 96 + TP_printk("adev=%p, sched_job=%p, first ib=%p, sched fence=%p, ring name:%s, num_ibs:%u", 97 + __entry->adev, __entry->sched_job, __entry->ib, 98 + __entry->fence, __entry->ring_name, __entry->num_ibs) 99 + ); 100 + 101 + 51 102 TRACE_EVENT(amdgpu_vm_grab_id, 52 103 TP_PROTO(unsigned vmid, int ring), 53 104 TP_ARGS(vmid, ring), ··· 245 194 __entry->bo = bo; 246 195 ), 247 196 TP_printk("list=%p, bo=%p", __entry->list, __entry->bo) 248 - ); 249 - 250 - DECLARE_EVENT_CLASS(amdgpu_fence_request, 251 - 252 - TP_PROTO(struct drm_device *dev, int ring, u32 seqno), 253 - 254 - TP_ARGS(dev, ring, seqno), 255 - 256 - TP_STRUCT__entry( 257 - __field(u32, dev) 258 - __field(int, ring) 259 - __field(u32, seqno) 260 - ), 261 - 262 - TP_fast_assign( 263 - __entry->dev = dev->primary->index; 264 - __entry->ring = ring; 265 - __entry->seqno = seqno; 266 - ), 267 - 268 - TP_printk("dev=%u, ring=%d, seqno=%u", 269 - __entry->dev, __entry->ring, __entry->seqno) 270 - ); 271 - 272 - DEFINE_EVENT(amdgpu_fence_request, amdgpu_fence_emit, 273 - 274 - TP_PROTO(struct drm_device *dev, int ring, u32 seqno), 275 - 276 - TP_ARGS(dev, ring, seqno) 277 - ); 278 - 279 - DEFINE_EVENT(amdgpu_fence_request, amdgpu_fence_wait_begin, 280 - 281 - TP_PROTO(struct drm_device *dev, int ring, u32 seqno), 282 - 283 - TP_ARGS(dev, ring, seqno) 284 - ); 285 - 286 - DEFINE_EVENT(amdgpu_fence_request, amdgpu_fence_wait_end, 287 - 288 - TP_PROTO(struct drm_device *dev, int ring, u32 seqno), 289 - 290 - TP_ARGS(dev, ring, seqno) 291 197 ); 292 198 293 199 DECLARE_EVENT_CLASS(amdgpu_semaphore_request,

+3 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

··· 1073 1073 ret = drm_mm_dump_table(m, mm); 1074 1074 spin_unlock(&glob->lru_lock); 1075 1075 if (ttm_pl == TTM_PL_VRAM) 1076 - seq_printf(m, "man size:%llu pages, ram usage:%luMB, vis usage:%luMB\n", 1076 + seq_printf(m, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n", 1077 1077 adev->mman.bdev.man[ttm_pl].size, 1078 - atomic64_read(&adev->vram_usage) >> 20, 1079 - atomic64_read(&adev->vram_vis_usage) >> 20); 1078 + (u64)atomic64_read(&adev->vram_usage) >> 20, 1079 + (u64)atomic64_read(&adev->vram_vis_usage) >> 20); 1080 1080 return ret; 1081 1081 } 1082 1082

+77 -61

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

··· 143 143 unsigned i; 144 144 145 145 /* check if the id is still valid */ 146 - if (vm_id->id && vm_id->last_id_use && 147 - vm_id->last_id_use == adev->vm_manager.active[vm_id->id]) { 148 - trace_amdgpu_vm_grab_id(vm_id->id, ring->idx); 149 - return 0; 146 + if (vm_id->id) { 147 + unsigned id = vm_id->id; 148 + long owner; 149 + 150 + owner = atomic_long_read(&adev->vm_manager.ids[id].owner); 151 + if (owner == (long)vm) { 152 + trace_amdgpu_vm_grab_id(vm_id->id, ring->idx); 153 + return 0; 154 + } 150 155 } 151 156 152 157 /* we definately need to flush */ ··· 159 154 160 155 /* skip over VMID 0, since it is the system VM */ 161 156 for (i = 1; i < adev->vm_manager.nvm; ++i) { 162 - struct fence *fence = adev->vm_manager.active[i]; 157 + struct fence *fence = adev->vm_manager.ids[i].active; 163 158 struct amdgpu_ring *fring; 164 159 165 160 if (fence == NULL) { ··· 181 176 if (choices[i]) { 182 177 struct fence *fence; 183 178 184 - fence = adev->vm_manager.active[choices[i]]; 179 + fence = adev->vm_manager.ids[choices[i]].active; 185 180 vm_id->id = choices[i]; 186 181 187 182 trace_amdgpu_vm_grab_id(choices[i], ring->idx); ··· 212 207 uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory); 213 208 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; 214 209 struct fence *flushed_updates = vm_id->flushed_updates; 215 - bool is_earlier = false; 210 + bool is_later; 216 211 217 - if (flushed_updates && updates) { 218 - BUG_ON(flushed_updates->context != updates->context); 219 - is_earlier = (updates->seqno - flushed_updates->seqno <= 220 - INT_MAX) ? true : false; 221 - } 212 + if (!flushed_updates) 213 + is_later = true; 214 + else if (!updates) 215 + is_later = false; 216 + else 217 + is_later = fence_is_later(updates, flushed_updates); 222 218 223 - if (pd_addr != vm_id->pd_gpu_addr || !flushed_updates || 224 - is_earlier) { 225 - 219 + if (pd_addr != vm_id->pd_gpu_addr || is_later) { 226 220 trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id); 227 - if (is_earlier) { 221 + if (is_later) { 228 222 vm_id->flushed_updates = fence_get(updates); 229 223 fence_put(flushed_updates); 230 224 } 231 - if (!flushed_updates) 232 - vm_id->flushed_updates = fence_get(updates); 233 225 vm_id->pd_gpu_addr = pd_addr; 234 226 amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr); 235 227 } ··· 246 244 */ 247 245 void amdgpu_vm_fence(struct amdgpu_device *adev, 248 246 struct amdgpu_vm *vm, 249 - struct amdgpu_fence *fence) 247 + struct fence *fence) 250 248 { 251 - unsigned ridx = fence->ring->idx; 252 - unsigned vm_id = vm->ids[ridx].id; 249 + struct amdgpu_ring *ring = amdgpu_ring_from_fence(fence); 250 + unsigned vm_id = vm->ids[ring->idx].id; 253 251 254 - fence_put(adev->vm_manager.active[vm_id]); 255 - adev->vm_manager.active[vm_id] = fence_get(&fence->base); 256 - 257 - fence_put(vm->ids[ridx].last_id_use); 258 - vm->ids[ridx].last_id_use = fence_get(&fence->base); 252 + fence_put(adev->vm_manager.ids[vm_id].active); 253 + adev->vm_manager.ids[vm_id].active = fence_get(fence); 254 + atomic_long_set(&adev->vm_manager.ids[vm_id].owner, (long)vm); 259 255 } 260 256 261 257 /** ··· 332 332 * 333 333 * @adev: amdgpu_device pointer 334 334 * @bo: bo to clear 335 + * 336 + * need to reserve bo first before calling it. 335 337 */ 336 338 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, 337 339 struct amdgpu_bo *bo) ··· 345 343 uint64_t addr; 346 344 int r; 347 345 348 - r = amdgpu_bo_reserve(bo, false); 349 - if (r) 350 - return r; 351 - 352 346 r = reservation_object_reserve_shared(bo->tbo.resv); 353 347 if (r) 354 348 return r; 355 349 356 350 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 357 351 if (r) 358 - goto error_unreserve; 352 + goto error; 359 353 360 354 addr = amdgpu_bo_gpu_offset(bo); 361 355 entries = amdgpu_bo_size(bo) / 8; 362 356 363 357 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL); 364 358 if (!ib) 365 - goto error_unreserve; 359 + goto error; 366 360 367 361 r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib); 368 362 if (r) ··· 376 378 if (!r) 377 379 amdgpu_bo_fence(bo, fence, true); 378 380 fence_put(fence); 379 - if (amdgpu_enable_scheduler) { 380 - amdgpu_bo_unreserve(bo); 381 + if (amdgpu_enable_scheduler) 381 382 return 0; 382 - } 383 + 383 384 error_free: 384 385 amdgpu_ib_free(adev, ib); 385 386 kfree(ib); 386 387 387 - error_unreserve: 388 - amdgpu_bo_unreserve(bo); 388 + error: 389 389 return r; 390 390 } 391 391 ··· 985 989 * Add a mapping of the BO at the specefied addr into the VM. 986 990 * Returns 0 for success, error for failure. 987 991 * 988 - * Object has to be reserved and gets unreserved by this function! 992 + * Object has to be reserved and unreserved outside! 989 993 */ 990 994 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 991 995 struct amdgpu_bo_va *bo_va, ··· 1001 1005 1002 1006 /* validate the parameters */ 1003 1007 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK || 1004 - size == 0 || size & AMDGPU_GPU_PAGE_MASK) { 1005 - amdgpu_bo_unreserve(bo_va->bo); 1008 + size == 0 || size & AMDGPU_GPU_PAGE_MASK) 1006 1009 return -EINVAL; 1007 - } 1008 1010 1009 1011 /* make sure object fit at this offset */ 1010 1012 eaddr = saddr + size; 1011 - if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) { 1012 - amdgpu_bo_unreserve(bo_va->bo); 1013 + if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) 1013 1014 return -EINVAL; 1014 - } 1015 1015 1016 1016 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE; 1017 1017 if (last_pfn > adev->vm_manager.max_pfn) { 1018 1018 dev_err(adev->dev, "va above limit (0x%08X > 0x%08X)\n", 1019 1019 last_pfn, adev->vm_manager.max_pfn); 1020 - amdgpu_bo_unreserve(bo_va->bo); 1021 1020 return -EINVAL; 1022 1021 } 1023 1022 1024 1023 saddr /= AMDGPU_GPU_PAGE_SIZE; 1025 1024 eaddr /= AMDGPU_GPU_PAGE_SIZE; 1026 1025 1026 + spin_lock(&vm->it_lock); 1027 1027 it = interval_tree_iter_first(&vm->va, saddr, eaddr - 1); 1028 + spin_unlock(&vm->it_lock); 1028 1029 if (it) { 1029 1030 struct amdgpu_bo_va_mapping *tmp; 1030 1031 tmp = container_of(it, struct amdgpu_bo_va_mapping, it); ··· 1029 1036 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with " 1030 1037 "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr, 1031 1038 tmp->it.start, tmp->it.last + 1); 1032 - amdgpu_bo_unreserve(bo_va->bo); 1033 1039 r = -EINVAL; 1034 1040 goto error; 1035 1041 } 1036 1042 1037 1043 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); 1038 1044 if (!mapping) { 1039 - amdgpu_bo_unreserve(bo_va->bo); 1040 1045 r = -ENOMEM; 1041 1046 goto error; 1042 1047 } ··· 1046 1055 mapping->flags = flags; 1047 1056 1048 1057 list_add(&mapping->list, &bo_va->invalids); 1058 + spin_lock(&vm->it_lock); 1049 1059 interval_tree_insert(&mapping->it, &vm->va); 1060 + spin_unlock(&vm->it_lock); 1050 1061 trace_amdgpu_vm_bo_map(bo_va, mapping); 1051 1062 1052 1063 /* Make sure the page tables are allocated */ ··· 1060 1067 if (eaddr > vm->max_pde_used) 1061 1068 vm->max_pde_used = eaddr; 1062 1069 1063 - amdgpu_bo_unreserve(bo_va->bo); 1064 - 1065 1070 /* walk over the address space and allocate the page tables */ 1066 1071 for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) { 1067 1072 struct reservation_object *resv = vm->page_directory->tbo.resv; ··· 1068 1077 if (vm->page_tables[pt_idx].bo) 1069 1078 continue; 1070 1079 1071 - ww_mutex_lock(&resv->lock, NULL); 1072 1080 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, 1073 1081 AMDGPU_GPU_PAGE_SIZE, true, 1074 1082 AMDGPU_GEM_DOMAIN_VRAM, 1075 1083 AMDGPU_GEM_CREATE_NO_CPU_ACCESS, 1076 1084 NULL, resv, &pt); 1077 - ww_mutex_unlock(&resv->lock); 1078 1085 if (r) 1079 1086 goto error_free; 1080 1087 ··· 1090 1101 1091 1102 error_free: 1092 1103 list_del(&mapping->list); 1104 + spin_lock(&vm->it_lock); 1093 1105 interval_tree_remove(&mapping->it, &vm->va); 1106 + spin_unlock(&vm->it_lock); 1094 1107 trace_amdgpu_vm_bo_unmap(bo_va, mapping); 1095 1108 kfree(mapping); 1096 1109 ··· 1110 1119 * Remove a mapping of the BO at the specefied addr from the VM. 1111 1120 * Returns 0 for success, error for failure. 1112 1121 * 1113 - * Object has to be reserved and gets unreserved by this function! 1122 + * Object has to be reserved and unreserved outside! 1114 1123 */ 1115 1124 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 1116 1125 struct amdgpu_bo_va *bo_va, ··· 1135 1144 break; 1136 1145 } 1137 1146 1138 - if (&mapping->list == &bo_va->invalids) { 1139 - amdgpu_bo_unreserve(bo_va->bo); 1147 + if (&mapping->list == &bo_va->invalids) 1140 1148 return -ENOENT; 1141 - } 1142 1149 } 1143 1150 1144 1151 list_del(&mapping->list); 1152 + spin_lock(&vm->it_lock); 1145 1153 interval_tree_remove(&mapping->it, &vm->va); 1154 + spin_unlock(&vm->it_lock); 1146 1155 trace_amdgpu_vm_bo_unmap(bo_va, mapping); 1147 1156 1148 1157 if (valid) 1149 1158 list_add(&mapping->list, &vm->freed); 1150 1159 else 1151 1160 kfree(mapping); 1152 - amdgpu_bo_unreserve(bo_va->bo); 1153 1161 1154 1162 return 0; 1155 1163 } ··· 1177 1187 1178 1188 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) { 1179 1189 list_del(&mapping->list); 1190 + spin_lock(&vm->it_lock); 1180 1191 interval_tree_remove(&mapping->it, &vm->va); 1192 + spin_unlock(&vm->it_lock); 1181 1193 trace_amdgpu_vm_bo_unmap(bo_va, mapping); 1182 1194 list_add(&mapping->list, &vm->freed); 1183 1195 } 1184 1196 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) { 1185 1197 list_del(&mapping->list); 1198 + spin_lock(&vm->it_lock); 1186 1199 interval_tree_remove(&mapping->it, &vm->va); 1200 + spin_unlock(&vm->it_lock); 1187 1201 kfree(mapping); 1188 1202 } 1189 1203 ··· 1235 1241 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 1236 1242 vm->ids[i].id = 0; 1237 1243 vm->ids[i].flushed_updates = NULL; 1238 - vm->ids[i].last_id_use = NULL; 1239 1244 } 1240 1245 mutex_init(&vm->mutex); 1241 1246 vm->va = RB_ROOT; ··· 1242 1249 INIT_LIST_HEAD(&vm->invalidated); 1243 1250 INIT_LIST_HEAD(&vm->cleared); 1244 1251 INIT_LIST_HEAD(&vm->freed); 1245 - 1252 + spin_lock_init(&vm->it_lock); 1246 1253 pd_size = amdgpu_vm_directory_size(adev); 1247 1254 pd_entries = amdgpu_vm_num_pdes(adev); 1248 1255 ··· 1262 1269 NULL, NULL, &vm->page_directory); 1263 1270 if (r) 1264 1271 return r; 1265 - 1272 + r = amdgpu_bo_reserve(vm->page_directory, false); 1273 + if (r) { 1274 + amdgpu_bo_unref(&vm->page_directory); 1275 + vm->page_directory = NULL; 1276 + return r; 1277 + } 1266 1278 r = amdgpu_vm_clear_bo(adev, vm->page_directory); 1279 + amdgpu_bo_unreserve(vm->page_directory); 1267 1280 if (r) { 1268 1281 amdgpu_bo_unref(&vm->page_directory); 1269 1282 vm->page_directory = NULL; ··· 1312 1313 1313 1314 amdgpu_bo_unref(&vm->page_directory); 1314 1315 fence_put(vm->page_directory_fence); 1315 - 1316 1316 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 1317 + unsigned id = vm->ids[i].id; 1318 + 1319 + atomic_long_cmpxchg(&adev->vm_manager.ids[id].owner, 1320 + (long)vm, 0); 1317 1321 fence_put(vm->ids[i].flushed_updates); 1318 - fence_put(vm->ids[i].last_id_use); 1319 1322 } 1320 1323 1321 1324 mutex_destroy(&vm->mutex); 1325 + } 1326 + 1327 + /** 1328 + * amdgpu_vm_manager_fini - cleanup VM manager 1329 + * 1330 + * @adev: amdgpu_device pointer 1331 + * 1332 + * Cleanup the VM manager and free resources. 1333 + */ 1334 + void amdgpu_vm_manager_fini(struct amdgpu_device *adev) 1335 + { 1336 + unsigned i; 1337 + 1338 + for (i = 0; i < AMDGPU_NUM_VM; ++i) 1339 + fence_put(adev->vm_manager.ids[i].active); 1322 1340 }

+4 -4

drivers/gpu/drm/amd/amdgpu/ci_dpm.c

··· 6569 6569 switch (state) { 6570 6570 case AMDGPU_IRQ_STATE_DISABLE: 6571 6571 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT); 6572 - cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; 6572 + cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; 6573 6573 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int); 6574 6574 break; 6575 6575 case AMDGPU_IRQ_STATE_ENABLE: 6576 6576 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT); 6577 - cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; 6577 + cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; 6578 6578 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int); 6579 6579 break; 6580 6580 default: ··· 6586 6586 switch (state) { 6587 6587 case AMDGPU_IRQ_STATE_DISABLE: 6588 6588 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT); 6589 - cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; 6589 + cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; 6590 6590 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int); 6591 6591 break; 6592 6592 case AMDGPU_IRQ_STATE_ENABLE: 6593 6593 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT); 6594 - cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; 6594 + cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; 6595 6595 WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int); 6596 6596 break; 6597 6597 default:

+295 -7

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

··· 268 268 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 269 269 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, 270 270 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, 271 - mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, 272 271 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 273 272 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 274 273 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, ··· 295 296 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, 296 297 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 297 298 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, 298 - mmPCIE_INDEX, 0xffffffff, 0x0140001c, 299 - mmPCIE_DATA, 0x000f0000, 0x00000000, 300 - mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 301 - mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 302 299 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 303 300 }; 304 301 ··· 995 1000 adev->gfx.config.max_cu_per_sh = 16; 996 1001 adev->gfx.config.max_sh_per_se = 1; 997 1002 adev->gfx.config.max_backends_per_se = 4; 998 - adev->gfx.config.max_texture_channel_caches = 8; 1003 + adev->gfx.config.max_texture_channel_caches = 16; 999 1004 adev->gfx.config.max_gprs = 256; 1000 1005 adev->gfx.config.max_gs_threads = 32; 1001 1006 adev->gfx.config.max_hw_contexts = 8; ··· 1608 1613 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); 1609 1614 } 1610 1615 case CHIP_FIJI: 1616 + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1617 + switch (reg_offset) { 1618 + case 0: 1619 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1620 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1621 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1622 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1623 + break; 1624 + case 1: 1625 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1626 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1627 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1628 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1629 + break; 1630 + case 2: 1631 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1632 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1633 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1634 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1635 + break; 1636 + case 3: 1637 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1638 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1639 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1640 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1641 + break; 1642 + case 4: 1643 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1644 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1645 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1646 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1647 + break; 1648 + case 5: 1649 + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1650 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1651 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1652 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1653 + break; 1654 + case 6: 1655 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1656 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1657 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1658 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1659 + break; 1660 + case 7: 1661 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1662 + PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1663 + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1664 + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); 1665 + break; 1666 + case 8: 1667 + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1668 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)); 1669 + break; 1670 + case 9: 1671 + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1672 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1673 + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1674 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1675 + break; 1676 + case 10: 1677 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1678 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1679 + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1680 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1681 + break; 1682 + case 11: 1683 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1684 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1685 + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1686 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1687 + break; 1688 + case 12: 1689 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1690 + PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1691 + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | 1692 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1693 + break; 1694 + case 13: 1695 + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1696 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1697 + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1698 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1699 + break; 1700 + case 14: 1701 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1702 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1703 + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1704 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1705 + break; 1706 + case 15: 1707 + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | 1708 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1709 + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1710 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1711 + break; 1712 + case 16: 1713 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1714 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1715 + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1716 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1717 + break; 1718 + case 17: 1719 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1720 + PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1721 + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1722 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1723 + break; 1724 + case 18: 1725 + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1726 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1727 + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1728 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1729 + break; 1730 + case 19: 1731 + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1732 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1733 + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1734 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1735 + break; 1736 + case 20: 1737 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1738 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1739 + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1740 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1741 + break; 1742 + case 21: 1743 + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | 1744 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1745 + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1746 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1747 + break; 1748 + case 22: 1749 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1750 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1751 + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1752 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1753 + break; 1754 + case 23: 1755 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | 1756 + PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1757 + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1758 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1759 + break; 1760 + case 24: 1761 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1762 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1763 + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | 1764 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1765 + break; 1766 + case 25: 1767 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1768 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1769 + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1770 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1771 + break; 1772 + case 26: 1773 + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | 1774 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1775 + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | 1776 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); 1777 + break; 1778 + case 27: 1779 + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1780 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1781 + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1782 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1783 + break; 1784 + case 28: 1785 + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1786 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1787 + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1788 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); 1789 + break; 1790 + case 29: 1791 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1792 + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) | 1793 + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1794 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1795 + break; 1796 + case 30: 1797 + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | 1798 + PIPE_CONFIG(ADDR_SURF_P4_16x16) | 1799 + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | 1800 + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); 1801 + break; 1802 + default: 1803 + gb_tile_moden = 0; 1804 + break; 1805 + } 1806 + adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; 1807 + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); 1808 + } 1809 + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { 1810 + switch (reg_offset) { 1811 + case 0: 1812 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1813 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1814 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1815 + NUM_BANKS(ADDR_SURF_8_BANK)); 1816 + break; 1817 + case 1: 1818 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1819 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1820 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1821 + NUM_BANKS(ADDR_SURF_8_BANK)); 1822 + break; 1823 + case 2: 1824 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1825 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1826 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1827 + NUM_BANKS(ADDR_SURF_8_BANK)); 1828 + break; 1829 + case 3: 1830 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1831 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1832 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1833 + NUM_BANKS(ADDR_SURF_8_BANK)); 1834 + break; 1835 + case 4: 1836 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1837 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1838 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1839 + NUM_BANKS(ADDR_SURF_8_BANK)); 1840 + break; 1841 + case 5: 1842 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1843 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1844 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1845 + NUM_BANKS(ADDR_SURF_8_BANK)); 1846 + break; 1847 + case 6: 1848 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1849 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1850 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1851 + NUM_BANKS(ADDR_SURF_8_BANK)); 1852 + break; 1853 + case 8: 1854 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1855 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1856 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1857 + NUM_BANKS(ADDR_SURF_8_BANK)); 1858 + break; 1859 + case 9: 1860 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1861 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1862 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1863 + NUM_BANKS(ADDR_SURF_8_BANK)); 1864 + break; 1865 + case 10: 1866 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1867 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1868 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1869 + NUM_BANKS(ADDR_SURF_8_BANK)); 1870 + break; 1871 + case 11: 1872 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1873 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1874 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1875 + NUM_BANKS(ADDR_SURF_8_BANK)); 1876 + break; 1877 + case 12: 1878 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1879 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1880 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1881 + NUM_BANKS(ADDR_SURF_8_BANK)); 1882 + break; 1883 + case 13: 1884 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1885 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1886 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1887 + NUM_BANKS(ADDR_SURF_8_BANK)); 1888 + break; 1889 + case 14: 1890 + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1891 + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1892 + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1893 + NUM_BANKS(ADDR_SURF_4_BANK)); 1894 + break; 1895 + case 7: 1896 + /* unused idx */ 1897 + continue; 1898 + default: 1899 + gb_tile_moden = 0; 1900 + break; 1901 + } 1902 + adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; 1903 + WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); 1904 + } 1905 + break; 1611 1906 case CHIP_TONGA: 1612 1907 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1613 1908 switch (reg_offset) { ··· 3256 2971 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 3257 2972 switch (adev->asic_type) { 3258 2973 case CHIP_TONGA: 3259 - case CHIP_FIJI: 3260 2974 amdgpu_ring_write(ring, 0x16000012); 3261 2975 amdgpu_ring_write(ring, 0x0000002A); 2976 + break; 2977 + case CHIP_FIJI: 2978 + amdgpu_ring_write(ring, 0x3a00161a); 2979 + amdgpu_ring_write(ring, 0x0000002e); 3262 2980 break; 3263 2981 case CHIP_TOPAZ: 3264 2982 case CHIP_CARRIZO:

+4 -7

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

··· 40 40 static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev); 41 41 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); 42 42 43 - MODULE_FIRMWARE("radeon/boniare_mc.bin"); 43 + MODULE_FIRMWARE("radeon/bonaire_mc.bin"); 44 44 MODULE_FIRMWARE("radeon/hawaii_mc.bin"); 45 45 46 46 /** ··· 501 501 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 502 502 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 503 503 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 504 + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 504 505 WREG32(mmVM_L2_CNTL, tmp); 505 506 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 506 507 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); ··· 961 960 962 961 static int gmc_v7_0_sw_fini(void *handle) 963 962 { 964 - int i; 965 963 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 966 964 967 965 if (adev->vm_manager.enabled) { 968 - for (i = 0; i < AMDGPU_NUM_VM; ++i) 969 - fence_put(adev->vm_manager.active[i]); 966 + amdgpu_vm_manager_fini(adev); 970 967 gmc_v7_0_vm_fini(adev); 971 968 adev->vm_manager.enabled = false; 972 969 } ··· 1009 1010 1010 1011 static int gmc_v7_0_suspend(void *handle) 1011 1012 { 1012 - int i; 1013 1013 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1014 1014 1015 1015 if (adev->vm_manager.enabled) { 1016 - for (i = 0; i < AMDGPU_NUM_VM; ++i) 1017 - fence_put(adev->vm_manager.active[i]); 1016 + amdgpu_vm_manager_fini(adev); 1018 1017 gmc_v7_0_vm_fini(adev); 1019 1018 adev->vm_manager.enabled = false; 1020 1019 }

+3 -6

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

··· 629 629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 630 630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 631 631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 632 + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 632 633 WREG32(mmVM_L2_CNTL, tmp); 633 634 tmp = RREG32(mmVM_L2_CNTL2); 634 635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); ··· 980 979 981 980 static int gmc_v8_0_sw_fini(void *handle) 982 981 { 983 - int i; 984 982 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 985 983 986 984 if (adev->vm_manager.enabled) { 987 - for (i = 0; i < AMDGPU_NUM_VM; ++i) 988 - fence_put(adev->vm_manager.active[i]); 985 + amdgpu_vm_manager_fini(adev); 989 986 gmc_v8_0_vm_fini(adev); 990 987 adev->vm_manager.enabled = false; 991 988 } ··· 1030 1031 1031 1032 static int gmc_v8_0_suspend(void *handle) 1032 1033 { 1033 - int i; 1034 1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1035 1035 1036 1036 if (adev->vm_manager.enabled) { 1037 - for (i = 0; i < AMDGPU_NUM_VM; ++i) 1038 - fence_put(adev->vm_manager.active[i]); 1037 + amdgpu_vm_manager_fini(adev); 1039 1038 gmc_v8_0_vm_fini(adev); 1040 1039 adev->vm_manager.enabled = false; 1041 1040 }

+21 -3

drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h

··· 16 16 TP_ARGS(sched_job), 17 17 TP_STRUCT__entry( 18 18 __field(struct amd_sched_entity *, entity) 19 + __field(struct amd_sched_job *, sched_job) 20 + __field(struct fence *, fence) 19 21 __field(const char *, name) 20 22 __field(u32, job_count) 21 23 __field(int, hw_job_count) ··· 25 23 26 24 TP_fast_assign( 27 25 __entry->entity = sched_job->s_entity; 26 + __entry->sched_job = sched_job; 27 + __entry->fence = &sched_job->s_fence->base; 28 28 __entry->name = sched_job->sched->name; 29 29 __entry->job_count = kfifo_len( 30 30 &sched_job->s_entity->job_queue) / sizeof(sched_job); 31 31 __entry->hw_job_count = atomic_read( 32 32 &sched_job->sched->hw_rq_count); 33 33 ), 34 - TP_printk("entity=%p, ring=%s, job count:%u, hw job count:%d", 35 - __entry->entity, __entry->name, __entry->job_count, 36 - __entry->hw_job_count) 34 + TP_printk("entity=%p, sched job=%p, fence=%p, ring=%s, job count:%u, hw job count:%d", 35 + __entry->entity, __entry->sched_job, __entry->fence, __entry->name, 36 + __entry->job_count, __entry->hw_job_count) 37 37 ); 38 + 39 + TRACE_EVENT(amd_sched_process_job, 40 + TP_PROTO(struct amd_sched_fence *fence), 41 + TP_ARGS(fence), 42 + TP_STRUCT__entry( 43 + __field(struct fence *, fence) 44 + ), 45 + 46 + TP_fast_assign( 47 + __entry->fence = &fence->base; 48 + ), 49 + TP_printk("fence=%p signaled", __entry->fence) 50 + ); 51 + 38 52 #endif 39 53 40 54 /* This part must be outside protection */

+14 -10

drivers/gpu/drm/amd/scheduler/gpu_scheduler.c

··· 34 34 amd_sched_entity_pop_job(struct amd_sched_entity *entity); 35 35 static void amd_sched_wakeup(struct amd_gpu_scheduler *sched); 36 36 37 + struct kmem_cache *sched_fence_slab; 38 + atomic_t sched_fence_slab_ref = ATOMIC_INIT(0); 39 + 37 40 /* Initialize a given run queue struct */ 38 41 static void amd_sched_rq_init(struct amd_sched_rq *rq) 39 42 { ··· 276 273 * 277 274 * Returns 0 for success, negative error code otherwise. 278 275 */ 279 - int amd_sched_entity_push_job(struct amd_sched_job *sched_job) 276 + void amd_sched_entity_push_job(struct amd_sched_job *sched_job) 280 277 { 281 278 struct amd_sched_entity *entity = sched_job->s_entity; 282 - struct amd_sched_fence *fence = amd_sched_fence_create( 283 - entity, sched_job->owner); 284 - 285 - if (!fence) 286 - return -ENOMEM; 287 - 288 - fence_get(&fence->base); 289 - sched_job->s_fence = fence; 290 279 291 280 wait_event(entity->sched->job_scheduled, 292 281 amd_sched_entity_in(sched_job)); 293 282 trace_amd_sched_job(sched_job); 294 - return 0; 295 283 } 296 284 297 285 /** ··· 337 343 list_del_init(&s_fence->list); 338 344 spin_unlock_irqrestore(&sched->fence_list_lock, flags); 339 345 } 346 + trace_amd_sched_process_job(s_fence); 340 347 fence_put(&s_fence->base); 341 348 wake_up_interruptible(&sched->wake_up_worker); 342 349 } ··· 445 450 init_waitqueue_head(&sched->wake_up_worker); 446 451 init_waitqueue_head(&sched->job_scheduled); 447 452 atomic_set(&sched->hw_rq_count, 0); 453 + if (atomic_inc_return(&sched_fence_slab_ref) == 1) { 454 + sched_fence_slab = kmem_cache_create( 455 + "amd_sched_fence", sizeof(struct amd_sched_fence), 0, 456 + SLAB_HWCACHE_ALIGN, NULL); 457 + if (!sched_fence_slab) 458 + return -ENOMEM; 459 + } 448 460 449 461 /* Each scheduler will run on a seperate kernel thread */ 450 462 sched->thread = kthread_run(amd_sched_main, sched, sched->name); ··· 472 470 { 473 471 if (sched->thread) 474 472 kthread_stop(sched->thread); 473 + if (atomic_dec_and_test(&sched_fence_slab_ref)) 474 + kmem_cache_destroy(sched_fence_slab); 475 475 }

+4 -2

drivers/gpu/drm/amd/scheduler/gpu_scheduler.h

··· 30 30 struct amd_gpu_scheduler; 31 31 struct amd_sched_rq; 32 32 33 + extern struct kmem_cache *sched_fence_slab; 34 + extern atomic_t sched_fence_slab_ref; 35 + 33 36 /** 34 37 * A scheduler entity is a wrapper around a job queue or a group 35 38 * of other entities. Entities take turns emitting jobs from their ··· 79 76 struct amd_gpu_scheduler *sched; 80 77 struct amd_sched_entity *s_entity; 81 78 struct amd_sched_fence *s_fence; 82 - void *owner; 83 79 }; 84 80 85 81 extern const struct fence_ops amd_sched_fence_ops; ··· 130 128 uint32_t jobs); 131 129 void amd_sched_entity_fini(struct amd_gpu_scheduler *sched, 132 130 struct amd_sched_entity *entity); 133 - int amd_sched_entity_push_job(struct amd_sched_job *sched_job); 131 + void amd_sched_entity_push_job(struct amd_sched_job *sched_job); 134 132 135 133 struct amd_sched_fence *amd_sched_fence_create( 136 134 struct amd_sched_entity *s_entity, void *owner);

+8 -2

drivers/gpu/drm/amd/scheduler/sched_fence.c

··· 32 32 struct amd_sched_fence *fence = NULL; 33 33 unsigned seq; 34 34 35 - fence = kzalloc(sizeof(struct amd_sched_fence), GFP_KERNEL); 35 + fence = kmem_cache_zalloc(sched_fence_slab, GFP_KERNEL); 36 36 if (fence == NULL) 37 37 return NULL; 38 38 fence->owner = owner; ··· 71 71 return true; 72 72 } 73 73 74 + static void amd_sched_fence_release(struct fence *f) 75 + { 76 + struct amd_sched_fence *fence = to_amd_sched_fence(f); 77 + kmem_cache_free(sched_fence_slab, fence); 78 + } 79 + 74 80 const struct fence_ops amd_sched_fence_ops = { 75 81 .get_driver_name = amd_sched_fence_get_driver_name, 76 82 .get_timeline_name = amd_sched_fence_get_timeline_name, 77 83 .enable_signaling = amd_sched_fence_enable_signaling, 78 84 .signaled = NULL, 79 85 .wait = fence_default_wait, 80 - .release = NULL, 86 + .release = amd_sched_fence_release, 81 87 };

+42 -19

drivers/gpu/drm/drm_atomic.c

··· 1432 1432 return ret; 1433 1433 } 1434 1434 1435 + /** 1436 + * drm_atomic_update_old_fb -- Unset old_fb pointers and set plane->fb pointers. 1437 + * 1438 + * @dev: drm device to check. 1439 + * @plane_mask: plane mask for planes that were updated. 1440 + * @ret: return value, can be -EDEADLK for a retry. 1441 + * 1442 + * Before doing an update plane->old_fb is set to plane->fb, 1443 + * but before dropping the locks old_fb needs to be set to NULL 1444 + * and plane->fb updated. This is a common operation for each 1445 + * atomic update, so this call is split off as a helper. 1446 + */ 1447 + void drm_atomic_clean_old_fb(struct drm_device *dev, 1448 + unsigned plane_mask, 1449 + int ret) 1450 + { 1451 + struct drm_plane *plane; 1452 + 1453 + /* if succeeded, fixup legacy plane crtc/fb ptrs before dropping 1454 + * locks (ie. while it is still safe to deref plane->state). We 1455 + * need to do this here because the driver entry points cannot 1456 + * distinguish between legacy and atomic ioctls. 1457 + */ 1458 + drm_for_each_plane_mask(plane, dev, plane_mask) { 1459 + if (ret == 0) { 1460 + struct drm_framebuffer *new_fb = plane->state->fb; 1461 + if (new_fb) 1462 + drm_framebuffer_reference(new_fb); 1463 + plane->fb = new_fb; 1464 + plane->crtc = plane->state->crtc; 1465 + 1466 + if (plane->old_fb) 1467 + drm_framebuffer_unreference(plane->old_fb); 1468 + } 1469 + plane->old_fb = NULL; 1470 + } 1471 + } 1472 + EXPORT_SYMBOL(drm_atomic_clean_old_fb); 1473 + 1435 1474 int drm_mode_atomic_ioctl(struct drm_device *dev, 1436 1475 void *data, struct drm_file *file_priv) 1437 1476 { ··· 1485 1446 struct drm_plane *plane; 1486 1447 struct drm_crtc *crtc; 1487 1448 struct drm_crtc_state *crtc_state; 1488 - unsigned plane_mask = 0; 1449 + unsigned plane_mask; 1489 1450 int ret = 0; 1490 1451 unsigned int i, j; 1491 1452 ··· 1525 1486 state->allow_modeset = !!(arg->flags & DRM_MODE_ATOMIC_ALLOW_MODESET); 1526 1487 1527 1488 retry: 1489 + plane_mask = 0; 1528 1490 copied_objs = 0; 1529 1491 copied_props = 0; 1530 1492 ··· 1616 1576 } 1617 1577 1618 1578 out: 1619 - /* if succeeded, fixup legacy plane crtc/fb ptrs before dropping 1620 - * locks (ie. while it is still safe to deref plane->state). We 1621 - * need to do this here because the driver entry points cannot 1622 - * distinguish between legacy and atomic ioctls. 1623 - */ 1624 - drm_for_each_plane_mask(plane, dev, plane_mask) { 1625 - if (ret == 0) { 1626 - struct drm_framebuffer *new_fb = plane->state->fb; 1627 - if (new_fb) 1628 - drm_framebuffer_reference(new_fb); 1629 - plane->fb = new_fb; 1630 - plane->crtc = plane->state->crtc; 1631 - 1632 - if (plane->old_fb) 1633 - drm_framebuffer_unreference(plane->old_fb); 1634 - } 1635 - plane->old_fb = NULL; 1636 - } 1579 + drm_atomic_clean_old_fb(dev, plane_mask, ret); 1637 1580 1638 1581 if (ret && arg->flags & DRM_MODE_PAGE_FLIP_EVENT) { 1639 1582 /*

+20 -9

drivers/gpu/drm/drm_atomic_helper.c

··· 210 210 return -EINVAL; 211 211 } 212 212 213 + if (!drm_encoder_crtc_ok(new_encoder, connector_state->crtc)) { 214 + DRM_DEBUG_ATOMIC("[ENCODER:%d:%s] incompatible with [CRTC:%d]\n", 215 + new_encoder->base.id, 216 + new_encoder->name, 217 + connector_state->crtc->base.id); 218 + return -EINVAL; 219 + } 220 + 213 221 if (new_encoder == connector_state->best_encoder) { 214 222 DRM_DEBUG_ATOMIC("[CONNECTOR:%d:%s] keeps [ENCODER:%d:%s], now on [CRTC:%d]\n", 215 223 connector->base.id, ··· 1561 1553 goto fail; 1562 1554 } 1563 1555 1556 + if (plane_state->crtc && (plane == plane->crtc->cursor)) 1557 + plane_state->state->legacy_cursor_update = true; 1558 + 1564 1559 ret = __drm_atomic_helper_disable_plane(plane, plane_state); 1565 1560 if (ret != 0) 1566 1561 goto fail; ··· 1615 1604 plane_state->src_y = 0; 1616 1605 plane_state->src_h = 0; 1617 1606 plane_state->src_w = 0; 1618 - 1619 - if (plane->crtc && (plane == plane->crtc->cursor)) 1620 - plane_state->state->legacy_cursor_update = true; 1621 1607 1622 1608 return 0; 1623 1609 } ··· 1749 1741 struct drm_crtc_state *crtc_state; 1750 1742 struct drm_plane_state *primary_state; 1751 1743 struct drm_crtc *crtc = set->crtc; 1744 + int hdisplay, vdisplay; 1752 1745 int ret; 1753 1746 1754 1747 crtc_state = drm_atomic_get_crtc_state(state, crtc); ··· 1792 1783 if (ret != 0) 1793 1784 return ret; 1794 1785 1786 + drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); 1787 + 1795 1788 drm_atomic_set_fb_for_plane(primary_state, set->fb); 1796 1789 primary_state->crtc_x = 0; 1797 1790 primary_state->crtc_y = 0; 1798 - primary_state->crtc_h = set->mode->vdisplay; 1799 - primary_state->crtc_w = set->mode->hdisplay; 1791 + primary_state->crtc_h = vdisplay; 1792 + primary_state->crtc_w = hdisplay; 1800 1793 primary_state->src_x = set->x << 16; 1801 1794 primary_state->src_y = set->y << 16; 1802 1795 if (primary_state->rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))) { 1803 - primary_state->src_h = set->mode->hdisplay << 16; 1804 - primary_state->src_w = set->mode->vdisplay << 16; 1796 + primary_state->src_h = hdisplay << 16; 1797 + primary_state->src_w = vdisplay << 16; 1805 1798 } else { 1806 - primary_state->src_h = set->mode->vdisplay << 16; 1807 - primary_state->src_w = set->mode->hdisplay << 16; 1799 + primary_state->src_h = vdisplay << 16; 1800 + primary_state->src_w = hdisplay << 16; 1808 1801 } 1809 1802 1810 1803 commit:

+14 -37

drivers/gpu/drm/drm_fb_helper.c

··· 342 342 struct drm_plane *plane; 343 343 struct drm_atomic_state *state; 344 344 int i, ret; 345 + unsigned plane_mask; 345 346 346 347 state = drm_atomic_state_alloc(dev); 347 348 if (!state) ··· 350 349 351 350 state->acquire_ctx = dev->mode_config.acquire_ctx; 352 351 retry: 352 + plane_mask = 0; 353 353 drm_for_each_plane(plane, dev) { 354 354 struct drm_plane_state *plane_state; 355 - 356 - plane->old_fb = plane->fb; 357 355 358 356 plane_state = drm_atomic_get_plane_state(state, plane); 359 357 if (IS_ERR(plane_state)) { ··· 361 361 } 362 362 363 363 plane_state->rotation = BIT(DRM_ROTATE_0); 364 + 365 + plane->old_fb = plane->fb; 366 + plane_mask |= 1 << drm_plane_index(plane); 364 367 365 368 /* disable non-primary: */ 366 369 if (plane->type == DRM_PLANE_TYPE_PRIMARY) ··· 385 382 ret = drm_atomic_commit(state); 386 383 387 384 fail: 388 - drm_for_each_plane(plane, dev) { 389 - if (ret == 0) { 390 - struct drm_framebuffer *new_fb = plane->state->fb; 391 - if (new_fb) 392 - drm_framebuffer_reference(new_fb); 393 - plane->fb = new_fb; 394 - plane->crtc = plane->state->crtc; 395 - 396 - if (plane->old_fb) 397 - drm_framebuffer_unreference(plane->old_fb); 398 - } 399 - plane->old_fb = NULL; 400 - } 385 + drm_atomic_clean_old_fb(dev, plane_mask, ret); 401 386 402 387 if (ret == -EDEADLK) 403 388 goto backoff; ··· 1227 1236 struct drm_fb_helper *fb_helper = info->par; 1228 1237 struct drm_device *dev = fb_helper->dev; 1229 1238 struct drm_atomic_state *state; 1239 + struct drm_plane *plane; 1230 1240 int i, ret; 1241 + unsigned plane_mask; 1231 1242 1232 1243 state = drm_atomic_state_alloc(dev); 1233 1244 if (!state) ··· 1237 1244 1238 1245 state->acquire_ctx = dev->mode_config.acquire_ctx; 1239 1246 retry: 1247 + plane_mask = 0; 1240 1248 for(i = 0; i < fb_helper->crtc_count; i++) { 1241 1249 struct drm_mode_set *mode_set; 1242 1250 1243 1251 mode_set = &fb_helper->crtc_info[i].mode_set; 1244 - 1245 - mode_set->crtc->primary->old_fb = mode_set->crtc->primary->fb; 1246 1252 1247 1253 mode_set->x = var->xoffset; 1248 1254 mode_set->y = var->yoffset; ··· 1249 1257 ret = __drm_atomic_helper_set_config(mode_set, state); 1250 1258 if (ret != 0) 1251 1259 goto fail; 1260 + 1261 + plane = mode_set->crtc->primary; 1262 + plane_mask |= drm_plane_index(plane); 1263 + plane->old_fb = plane->fb; 1252 1264 } 1253 1265 1254 1266 ret = drm_atomic_commit(state); ··· 1264 1268 1265 1269 1266 1270 fail: 1267 - for(i = 0; i < fb_helper->crtc_count; i++) { 1268 - struct drm_mode_set *mode_set; 1269 - struct drm_plane *plane; 1270 - 1271 - mode_set = &fb_helper->crtc_info[i].mode_set; 1272 - plane = mode_set->crtc->primary; 1273 - 1274 - if (ret == 0) { 1275 - struct drm_framebuffer *new_fb = plane->state->fb; 1276 - 1277 - if (new_fb) 1278 - drm_framebuffer_reference(new_fb); 1279 - plane->fb = new_fb; 1280 - plane->crtc = plane->state->crtc; 1281 - 1282 - if (plane->old_fb) 1283 - drm_framebuffer_unreference(plane->old_fb); 1284 - } 1285 - plane->old_fb = NULL; 1286 - } 1271 + drm_atomic_clean_old_fb(dev, plane_mask, ret); 1287 1272 1288 1273 if (ret == -EDEADLK) 1289 1274 goto backoff;

+4

drivers/gpu/drm/i915/i915_drv.h

··· 351 351 /* hsw/bdw */ 352 352 DPLL_ID_WRPLL1 = 0, 353 353 DPLL_ID_WRPLL2 = 1, 354 + DPLL_ID_SPLL = 2, 355 + 354 356 /* skl */ 355 357 DPLL_ID_SKL_DPLL1 = 0, 356 358 DPLL_ID_SKL_DPLL2 = 1, ··· 369 367 370 368 /* hsw, bdw */ 371 369 uint32_t wrpll; 370 + uint32_t spll; 372 371 373 372 /* skl */ 374 373 /* ··· 2651 2648 int enable_cmd_parser; 2652 2649 /* leave bools at the end to not create holes */ 2653 2650 bool enable_hangcheck; 2651 + bool fastboot; 2654 2652 bool prefault_disable; 2655 2653 bool load_detect_test; 2656 2654 bool reset;

+7 -1

drivers/gpu/drm/i915/i915_gem.c

··· 3809 3809 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 3810 3810 struct drm_file *file) 3811 3811 { 3812 + struct drm_i915_private *dev_priv = dev->dev_private; 3812 3813 struct drm_i915_gem_caching *args = data; 3813 3814 struct drm_i915_gem_object *obj; 3814 3815 enum i915_cache_level level; ··· 3838 3837 return -EINVAL; 3839 3838 } 3840 3839 3840 + intel_runtime_pm_get(dev_priv); 3841 + 3841 3842 ret = i915_mutex_lock_interruptible(dev); 3842 3843 if (ret) 3843 - return ret; 3844 + goto rpm_put; 3844 3845 3845 3846 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 3846 3847 if (&obj->base == NULL) { ··· 3855 3852 drm_gem_object_unreference(&obj->base); 3856 3853 unlock: 3857 3854 mutex_unlock(&dev->struct_mutex); 3855 + rpm_put: 3856 + intel_runtime_pm_put(dev_priv); 3857 + 3858 3858 return ret; 3859 3859 } 3860 3860

+5

drivers/gpu/drm/i915/i915_params.c

··· 40 40 .preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT), 41 41 .disable_power_well = -1, 42 42 .enable_ips = 1, 43 + .fastboot = 0, 43 44 .prefault_disable = 0, 44 45 .load_detect_test = 0, 45 46 .reset = true, ··· 133 132 134 133 module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600); 135 134 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)"); 135 + 136 + module_param_named(fastboot, i915.fastboot, bool, 0600); 137 + MODULE_PARM_DESC(fastboot, 138 + "Try to skip unnecessary mode sets at boot time (default: false)"); 136 139 137 140 module_param_named_unsafe(prefault_disable, i915.prefault_disable, bool, 0600); 138 141 MODULE_PARM_DESC(prefault_disable,

+4 -27

drivers/gpu/drm/i915/intel_crt.c

··· 138 138 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 139 139 } 140 140 141 - static void hsw_crt_pre_enable(struct intel_encoder *encoder) 142 - { 143 - struct drm_device *dev = encoder->base.dev; 144 - struct drm_i915_private *dev_priv = dev->dev_private; 145 - 146 - WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); 147 - I915_WRITE(SPLL_CTL, 148 - SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC); 149 - POSTING_READ(SPLL_CTL); 150 - udelay(20); 151 - } 152 - 153 141 /* Note: The caller is required to filter out dpms modes not supported by the 154 142 * platform. */ 155 143 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) ··· 204 216 intel_disable_crt(encoder); 205 217 } 206 218 207 - static void hsw_crt_post_disable(struct intel_encoder *encoder) 208 - { 209 - struct drm_device *dev = encoder->base.dev; 210 - struct drm_i915_private *dev_priv = dev->dev_private; 211 - uint32_t val; 212 - 213 - DRM_DEBUG_KMS("Disabling SPLL\n"); 214 - val = I915_READ(SPLL_CTL); 215 - WARN_ON(!(val & SPLL_PLL_ENABLE)); 216 - I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 217 - POSTING_READ(SPLL_CTL); 218 - } 219 - 220 219 static void intel_enable_crt(struct intel_encoder *encoder) 221 220 { 222 221 struct intel_crt *crt = intel_encoder_to_crt(encoder); ··· 255 280 if (HAS_DDI(dev)) { 256 281 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; 257 282 pipe_config->port_clock = 135000 * 2; 283 + 284 + pipe_config->dpll_hw_state.wrpll = 0; 285 + pipe_config->dpll_hw_state.spll = 286 + SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; 258 287 } 259 288 260 289 return true; ··· 839 860 if (HAS_DDI(dev)) { 840 861 crt->base.get_config = hsw_crt_get_config; 841 862 crt->base.get_hw_state = intel_ddi_get_hw_state; 842 - crt->base.pre_enable = hsw_crt_pre_enable; 843 - crt->base.post_disable = hsw_crt_post_disable; 844 863 } else { 845 864 crt->base.get_config = intel_crt_get_config; 846 865 crt->base.get_hw_state = intel_crt_get_hw_state;

+65 -10

drivers/gpu/drm/i915/intel_ddi.c

··· 1286 1286 } 1287 1287 1288 1288 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); 1289 + } else if (crtc_state->ddi_pll_sel == PORT_CLK_SEL_SPLL) { 1290 + struct drm_atomic_state *state = crtc_state->base.state; 1291 + struct intel_shared_dpll_config *spll = 1292 + &intel_atomic_get_shared_dpll_state(state)[DPLL_ID_SPLL]; 1293 + 1294 + if (spll->crtc_mask && 1295 + WARN_ON(spll->hw_state.spll != crtc_state->dpll_hw_state.spll)) 1296 + return false; 1297 + 1298 + crtc_state->shared_dpll = DPLL_ID_SPLL; 1299 + spll->hw_state.spll = crtc_state->dpll_hw_state.spll; 1300 + spll->crtc_mask |= 1 << intel_crtc->pipe; 1289 1301 } 1290 1302 1291 1303 return true; ··· 2449 2437 } 2450 2438 } 2451 2439 2452 - static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, 2440 + static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, 2453 2441 struct intel_shared_dpll *pll) 2454 2442 { 2455 2443 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); ··· 2457 2445 udelay(20); 2458 2446 } 2459 2447 2460 - static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, 2448 + static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, 2461 2449 struct intel_shared_dpll *pll) 2450 + { 2451 + I915_WRITE(SPLL_CTL, pll->config.hw_state.spll); 2452 + POSTING_READ(SPLL_CTL); 2453 + udelay(20); 2454 + } 2455 + 2456 + static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, 2457 + struct intel_shared_dpll *pll) 2462 2458 { 2463 2459 uint32_t val; 2464 2460 ··· 2475 2455 POSTING_READ(WRPLL_CTL(pll->id)); 2476 2456 } 2477 2457 2478 - static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2479 - struct intel_shared_dpll *pll, 2480 - struct intel_dpll_hw_state *hw_state) 2458 + static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, 2459 + struct intel_shared_dpll *pll) 2460 + { 2461 + uint32_t val; 2462 + 2463 + val = I915_READ(SPLL_CTL); 2464 + I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 2465 + POSTING_READ(SPLL_CTL); 2466 + } 2467 + 2468 + static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, 2469 + struct intel_shared_dpll *pll, 2470 + struct intel_dpll_hw_state *hw_state) 2481 2471 { 2482 2472 uint32_t val; 2483 2473 ··· 2500 2470 return val & WRPLL_PLL_ENABLE; 2501 2471 } 2502 2472 2473 + static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, 2474 + struct intel_shared_dpll *pll, 2475 + struct intel_dpll_hw_state *hw_state) 2476 + { 2477 + uint32_t val; 2478 + 2479 + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2480 + return false; 2481 + 2482 + val = I915_READ(SPLL_CTL); 2483 + hw_state->spll = val; 2484 + 2485 + return val & SPLL_PLL_ENABLE; 2486 + } 2487 + 2488 + 2503 2489 static const char * const hsw_ddi_pll_names[] = { 2504 2490 "WRPLL 1", 2505 2491 "WRPLL 2", 2492 + "SPLL" 2506 2493 }; 2507 2494 2508 2495 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) 2509 2496 { 2510 2497 int i; 2511 2498 2512 - dev_priv->num_shared_dpll = 2; 2499 + dev_priv->num_shared_dpll = 3; 2513 2500 2514 - for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2501 + for (i = 0; i < 2; i++) { 2515 2502 dev_priv->shared_dplls[i].id = i; 2516 2503 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 2517 - dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; 2518 - dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; 2504 + dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable; 2505 + dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable; 2519 2506 dev_priv->shared_dplls[i].get_hw_state = 2520 - hsw_ddi_pll_get_hw_state; 2507 + hsw_ddi_wrpll_get_hw_state; 2521 2508 } 2509 + 2510 + /* SPLL is special, but needs to be initialized anyway.. */ 2511 + dev_priv->shared_dplls[i].id = i; 2512 + dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 2513 + dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable; 2514 + dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable; 2515 + dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state; 2516 + 2522 2517 } 2523 2518 2524 2519 static const char * const skl_ddi_pll_names[] = {

+27 -10

drivers/gpu/drm/i915/intel_display.c

··· 2646 2646 return; 2647 2647 2648 2648 valid_fb: 2649 - plane_state->src_x = plane_state->src_y = 0; 2649 + plane_state->src_x = 0; 2650 + plane_state->src_y = 0; 2650 2651 plane_state->src_w = fb->width << 16; 2651 2652 plane_state->src_h = fb->height << 16; 2652 2653 2653 - plane_state->crtc_x = plane_state->src_y = 0; 2654 + plane_state->crtc_x = 0; 2655 + plane_state->crtc_y = 0; 2654 2656 plane_state->crtc_w = fb->width; 2655 2657 plane_state->crtc_h = fb->height; 2656 2658 ··· 4239 4237 struct intel_shared_dpll *pll; 4240 4238 struct intel_shared_dpll_config *shared_dpll; 4241 4239 enum intel_dpll_id i; 4240 + int max = dev_priv->num_shared_dpll; 4242 4241 4243 4242 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); 4244 4243 ··· 4274 4271 WARN_ON(shared_dpll[i].crtc_mask); 4275 4272 4276 4273 goto found; 4277 - } 4274 + } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) 4275 + /* Do not consider SPLL */ 4276 + max = 2; 4278 4277 4279 - for (i = 0; i < dev_priv->num_shared_dpll; i++) { 4278 + for (i = 0; i < max; i++) { 4280 4279 pll = &dev_priv->shared_dplls[i]; 4281 4280 4282 4281 /* Only want to check enabled timings first */ ··· 9728 9723 case PORT_CLK_SEL_WRPLL2: 9729 9724 pipe_config->shared_dpll = DPLL_ID_WRPLL2; 9730 9725 break; 9726 + case PORT_CLK_SEL_SPLL: 9727 + pipe_config->shared_dpll = DPLL_ID_SPLL; 9731 9728 } 9732 9729 } 9733 9730 ··· 12010 12003 pipe_config->dpll_hw_state.cfgcr1, 12011 12004 pipe_config->dpll_hw_state.cfgcr2); 12012 12005 } else if (HAS_DDI(dev)) { 12013 - DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n", 12006 + DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", 12014 12007 pipe_config->ddi_pll_sel, 12015 - pipe_config->dpll_hw_state.wrpll); 12008 + pipe_config->dpll_hw_state.wrpll, 12009 + pipe_config->dpll_hw_state.spll); 12016 12010 } else { 12017 12011 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " 12018 12012 "fp0: 0x%x, fp1: 0x%x\n", ··· 12536 12528 PIPE_CONF_CHECK_X(dpll_hw_state.fp0); 12537 12529 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); 12538 12530 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); 12531 + PIPE_CONF_CHECK_X(dpll_hw_state.spll); 12539 12532 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); 12540 12533 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); 12541 12534 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); ··· 13041 13032 struct intel_crtc_state *pipe_config = 13042 13033 to_intel_crtc_state(crtc_state); 13043 13034 13035 + memset(&to_intel_crtc(crtc)->atomic, 0, 13036 + sizeof(struct intel_crtc_atomic_commit)); 13037 + 13044 13038 /* Catch I915_MODE_FLAG_INHERITED */ 13045 13039 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) 13046 13040 crtc_state->mode_changed = true; ··· 13068 13056 if (ret) 13069 13057 return ret; 13070 13058 13071 - if (intel_pipe_config_compare(state->dev, 13059 + if (i915.fastboot && 13060 + intel_pipe_config_compare(state->dev, 13072 13061 to_intel_crtc_state(crtc->state), 13073 13062 pipe_config, true)) { 13074 13063 crtc_state->mode_changed = false; ··· 14377 14364 static struct drm_framebuffer * 14378 14365 intel_user_framebuffer_create(struct drm_device *dev, 14379 14366 struct drm_file *filp, 14380 - struct drm_mode_fb_cmd2 *mode_cmd) 14367 + struct drm_mode_fb_cmd2 *user_mode_cmd) 14381 14368 { 14382 14369 struct drm_i915_gem_object *obj; 14370 + struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; 14383 14371 14384 14372 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, 14385 - mode_cmd->handles[0])); 14373 + mode_cmd.handles[0])); 14386 14374 if (&obj->base == NULL) 14387 14375 return ERR_PTR(-ENOENT); 14388 14376 14389 - return intel_framebuffer_create(dev, mode_cmd, obj); 14377 + return intel_framebuffer_create(dev, &mode_cmd, obj); 14390 14378 } 14391 14379 14392 14380 #ifndef CONFIG_DRM_FBDEV_EMULATION ··· 14718 14704 14719 14705 /* Apple Macbook 2,1 (Core 2 T7400) */ 14720 14706 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, 14707 + 14708 + /* Apple Macbook 4,1 */ 14709 + { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, 14721 14710 14722 14711 /* Toshiba CB35 Chromebook (Celeron 2955U) */ 14723 14712 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },

+6 -4

drivers/gpu/drm/i915/intel_pm.c

··· 4449 4449 POSTING_READ(GEN6_RPNSWREQ); 4450 4450 4451 4451 dev_priv->rps.cur_freq = val; 4452 - trace_intel_gpu_freq_change(val * 50); 4452 + trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); 4453 4453 } 4454 4454 4455 4455 static void valleyview_set_rps(struct drm_device *dev, u8 val) ··· 7255 7255 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) 7256 7256 { 7257 7257 if (IS_GEN9(dev_priv->dev)) 7258 - return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER; 7258 + return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, 7259 + GEN9_FREQ_SCALER); 7259 7260 else if (IS_CHERRYVIEW(dev_priv->dev)) 7260 7261 return chv_gpu_freq(dev_priv, val); 7261 7262 else if (IS_VALLEYVIEW(dev_priv->dev)) ··· 7268 7267 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) 7269 7268 { 7270 7269 if (IS_GEN9(dev_priv->dev)) 7271 - return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER; 7270 + return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, 7271 + GT_FREQUENCY_MULTIPLIER); 7272 7272 else if (IS_CHERRYVIEW(dev_priv->dev)) 7273 7273 return chv_freq_opcode(dev_priv, val); 7274 7274 else if (IS_VALLEYVIEW(dev_priv->dev)) 7275 7275 return byt_freq_opcode(dev_priv, val); 7276 7276 else 7277 - return val / GT_FREQUENCY_MULTIPLIER; 7277 + return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); 7278 7278 } 7279 7279 7280 7280 struct request_boost {

+5 -6

drivers/gpu/drm/mgag200/mgag200_cursor.c

··· 70 70 BUG_ON(pixels_2 != pixels_current && pixels_2 != pixels_prev); 71 71 BUG_ON(pixels_current == pixels_prev); 72 72 73 + if (!handle || !file_priv) { 74 + mga_hide_cursor(mdev); 75 + return 0; 76 + } 77 + 73 78 obj = drm_gem_object_lookup(dev, file_priv, handle); 74 79 if (!obj) 75 80 return -ENOENT; ··· 91 86 WREG8(MGA_CURPOSXH, 0); 92 87 mgag200_bo_unreserve(pixels_1); 93 88 goto out_unreserve1; 94 - } 95 - 96 - if (!handle) { 97 - mga_hide_cursor(mdev); 98 - ret = 0; 99 - goto out1; 100 89 } 101 90 102 91 /* Move cursor buffers into VRAM if they aren't already */

+11 -4

drivers/gpu/drm/radeon/radeon_object.c

··· 221 221 if (!(rdev->flags & RADEON_IS_PCIE)) 222 222 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 223 223 224 + /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx 225 + * See https://bugs.freedesktop.org/show_bug.cgi?id=91268 226 + */ 227 + if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635) 228 + bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 229 + 224 230 #ifdef CONFIG_X86_32 225 231 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 226 232 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 227 233 */ 228 - bo->flags &= ~RADEON_GEM_GTT_WC; 234 + bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 229 235 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 230 236 /* Don't try to enable write-combining when it can't work, or things 231 237 * may be slow ··· 241 235 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 242 236 thanks to write-combining 243 237 244 - DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 245 - "better performance thanks to write-combining\n"); 246 - bo->flags &= ~RADEON_GEM_GTT_WC; 238 + if (bo->flags & RADEON_GEM_GTT_WC) 239 + DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 240 + "better performance thanks to write-combining\n"); 241 + bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 247 242 #endif 248 243 249 244 radeon_ttm_placement_from_domain(bo, domain);

+1 -2

drivers/gpu/drm/radeon/radeon_pm.c

··· 1542 1542 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1543 1543 if (ret) 1544 1544 DRM_ERROR("failed to create device file for power method\n"); 1545 - if (!ret) 1546 - rdev->pm.sysfs_initialized = true; 1545 + rdev->pm.sysfs_initialized = true; 1547 1546 } 1548 1547 1549 1548 mutex_lock(&rdev->pm.mutex);

+1 -1

drivers/gpu/drm/radeon/si_dpm.c

··· 2927 2927 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 }, 2928 2928 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 }, 2929 2929 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 }, 2930 - { PCI_VENDOR_ID_ATI, 0x6811, 0x1762, 0x2015, 0, 120000 }, 2930 + { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 }, 2931 2931 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 }, 2932 2932 { 0, 0, 0, 0 }, 2933 2933 };

+5 -4

drivers/gpu/drm/vc4/vc4_crtc.c

··· 168 168 struct drm_connector *connector; 169 169 170 170 drm_for_each_connector(connector, crtc->dev) { 171 - if (connector && connector->state->crtc == crtc) { 171 + if (connector->state->crtc == crtc) { 172 172 struct drm_encoder *encoder = connector->encoder; 173 173 struct vc4_encoder *vc4_encoder = 174 174 to_vc4_encoder(encoder); ··· 401 401 dlist_next++; 402 402 403 403 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), 404 - (u32 *)vc4_crtc->dlist - (u32 *)vc4->hvs->dlist); 404 + (u32 __iomem *)vc4_crtc->dlist - 405 + (u32 __iomem *)vc4->hvs->dlist); 405 406 406 407 /* Make the next display list start after ours. */ 407 408 vc4_crtc->dlist_size -= (dlist_next - vc4_crtc->dlist); ··· 592 591 * that will take too much. 593 592 */ 594 593 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY); 595 - if (!primary_plane) { 594 + if (IS_ERR(primary_plane)) { 596 595 dev_err(dev, "failed to construct primary plane\n"); 597 596 ret = PTR_ERR(primary_plane); 598 597 goto err; 599 598 } 600 599 601 600 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR); 602 - if (!cursor_plane) { 601 + if (IS_ERR(cursor_plane)) { 603 602 dev_err(dev, "failed to construct cursor plane\n"); 604 603 ret = PTR_ERR(cursor_plane); 605 604 goto err_primary;

-1

drivers/gpu/drm/vc4/vc4_drv.c

··· 259 259 .remove = vc4_platform_drm_remove, 260 260 .driver = { 261 261 .name = "vc4-drm", 262 - .owner = THIS_MODULE, 263 262 .of_match_table = vc4_of_match, 264 263 }, 265 264 };

+4 -4

drivers/gpu/drm/vc4/vc4_hvs.c

··· 75 75 for (i = 0; i < 64; i += 4) { 76 76 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n", 77 77 i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D", 78 - ((uint32_t *)vc4->hvs->dlist)[i + 0], 79 - ((uint32_t *)vc4->hvs->dlist)[i + 1], 80 - ((uint32_t *)vc4->hvs->dlist)[i + 2], 81 - ((uint32_t *)vc4->hvs->dlist)[i + 3]); 78 + readl((u32 __iomem *)vc4->hvs->dlist + i + 0), 79 + readl((u32 __iomem *)vc4->hvs->dlist + i + 1), 80 + readl((u32 __iomem *)vc4->hvs->dlist + i + 2), 81 + readl((u32 __iomem *)vc4->hvs->dlist + i + 3)); 82 82 } 83 83 } 84 84

+14 -4

drivers/gpu/drm/vc4/vc4_plane.c

··· 70 70 return state->fb && state->crtc; 71 71 } 72 72 73 - struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane) 73 + static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane) 74 74 { 75 75 struct vc4_plane_state *vc4_state; 76 76 ··· 97 97 return &vc4_state->base; 98 98 } 99 99 100 - void vc4_plane_destroy_state(struct drm_plane *plane, 101 - struct drm_plane_state *state) 100 + static void vc4_plane_destroy_state(struct drm_plane *plane, 101 + struct drm_plane_state *state) 102 102 { 103 103 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 104 104 ··· 108 108 } 109 109 110 110 /* Called during init to allocate the plane's atomic state. */ 111 - void vc4_plane_reset(struct drm_plane *plane) 111 + static void vc4_plane_reset(struct drm_plane *plane) 112 112 { 113 113 struct vc4_plane_state *vc4_state; 114 114 ··· 156 156 int crtc_y = state->crtc_y; 157 157 int crtc_w = state->crtc_w; 158 158 int crtc_h = state->crtc_h; 159 + 160 + if (state->crtc_w << 16 != state->src_w || 161 + state->crtc_h << 16 != state->src_h) { 162 + /* We don't support scaling yet, which involves 163 + * allocating the LBM memory for scaling temporary 164 + * storage, and putting filter kernels in the HVS 165 + * context. 166 + */ 167 + return -EINVAL; 168 + } 159 169 160 170 if (crtc_x < 0) { 161 171 offset += drm_format_plane_cpp(fb->pixel_format, 0) * -crtc_x;

+3

include/drm/drm_atomic.h

··· 136 136 137 137 void drm_atomic_legacy_backoff(struct drm_atomic_state *state); 138 138 139 + void 140 + drm_atomic_clean_old_fb(struct drm_device *dev, unsigned plane_mask, int ret); 141 + 139 142 int __must_check drm_atomic_check_only(struct drm_atomic_state *state); 140 143 int __must_check drm_atomic_commit(struct drm_atomic_state *state); 141 144 int __must_check drm_atomic_async_commit(struct drm_atomic_state *state);

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