tjh.dev / kernel
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Merge tag 'drm-fixes-2025-11-21' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"A range of small fixes across the board, the i915 display
disambiguation is probably the biggest otherwise amdgpu and xe as
usual with tegra, nouveau, radeon and a core atomic fix.

Looks mostly normal.

atomic:
- Return error codes on failed blob creation for planes

nouveau:
- Fix memory leak

tegra:
- Fix device ref counting
- Fix pid ref counting
- Revert booting on Pixel C

xe:
- Fix out-of-bounds access with BIT()
- Fix kunit test checking wrong condition
- Drop duplicate kconfig select
- Fix guc2host irq handler with MSI-X

i915:
- Wildcat Lake and Panther Lake detangled for display fixes

amdgpu:
- DTBCLK gating fix
- EDID fetching retry improvements
- HDMI HPD debounce filtering
- DCN 2.0 cursor fix
- DP MST PBN fix
- VPE fix
- GC 11 fix
- PRT fix
- MMIO remap page fix
- SR-IOV fix

radeon:
- Fence deadlock fix"

* tag 'drm-fixes-2025-11-21' of https://gitlab.freedesktop.org/drm/kernel: (25 commits)
drm/amdgpu: Add sriov vf check for VCN per queue reset support.
drm/amdgpu/ttm: Fix crash when handling MMIO_REMAP in PDE flags
drm/amdgpu/vm: Check PRT uAPI flag instead of PTE flag
drm/amdgpu: Skip emit de meta data on gfx11 with rs64 enabled
drm/amd: Skip power ungate during suspend for VPE
drm/plane: Fix create_in_format_blob() return value
drm/xe/irq: Handle msix vector0 interrupt
drm/xe: Remove duplicate DRM_EXEC selection from Kconfig
drm/xe/kunit: Fix forcewake assertion in mocs test
drm/xe: Prevent BIT() overflow when handling invalid prefetch region
drm/radeon: delete radeon_fence_process in is_signaled, no deadlock
drm/amd/display: Fix pbn to kbps Conversion
drm/amd/display: Clear the CUR_ENABLE register on DCN20 on DPP5
drm/amd/display: Add an HPD filter for HDMI
drm/amd/display: Increase DPCD read retries
drm/amd/display: Move sleep into each retry for retrieve_link_cap()
drm/amd/display: Prevent Gating DTBCLK before It Is Properly Latched
drm/i915/xe3: Restrict PTL intel_encoder_is_c10phy() to only PHY A
drm/i915/display: Add definition for wcl as subplatform
drm/pcids: Split PTL pciids group to make wcl subplatform
...

Linus Torvalds c6d732c3 a48f8229

+246 -105
+2 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 3414 3414 (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || 3415 3415 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA)) 3416 3416 continue; 3417 - /* skip CG for VCE/UVD, it's handled specially */ 3417 + /* skip CG for VCE/UVD/VPE, it's handled specially */ 3418 3418 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && 3419 3419 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && 3420 3420 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && 3421 + adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VPE && 3421 3422 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && 3422 3423 adev->ip_blocks[i].version->funcs->set_powergating_state) { 3423 3424 /* enable powergating to save power */
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
··· 1372 1372 mem->mem_type == AMDGPU_PL_MMIO_REMAP)) { 1373 1373 flags |= AMDGPU_PTE_SYSTEM; 1374 1374 1375 - if (ttm->caching == ttm_cached) 1375 + if (ttm && ttm->caching == ttm_cached) 1376 1376 flags |= AMDGPU_PTE_SNOOPED; 1377 1377 } 1378 1378
+2 -2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
··· 2078 2078 struct amdgpu_bo *bo = before->bo_va->base.bo; 2079 2079 2080 2080 amdgpu_vm_it_insert(before, &vm->va); 2081 - if (before->flags & AMDGPU_PTE_PRT_FLAG(adev)) 2081 + if (before->flags & AMDGPU_VM_PAGE_PRT) 2082 2082 amdgpu_vm_prt_get(adev); 2083 2083 2084 2084 if (amdgpu_vm_is_bo_always_valid(vm, bo) && ··· 2093 2093 struct amdgpu_bo *bo = after->bo_va->base.bo; 2094 2094 2095 2095 amdgpu_vm_it_insert(after, &vm->va); 2096 - if (after->flags & AMDGPU_PTE_PRT_FLAG(adev)) 2096 + if (after->flags & AMDGPU_VM_PAGE_PRT) 2097 2097 amdgpu_vm_prt_get(adev); 2098 2098 2099 2099 if (amdgpu_vm_is_bo_always_valid(vm, bo) &&
+2 -2
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 5872 5872 if (flags & AMDGPU_IB_PREEMPTED) 5873 5873 control |= INDIRECT_BUFFER_PRE_RESUME(1); 5874 5874 5875 - if (vmid) 5875 + if (vmid && !ring->adev->gfx.rs64_enable) 5876 5876 gfx_v11_0_ring_emit_de_meta(ring, 5877 - (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 5877 + !amdgpu_sriov_vf(ring->adev) && (flags & AMDGPU_IB_PREEMPTED)); 5878 5878 } 5879 5879 5880 5880 amdgpu_ring_write(ring, header);
+1 -1
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
··· 141 141 adev->vcn.supported_reset = 142 142 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 143 143 144 - if (amdgpu_dpm_reset_vcn_is_supported(adev)) 144 + if (amdgpu_dpm_reset_vcn_is_supported(adev) && !amdgpu_sriov_vf(adev)) 145 145 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 146 146 147 147 return 0;
+3 -1
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
··· 122 122 123 123 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 124 124 case IP_VERSION(13, 0, 12): 125 - if ((adev->psp.sos.fw_version >= 0x00450025) && amdgpu_dpm_reset_vcn_is_supported(adev)) 125 + if ((adev->psp.sos.fw_version >= 0x00450025) && 126 + amdgpu_dpm_reset_vcn_is_supported(adev) && 127 + !amdgpu_sriov_vf(adev)) 126 128 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 127 129 break; 128 130 default:
+138
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 3859 3859 update_subconnector_property(aconnector); 3860 3860 } 3861 3861 3862 + static bool are_sinks_equal(const struct dc_sink *sink1, const struct dc_sink *sink2) 3863 + { 3864 + if (!sink1 || !sink2) 3865 + return false; 3866 + if (sink1->sink_signal != sink2->sink_signal) 3867 + return false; 3868 + 3869 + if (sink1->dc_edid.length != sink2->dc_edid.length) 3870 + return false; 3871 + 3872 + if (memcmp(sink1->dc_edid.raw_edid, sink2->dc_edid.raw_edid, 3873 + sink1->dc_edid.length) != 0) 3874 + return false; 3875 + return true; 3876 + } 3877 + 3878 + 3879 + /** 3880 + * DOC: hdmi_hpd_debounce_work 3881 + * 3882 + * HDMI HPD debounce delay in milliseconds. When an HDMI display toggles HPD 3883 + * (such as during power save transitions), this delay determines how long to 3884 + * wait before processing the HPD event. This allows distinguishing between a 3885 + * physical unplug (>hdmi_hpd_debounce_delay) 3886 + * and a spontaneous RX HPD toggle (<hdmi_hpd_debounce_delay). 3887 + * 3888 + * If the toggle is less than this delay, the driver compares sink capabilities 3889 + * and permits a hotplug event if they changed. 3890 + * 3891 + * The default value of 1500ms was chosen based on experimental testing with 3892 + * various monitors that exhibit spontaneous HPD toggling behavior. 3893 + */ 3894 + static void hdmi_hpd_debounce_work(struct work_struct *work) 3895 + { 3896 + struct amdgpu_dm_connector *aconnector = 3897 + container_of(to_delayed_work(work), struct amdgpu_dm_connector, 3898 + hdmi_hpd_debounce_work); 3899 + struct drm_connector *connector = &aconnector->base; 3900 + struct drm_device *dev = connector->dev; 3901 + struct amdgpu_device *adev = drm_to_adev(dev); 3902 + struct dc *dc = aconnector->dc_link->ctx->dc; 3903 + bool fake_reconnect = false; 3904 + bool reallow_idle = false; 3905 + bool ret = false; 3906 + guard(mutex)(&aconnector->hpd_lock); 3907 + 3908 + /* Re-detect the display */ 3909 + scoped_guard(mutex, &adev->dm.dc_lock) { 3910 + if (dc->caps.ips_support && dc->ctx->dmub_srv->idle_allowed) { 3911 + dc_allow_idle_optimizations(dc, false); 3912 + reallow_idle = true; 3913 + } 3914 + ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 3915 + } 3916 + 3917 + if (ret) { 3918 + /* Apply workaround delay for certain panels */ 3919 + apply_delay_after_dpcd_poweroff(adev, aconnector->dc_sink); 3920 + /* Compare sinks to determine if this was a spontaneous HPD toggle */ 3921 + if (are_sinks_equal(aconnector->dc_link->local_sink, aconnector->hdmi_prev_sink)) { 3922 + /* 3923 + * Sinks match - this was a spontaneous HDMI HPD toggle. 3924 + */ 3925 + drm_dbg_kms(dev, "HDMI HPD: Sink unchanged after debounce, internal re-enable\n"); 3926 + fake_reconnect = true; 3927 + } 3928 + 3929 + /* Update connector state */ 3930 + amdgpu_dm_update_connector_after_detect(aconnector); 3931 + 3932 + drm_modeset_lock_all(dev); 3933 + dm_restore_drm_connector_state(dev, connector); 3934 + drm_modeset_unlock_all(dev); 3935 + 3936 + /* Only notify OS if sink actually changed */ 3937 + if (!fake_reconnect && aconnector->base.force == DRM_FORCE_UNSPECIFIED) 3938 + drm_kms_helper_hotplug_event(dev); 3939 + } 3940 + 3941 + /* Release the cached sink reference */ 3942 + if (aconnector->hdmi_prev_sink) { 3943 + dc_sink_release(aconnector->hdmi_prev_sink); 3944 + aconnector->hdmi_prev_sink = NULL; 3945 + } 3946 + 3947 + scoped_guard(mutex, &adev->dm.dc_lock) { 3948 + if (reallow_idle && dc->caps.ips_support) 3949 + dc_allow_idle_optimizations(dc, true); 3950 + } 3951 + } 3952 + 3862 3953 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) 3863 3954 { 3864 3955 struct drm_connector *connector = &aconnector->base; ··· 3959 3868 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state); 3960 3869 struct dc *dc = aconnector->dc_link->ctx->dc; 3961 3870 bool ret = false; 3871 + bool debounce_required = false; 3962 3872 3963 3873 if (adev->dm.disable_hpd_irq) 3964 3874 return; ··· 3982 3890 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) 3983 3891 drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); 3984 3892 3893 + /* 3894 + * Check for HDMI disconnect with debounce enabled. 3895 + */ 3896 + debounce_required = (aconnector->hdmi_hpd_debounce_delay_ms > 0 && 3897 + dc_is_hdmi_signal(aconnector->dc_link->connector_signal) && 3898 + new_connection_type == dc_connection_none && 3899 + aconnector->dc_link->local_sink != NULL); 3900 + 3985 3901 if (aconnector->base.force && new_connection_type == dc_connection_none) { 3986 3902 emulated_link_detect(aconnector->dc_link); 3987 3903 ··· 3999 3899 4000 3900 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) 4001 3901 drm_kms_helper_connector_hotplug_event(connector); 3902 + } else if (debounce_required) { 3903 + /* 3904 + * HDMI disconnect detected - schedule delayed work instead of 3905 + * processing immediately. This allows us to coalesce spurious 3906 + * HDMI signals from physical unplugs. 3907 + */ 3908 + drm_dbg_kms(dev, "HDMI HPD: Disconnect detected, scheduling debounce work (%u ms)\n", 3909 + aconnector->hdmi_hpd_debounce_delay_ms); 3910 + 3911 + /* Cache the current sink for later comparison */ 3912 + if (aconnector->hdmi_prev_sink) 3913 + dc_sink_release(aconnector->hdmi_prev_sink); 3914 + aconnector->hdmi_prev_sink = aconnector->dc_link->local_sink; 3915 + if (aconnector->hdmi_prev_sink) 3916 + dc_sink_retain(aconnector->hdmi_prev_sink); 3917 + 3918 + /* Schedule delayed detection. */ 3919 + if (mod_delayed_work(system_wq, 3920 + &aconnector->hdmi_hpd_debounce_work, 3921 + msecs_to_jiffies(aconnector->hdmi_hpd_debounce_delay_ms))) 3922 + drm_dbg_kms(dev, "HDMI HPD: Re-scheduled debounce work\n"); 3923 + 4002 3924 } else { 3925 + 3926 + /* If the aconnector->hdmi_hpd_debounce_work is scheduled, exit early */ 3927 + if (delayed_work_pending(&aconnector->hdmi_hpd_debounce_work)) 3928 + return; 3929 + 4003 3930 scoped_guard(mutex, &adev->dm.dc_lock) { 4004 3931 dc_exit_ips_for_hw_access(dc); 4005 3932 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); ··· 7515 7388 if (aconnector->mst_mgr.dev) 7516 7389 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr); 7517 7390 7391 + /* Cancel and flush any pending HDMI HPD debounce work */ 7392 + cancel_delayed_work_sync(&aconnector->hdmi_hpd_debounce_work); 7393 + if (aconnector->hdmi_prev_sink) { 7394 + dc_sink_release(aconnector->hdmi_prev_sink); 7395 + aconnector->hdmi_prev_sink = NULL; 7396 + } 7397 + 7518 7398 if (aconnector->bl_idx != -1) { 7519 7399 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]); 7520 7400 dm->backlight_dev[aconnector->bl_idx] = NULL; ··· 8682 8548 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); 8683 8549 mutex_init(&aconnector->hpd_lock); 8684 8550 mutex_init(&aconnector->handle_mst_msg_ready); 8551 + 8552 + aconnector->hdmi_hpd_debounce_delay_ms = AMDGPU_DM_HDMI_HPD_DEBOUNCE_MS; 8553 + INIT_DELAYED_WORK(&aconnector->hdmi_hpd_debounce_work, hdmi_hpd_debounce_work); 8554 + aconnector->hdmi_prev_sink = NULL; 8685 8555 8686 8556 /* 8687 8557 * configure support HPD hot plug connector_>polled default value is 0
+6
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
··· 59 59 60 60 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) 61 61 62 + #define AMDGPU_DM_HDMI_HPD_DEBOUNCE_MS 1500 62 63 /* 63 64 #include "include/amdgpu_dal_power_if.h" 64 65 #include "amdgpu_dm_irq.h" ··· 820 819 bool pack_sdp_v1_3; 821 820 enum adaptive_sync_type as_type; 822 821 struct amdgpu_hdmi_vsdb_info vsdb_info; 822 + 823 + /* HDMI HPD debounce support */ 824 + unsigned int hdmi_hpd_debounce_delay_ms; 825 + struct delayed_work hdmi_hpd_debounce_work; 826 + struct dc_sink *hdmi_prev_sink; 823 827 }; 824 828 825 829 static inline void amdgpu_dm_set_mst_status(uint8_t *status,
+23 -36
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
··· 884 884 }; 885 885 886 886 #if defined(CONFIG_DRM_AMD_DC_FP) 887 - static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link) 887 + static uint64_t kbps_to_pbn(int kbps, bool is_peak_pbn) 888 888 { 889 - u8 link_coding_cap; 890 - uint16_t fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_8B_10B; 889 + uint64_t effective_kbps = (uint64_t)kbps; 891 890 892 - link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(dc_link); 893 - if (link_coding_cap == DP_128b_132b_ENCODING) 894 - fec_overhead_multiplier_x1000 = PBN_FEC_OVERHEAD_MULTIPLIER_128B_132B; 891 + if (is_peak_pbn) { // add 0.6% (1006/1000) overhead into effective kbps 892 + effective_kbps *= 1006; 893 + effective_kbps = div_u64(effective_kbps, 1000); 894 + } 895 895 896 - return fec_overhead_multiplier_x1000; 896 + return (uint64_t) DIV64_U64_ROUND_UP(effective_kbps * 64, (54 * 8 * 1000)); 897 897 } 898 898 899 - static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000) 899 + static uint32_t pbn_to_kbps(unsigned int pbn, bool with_margin) 900 900 { 901 - u64 peak_kbps = kbps; 901 + uint64_t pbn_effective = (uint64_t)pbn; 902 902 903 - peak_kbps *= 1006; 904 - peak_kbps *= fec_overhead_multiplier_x1000; 905 - peak_kbps = div_u64(peak_kbps, 1000 * 1000); 906 - return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); 903 + if (with_margin) // deduct 0.6% (994/1000) overhead from effective pbn 904 + pbn_effective *= (1000000 / PEAK_FACTOR_X1000); 905 + else 906 + pbn_effective *= 1000; 907 + 908 + return DIV_U64_ROUND_UP(pbn_effective * 8 * 54, 64); 907 909 } 908 910 909 911 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, ··· 976 974 dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options); 977 975 dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; 978 976 979 - kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); 977 + kbps = pbn_to_kbps(pbn, false); 980 978 dc_dsc_compute_config( 981 979 param.sink->ctx->dc->res_pool->dscs[0], 982 980 &param.sink->dsc_caps.dsc_dec_caps, ··· 1005 1003 int link_timeslots_used; 1006 1004 int fair_pbn_alloc; 1007 1005 int ret = 0; 1008 - uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 1009 1006 1010 1007 for (i = 0; i < count; i++) { 1011 1008 if (vars[i + k].dsc_enabled) { 1012 1009 initial_slack[i] = 1013 - kbps_to_peak_pbn(params[i].bw_range.max_kbps, fec_overhead_multiplier_x1000) - vars[i + k].pbn; 1010 + kbps_to_pbn(params[i].bw_range.max_kbps, false) - vars[i + k].pbn; 1014 1011 bpp_increased[i] = false; 1015 1012 remaining_to_increase += 1; 1016 1013 } else { ··· 1105 1104 int next_index; 1106 1105 int remaining_to_try = 0; 1107 1106 int ret; 1108 - uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 1109 1107 int var_pbn; 1110 1108 1111 1109 for (i = 0; i < count; i++) { ··· 1137 1137 1138 1138 DRM_DEBUG_DRIVER("MST_DSC index #%d, try no compression\n", next_index); 1139 1139 var_pbn = vars[next_index].pbn; 1140 - vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1140 + vars[next_index].pbn = kbps_to_pbn(params[next_index].bw_range.stream_kbps, true); 1141 1141 ret = drm_dp_atomic_find_time_slots(state, 1142 1142 params[next_index].port->mgr, 1143 1143 params[next_index].port, ··· 1197 1197 int count = 0; 1198 1198 int i, k, ret; 1199 1199 bool debugfs_overwrite = false; 1200 - uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); 1201 1200 struct drm_connector_state *new_conn_state; 1202 1201 1203 1202 memset(params, 0, sizeof(params)); ··· 1277 1278 DRM_DEBUG_DRIVER("MST_DSC Try no compression\n"); 1278 1279 for (i = 0; i < count; i++) { 1279 1280 vars[i + k].aconnector = params[i].aconnector; 1280 - vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1281 + vars[i + k].pbn = kbps_to_pbn(params[i].bw_range.stream_kbps, false); 1281 1282 vars[i + k].dsc_enabled = false; 1282 1283 vars[i + k].bpp_x16 = 0; 1283 1284 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port, ··· 1299 1300 DRM_DEBUG_DRIVER("MST_DSC Try max compression\n"); 1300 1301 for (i = 0; i < count; i++) { 1301 1302 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) { 1302 - vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000); 1303 + vars[i + k].pbn = kbps_to_pbn(params[i].bw_range.min_kbps, false); 1303 1304 vars[i + k].dsc_enabled = true; 1304 1305 vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16; 1305 1306 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, ··· 1307 1308 if (ret < 0) 1308 1309 return ret; 1309 1310 } else { 1310 - vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000); 1311 + vars[i + k].pbn = kbps_to_pbn(params[i].bw_range.stream_kbps, false); 1311 1312 vars[i + k].dsc_enabled = false; 1312 1313 vars[i + k].bpp_x16 = 0; 1313 1314 ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, ··· 1762 1763 return ret; 1763 1764 } 1764 1765 1765 - static uint32_t kbps_from_pbn(unsigned int pbn) 1766 - { 1767 - uint64_t kbps = (uint64_t)pbn; 1768 - 1769 - kbps *= (1000000 / PEAK_FACTOR_X1000); 1770 - kbps *= 8; 1771 - kbps *= 54; 1772 - kbps /= 64; 1773 - 1774 - return (uint32_t)kbps; 1775 - } 1776 - 1777 1766 static bool is_dsc_common_config_possible(struct dc_stream_state *stream, 1778 1767 struct dc_dsc_bw_range *bw_range) 1779 1768 { ··· 1860 1873 dc_link_get_highest_encoding_format(stream->link)); 1861 1874 cur_link_settings = stream->link->verified_link_cap; 1862 1875 root_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, &cur_link_settings); 1863 - virtual_channel_bw_in_kbps = kbps_from_pbn(aconnector->mst_output_port->full_pbn); 1876 + virtual_channel_bw_in_kbps = pbn_to_kbps(aconnector->mst_output_port->full_pbn, true); 1864 1877 1865 1878 /* pick the end to end bw bottleneck */ 1866 1879 end_to_end_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps); ··· 1913 1926 immediate_upstream_port = aconnector->mst_output_port->parent->port_parent; 1914 1927 1915 1928 if (immediate_upstream_port) { 1916 - virtual_channel_bw_in_kbps = kbps_from_pbn(immediate_upstream_port->full_pbn); 1929 + virtual_channel_bw_in_kbps = pbn_to_kbps(immediate_upstream_port->full_pbn, true); 1917 1930 virtual_channel_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps); 1918 1931 } else { 1919 1932 /* For topology LCT 1 case - only one mstb*/
+3 -1
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
··· 394 394 display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps); 395 395 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz) 396 396 new_clocks->ref_dtbclk_khz = 600000; 397 + else if (!new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz > 590000) 398 + new_clocks->ref_dtbclk_khz = 0; 397 399 398 400 /* 399 401 * if it is safe to lower, but we are already in the lower state, we don't have to do anything ··· 437 435 438 436 actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT); 439 437 440 - if (actual_dtbclk) { 438 + if (actual_dtbclk > 590000) { 441 439 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; 442 440 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; 443 441 }
+1 -1
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
··· 1411 1411 __func__, params->otg_inst, params->pixclk_khz, 1412 1412 params->ref_dtbclk_khz, req_dtbclk_khz, phase, modulo); 1413 1413 1414 - } else { 1414 + } else if (!params->ref_dtbclk_khz && !req_dtbclk_khz) { 1415 1415 switch (params->otg_inst) { 1416 1416 case 0: 1417 1417 REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 0);
+8
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
··· 614 614 * DOMAIN11_PGFSM_PWR_STATUS, pwr_status, 615 615 * 1, 1000); 616 616 */ 617 + 618 + /* Force disable cursor on plane powerdown on DPP 5 using dpp_force_disable_cursor */ 619 + if (!power_on) { 620 + struct dpp *dpp5 = hws->ctx->dc->res_pool->dpps[dpp_inst]; 621 + if (dpp5 && dpp5->funcs->dpp_force_disable_cursor) 622 + dpp5->funcs->dpp_force_disable_cursor(dpp5); 623 + } 624 + 617 625 break; 618 626 default: 619 627 BREAK_TO_DEBUGGER();
+2 -2
drivers/gpu/drm/drm_plane.c
··· 210 210 formats_size = sizeof(__u32) * plane->format_count; 211 211 if (WARN_ON(!formats_size)) { 212 212 /* 0 formats are never expected */ 213 - return 0; 213 + return ERR_PTR(-EINVAL); 214 214 } 215 215 216 216 modifiers_size = ··· 226 226 227 227 blob = drm_property_create_blob(dev, blob_size, NULL); 228 228 if (IS_ERR(blob)) 229 - return NULL; 229 + return blob; 230 230 231 231 blob_data = blob->data; 232 232 blob_data->version = FORMAT_BLOB_CURRENT;
+6 -8
drivers/gpu/drm/i915/display/intel_cx0_phy.c
··· 39 39 struct intel_display *display = to_intel_display(encoder); 40 40 enum phy phy = intel_encoder_to_phy(encoder); 41 41 42 - /* PTL doesn't have a PHY connected to PORT B; as such, 43 - * there will never be a case where PTL uses PHY B. 44 - * WCL uses PORT A and B with the C10 PHY. 45 - * Reusing the condition for WCL and extending it for PORT B 46 - * should not cause any issues for PTL. 47 - */ 48 - if (display->platform.pantherlake && phy < PHY_C) 49 - return true; 42 + if (display->platform.pantherlake) { 43 + if (display->platform.pantherlake_wildcatlake) 44 + return phy <= PHY_B; 45 + else 46 + return phy == PHY_A; 47 + } 50 48 51 49 if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C) 52 50 return true;
+13
drivers/gpu/drm/i915/display/intel_display_device.c
··· 1404 1404 PLATFORM_GROUP(dgfx), 1405 1405 }; 1406 1406 1407 + static const u16 wcl_ids[] = { 1408 + INTEL_WCL_IDS(ID), 1409 + 0 1410 + }; 1411 + 1407 1412 static const struct platform_desc ptl_desc = { 1408 1413 PLATFORM(pantherlake), 1414 + .subplatforms = (const struct subplatform_desc[]) { 1415 + { 1416 + SUBPLATFORM(pantherlake, wildcatlake), 1417 + .pciidlist = wcl_ids, 1418 + }, 1419 + {}, 1420 + } 1409 1421 }; 1410 1422 1411 1423 __diag_pop(); ··· 1494 1482 INTEL_LNL_IDS(INTEL_DISPLAY_DEVICE, &lnl_desc), 1495 1483 INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc), 1496 1484 INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc), 1485 + INTEL_WCL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc), 1497 1486 }; 1498 1487 1499 1488 static const struct {
+3 -1
drivers/gpu/drm/i915/display/intel_display_device.h
··· 101 101 /* Display ver 14.1 (based on GMD ID) */ \ 102 102 func(battlemage) \ 103 103 /* Display ver 30 (based on GMD ID) */ \ 104 - func(pantherlake) 104 + func(pantherlake) \ 105 + func(pantherlake_wildcatlake) 106 + 105 107 106 108 #define __MEMBER(name) unsigned long name:1; 107 109 #define __COUNT(x) 1 +
+7 -3
drivers/gpu/drm/i915/display/intel_dmc.c
··· 127 127 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 128 128 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 129 129 130 + #define XE3LPD_3002_DMC_PATH DMC_PATH(xe3lpd_3002) 131 + MODULE_FIRMWARE(XE3LPD_3002_DMC_PATH); 132 + 130 133 #define XE3LPD_DMC_PATH DMC_PATH(xe3lpd) 131 134 MODULE_FIRMWARE(XE3LPD_DMC_PATH); 132 135 ··· 186 183 { 187 184 const char *fw_path = NULL; 188 185 u32 max_fw_size = 0; 189 - 190 - if (DISPLAY_VERx100(display) == 3002 || 191 - DISPLAY_VERx100(display) == 3000) { 186 + if (DISPLAY_VERx100(display) == 3002) { 187 + fw_path = XE3LPD_3002_DMC_PATH; 188 + max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 189 + } else if (DISPLAY_VERx100(display) == 3000) { 192 190 fw_path = XE3LPD_DMC_PATH; 193 191 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 194 192 } else if (DISPLAY_VERx100(display) == 2000) {
+2
drivers/gpu/drm/nouveau/nvkm/falcon/fw.c
··· 159 159 nvkm_memory_unref(&fw->inst); 160 160 nvkm_falcon_fw_dtor_sigs(fw); 161 161 nvkm_firmware_dtor(&fw->fw); 162 + kfree(fw->boot); 163 + fw->boot = NULL; 162 164 } 163 165 164 166 static const struct nvkm_firmware_func
-7
drivers/gpu/drm/radeon/radeon_fence.c
··· 360 360 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) 361 361 return true; 362 362 363 - if (down_read_trylock(&rdev->exclusive_lock)) { 364 - radeon_fence_process(rdev, ring); 365 - up_read(&rdev->exclusive_lock); 366 - 367 - if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) 368 - return true; 369 - } 370 363 return false; 371 364 } 372 365
+1
drivers/gpu/drm/tegra/dc.c
··· 3148 3148 dc->client.parent = &parent->client; 3149 3149 3150 3150 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); 3151 + put_device(companion); 3151 3152 } 3152 3153 3153 3154 return 0;
-9
drivers/gpu/drm/tegra/dsi.c
··· 913 913 u32 value; 914 914 int err; 915 915 916 - /* If the bootloader enabled DSI it needs to be disabled 917 - * in order for the panel initialization commands to be 918 - * properly sent. 919 - */ 920 - value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 921 - 922 - if (value & DSI_POWER_CONTROL_ENABLE) 923 - tegra_dsi_disable(dsi); 924 - 925 916 err = tegra_dsi_prepare(dsi); 926 917 if (err < 0) { 927 918 dev_err(dsi->dev, "failed to prepare: %d\n", err);
+5 -2
drivers/gpu/drm/tegra/uapi.c
··· 114 114 if (err) 115 115 goto put_channel; 116 116 117 - if (supported) 117 + if (supported) { 118 + struct pid *pid = get_task_pid(current, PIDTYPE_TGID); 118 119 context->memory_context = host1x_memory_context_alloc( 119 - host, client->base.dev, get_task_pid(current, PIDTYPE_TGID)); 120 + host, client->base.dev, pid); 121 + put_pid(pid); 122 + } 120 123 121 124 if (IS_ERR(context->memory_context)) { 122 125 if (PTR_ERR(context->memory_context) != -EOPNOTSUPP) {
-1
drivers/gpu/drm/xe/Kconfig
··· 13 13 select TMPFS 14 14 select DRM_BUDDY 15 15 select DRM_CLIENT_SELECTION 16 - select DRM_EXEC 17 16 select DRM_KMS_HELPER 18 17 select DRM_KUNIT_TEST_HELPERS if DRM_XE_KUNIT_TEST != n 19 18 select DRM_PANEL
+1 -1
drivers/gpu/drm/xe/tests/xe_mocs.c
··· 49 49 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 50 50 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { 51 51 xe_force_wake_put(gt_to_fw(gt), fw_ref); 52 - KUNIT_ASSERT_TRUE_MSG(test, true, "Forcewake Failed.\n"); 52 + KUNIT_FAIL_AND_ABORT(test, "Forcewake Failed.\n"); 53 53 } 54 54 55 55 for (i = 0; i < info->num_mocs_regs; i++) {
+1 -17
drivers/gpu/drm/xe/xe_irq.c
··· 847 847 return 0; 848 848 } 849 849 850 - static irqreturn_t guc2host_irq_handler(int irq, void *arg) 851 - { 852 - struct xe_device *xe = arg; 853 - struct xe_tile *tile; 854 - u8 id; 855 - 856 - if (!atomic_read(&xe->irq.enabled)) 857 - return IRQ_NONE; 858 - 859 - for_each_tile(tile, xe, id) 860 - xe_guc_irq_handler(&tile->primary_gt->uc.guc, 861 - GUC_INTR_GUC2HOST); 862 - 863 - return IRQ_HANDLED; 864 - } 865 - 866 850 static irqreturn_t xe_irq_msix_default_hwe_handler(int irq, void *arg) 867 851 { 868 852 unsigned int tile_id, gt_id; ··· 963 979 u16 msix; 964 980 965 981 msix = GUC2HOST_MSIX; 966 - err = xe_irq_msix_request_irq(xe, guc2host_irq_handler, xe, 982 + err = xe_irq_msix_request_irq(xe, xe_irq_handler(xe), xe, 967 983 DRIVER_NAME "-guc2host", false, &msix); 968 984 if (err) 969 985 return err;
+1
drivers/gpu/drm/xe/xe_pci.c
··· 375 375 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc), 376 376 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc), 377 377 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 378 + INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc), 378 379 { } 379 380 }; 380 381 MODULE_DEVICE_TABLE(pci, pciidlist);
+4 -2
drivers/gpu/drm/xe/xe_vm.c
··· 3369 3369 op == DRM_XE_VM_BIND_OP_PREFETCH) || 3370 3370 XE_IOCTL_DBG(xe, prefetch_region && 3371 3371 op != DRM_XE_VM_BIND_OP_PREFETCH) || 3372 - XE_IOCTL_DBG(xe, (prefetch_region != DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC && 3373 - !(BIT(prefetch_region) & xe->info.mem_region_mask))) || 3372 + XE_IOCTL_DBG(xe, (prefetch_region != DRM_XE_CONSULT_MEM_ADVISE_PREF_LOC && 3373 + /* Guard against undefined shift in BIT(prefetch_region) */ 3374 + (prefetch_region >= (sizeof(xe->info.mem_region_mask) * 8) || 3375 + !(BIT(prefetch_region) & xe->info.mem_region_mask)))) || 3374 3376 XE_IOCTL_DBG(xe, obj && 3375 3377 op == DRM_XE_VM_BIND_OP_UNMAP) || 3376 3378 XE_IOCTL_DBG(xe, (flags & DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET) &&
+4 -1
include/drm/intel/pciids.h
··· 877 877 MACRO__(0xB08F, ## __VA_ARGS__), \ 878 878 MACRO__(0xB090, ## __VA_ARGS__), \ 879 879 MACRO__(0xB0A0, ## __VA_ARGS__), \ 880 - MACRO__(0xB0B0, ## __VA_ARGS__), \ 880 + MACRO__(0xB0B0, ## __VA_ARGS__) 881 + 882 + /* WCL */ 883 + #define INTEL_WCL_IDS(MACRO__, ...) \ 881 884 MACRO__(0xFD80, ## __VA_ARGS__), \ 882 885 MACRO__(0xFD81, ## __VA_ARGS__) 883 886