drm/msm/dpu: split irq_control into irq_enable and _disable

+27 -9

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

··· 721 721 } 722 722 } 723 723 724 - static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) 724 + static void _dpu_encoder_irq_enable(struct drm_encoder *drm_enc) 725 725 { 726 726 struct dpu_encoder_virt *dpu_enc; 727 727 int i; ··· 733 733 734 734 dpu_enc = to_dpu_encoder_virt(drm_enc); 735 735 736 - DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); 736 + DPU_DEBUG_ENC(dpu_enc, "\n"); 737 737 for (i = 0; i < dpu_enc->num_phys_encs; i++) { 738 738 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 739 739 740 - if (phys->ops.irq_control) 741 - phys->ops.irq_control(phys, enable); 740 + phys->ops.irq_enable(phys); 741 + } 742 + } 743 + 744 + static void _dpu_encoder_irq_disable(struct drm_encoder *drm_enc) 745 + { 746 + struct dpu_encoder_virt *dpu_enc; 747 + int i; 748 + 749 + if (!drm_enc) { 750 + DPU_ERROR("invalid encoder\n"); 751 + return; 742 752 } 743 753 754 + dpu_enc = to_dpu_encoder_virt(drm_enc); 755 + 756 + DPU_DEBUG_ENC(dpu_enc, "\n"); 757 + for (i = 0; i < dpu_enc->num_phys_encs; i++) { 758 + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; 759 + 760 + phys->ops.irq_disable(phys); 761 + } 744 762 } 745 763 746 764 static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, ··· 784 766 pm_runtime_get_sync(&dpu_kms->pdev->dev); 785 767 786 768 /* enable all the irq */ 787 - _dpu_encoder_irq_control(drm_enc, true); 769 + _dpu_encoder_irq_enable(drm_enc); 788 770 789 771 } else { 790 772 /* disable all the irq */ 791 - _dpu_encoder_irq_control(drm_enc, false); 773 + _dpu_encoder_irq_disable(drm_enc); 792 774 793 775 /* disable DPU core clks */ 794 776 pm_runtime_put_sync(&dpu_kms->pdev->dev); ··· 849 831 } 850 832 851 833 if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) 852 - _dpu_encoder_irq_control(drm_enc, true); 834 + _dpu_encoder_irq_enable(drm_enc); 853 835 else 854 836 _dpu_encoder_resource_control_helper(drm_enc, true); 855 837 ··· 904 886 905 887 if (is_vid_mode && 906 888 dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { 907 - _dpu_encoder_irq_control(drm_enc, true); 889 + _dpu_encoder_irq_enable(drm_enc); 908 890 } 909 891 /* skip if is already OFF or IDLE, resources are off already */ 910 892 else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || ··· 979 961 } 980 962 981 963 if (is_vid_mode) 982 - _dpu_encoder_irq_control(drm_enc, false); 964 + _dpu_encoder_irq_disable(drm_enc); 983 965 else 984 966 _dpu_encoder_resource_control_helper(drm_enc, false); 985 967

+4 -2

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

··· 85 85 * @handle_post_kickoff: Do any work necessary post-kickoff work 86 86 * @trigger_start: Process start event on physical encoder 87 87 * @needs_single_flush: Whether encoder slaves need to be flushed 88 - * @irq_control: Handler to enable/disable all the encoder IRQs 88 + * @irq_enable: Handler to enable all the encoder IRQs 89 + * @irq_disable: Handler to disable all the encoder IRQs 89 90 * @prepare_idle_pc: phys encoder can update the vsync_enable status 90 91 * on idle power collapse prepare 91 92 * @restore: Restore all the encoder configs. ··· 111 110 void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc); 112 111 void (*trigger_start)(struct dpu_encoder_phys *phys_enc); 113 112 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc); 114 - void (*irq_control)(struct dpu_encoder_phys *phys, bool enable); 113 + void (*irq_enable)(struct dpu_encoder_phys *phys); 114 + void (*irq_disable)(struct dpu_encoder_phys *phys); 115 115 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); 116 116 void (*restore)(struct dpu_encoder_phys *phys); 117 117 int (*get_line_count)(struct dpu_encoder_phys *phys);

+32 -29

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

··· 291 291 return ret; 292 292 } 293 293 294 - static void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc, 295 - bool enable) 294 + static void dpu_encoder_phys_cmd_irq_enable(struct dpu_encoder_phys *phys_enc) 296 295 { 297 - trace_dpu_enc_phys_cmd_irq_ctrl(DRMID(phys_enc->parent), 298 - phys_enc->hw_pp->idx - PINGPONG_0, 299 - enable, phys_enc->vblank_refcount); 296 + trace_dpu_enc_phys_cmd_irq_enable(DRMID(phys_enc->parent), 297 + phys_enc->hw_pp->idx - PINGPONG_0, 298 + phys_enc->vblank_refcount); 300 299 301 - if (enable) { 300 + dpu_core_irq_register_callback(phys_enc->dpu_kms, 301 + phys_enc->irq[INTR_IDX_PINGPONG], 302 + dpu_encoder_phys_cmd_pp_tx_done_irq, 303 + phys_enc); 304 + dpu_core_irq_register_callback(phys_enc->dpu_kms, 305 + phys_enc->irq[INTR_IDX_UNDERRUN], 306 + dpu_encoder_phys_cmd_underrun_irq, 307 + phys_enc); 308 + dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true); 309 + 310 + if (dpu_encoder_phys_cmd_is_master(phys_enc)) 302 311 dpu_core_irq_register_callback(phys_enc->dpu_kms, 303 - phys_enc->irq[INTR_IDX_PINGPONG], 304 - dpu_encoder_phys_cmd_pp_tx_done_irq, 305 - phys_enc); 306 - dpu_core_irq_register_callback(phys_enc->dpu_kms, 307 - phys_enc->irq[INTR_IDX_UNDERRUN], 308 - dpu_encoder_phys_cmd_underrun_irq, 309 - phys_enc); 310 - dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true); 312 + phys_enc->irq[INTR_IDX_CTL_START], 313 + dpu_encoder_phys_cmd_ctl_start_irq, 314 + phys_enc); 315 + } 311 316 312 - if (dpu_encoder_phys_cmd_is_master(phys_enc)) 313 - dpu_core_irq_register_callback(phys_enc->dpu_kms, 314 - phys_enc->irq[INTR_IDX_CTL_START], 315 - dpu_encoder_phys_cmd_ctl_start_irq, 316 - phys_enc); 317 - } else { 318 - if (dpu_encoder_phys_cmd_is_master(phys_enc)) 319 - dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 320 - phys_enc->irq[INTR_IDX_CTL_START]); 317 + static void dpu_encoder_phys_cmd_irq_disable(struct dpu_encoder_phys *phys_enc) 318 + { 319 + trace_dpu_enc_phys_cmd_irq_disable(DRMID(phys_enc->parent), 320 + phys_enc->hw_pp->idx - PINGPONG_0, 321 + phys_enc->vblank_refcount); 321 322 323 + if (dpu_encoder_phys_cmd_is_master(phys_enc)) 322 324 dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 323 - phys_enc->irq[INTR_IDX_UNDERRUN]); 324 - dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false); 325 - dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 326 - phys_enc->irq[INTR_IDX_PINGPONG]); 327 - } 325 + phys_enc->irq[INTR_IDX_CTL_START]); 326 + 327 + dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_UNDERRUN]); 328 + dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false); 329 + dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_PINGPONG]); 328 330 } 329 331 330 332 static void dpu_encoder_phys_cmd_tearcheck_config( ··· 715 713 ops->wait_for_tx_complete = dpu_encoder_phys_cmd_wait_for_tx_complete; 716 714 ops->trigger_start = dpu_encoder_phys_cmd_trigger_start; 717 715 ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush; 718 - ops->irq_control = dpu_encoder_phys_cmd_irq_control; 716 + ops->irq_enable = dpu_encoder_phys_cmd_irq_enable; 717 + ops->irq_disable = dpu_encoder_phys_cmd_irq_disable; 719 718 ops->restore = dpu_encoder_phys_cmd_enable_helper; 720 719 ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc; 721 720 ops->handle_post_kickoff = dpu_encoder_phys_cmd_handle_post_kickoff;

+24 -20

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

··· 616 616 } 617 617 } 618 618 619 - static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, 620 - bool enable) 619 + static void dpu_encoder_phys_vid_irq_enable(struct dpu_encoder_phys *phys_enc) 621 620 { 622 621 int ret; 623 622 624 - trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent), 625 - phys_enc->hw_intf->idx - INTF_0, 626 - enable, 627 - phys_enc->vblank_refcount); 623 + trace_dpu_enc_phys_vid_irq_enable(DRMID(phys_enc->parent), 624 + phys_enc->hw_intf->idx - INTF_0, 625 + phys_enc->vblank_refcount); 628 626 629 - if (enable) { 630 - ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); 631 - if (WARN_ON(ret)) 632 - return; 627 + ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); 628 + if (WARN_ON(ret)) 629 + return; 633 630 634 - dpu_core_irq_register_callback(phys_enc->dpu_kms, 635 - phys_enc->irq[INTR_IDX_UNDERRUN], 636 - dpu_encoder_phys_vid_underrun_irq, 637 - phys_enc); 638 - } else { 639 - dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false); 640 - dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 641 - phys_enc->irq[INTR_IDX_UNDERRUN]); 642 - } 631 + dpu_core_irq_register_callback(phys_enc->dpu_kms, 632 + phys_enc->irq[INTR_IDX_UNDERRUN], 633 + dpu_encoder_phys_vid_underrun_irq, 634 + phys_enc); 635 + } 636 + 637 + static void dpu_encoder_phys_vid_irq_disable(struct dpu_encoder_phys *phys_enc) 638 + { 639 + trace_dpu_enc_phys_vid_irq_disable(DRMID(phys_enc->parent), 640 + phys_enc->hw_intf->idx - INTF_0, 641 + phys_enc->vblank_refcount); 642 + 643 + dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false); 644 + dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 645 + phys_enc->irq[INTR_IDX_UNDERRUN]); 643 646 } 644 647 645 648 static int dpu_encoder_phys_vid_get_line_count( ··· 693 690 ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq; 694 691 ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done; 695 692 ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_tx_complete; 696 - ops->irq_control = dpu_encoder_phys_vid_irq_control; 693 + ops->irq_enable = dpu_encoder_phys_vid_irq_enable; 694 + ops->irq_disable = dpu_encoder_phys_vid_irq_disable; 697 695 ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff; 698 696 ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff; 699 697 ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;

+20 -9

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c

··· 511 511 } 512 512 513 513 /** 514 - * dpu_encoder_phys_wb_irq_ctrl - irq control of WB 514 + * dpu_encoder_phys_wb_irq_enable - irq control of WB 515 515 * @phys: Pointer to physical encoder 516 - * @enable: indicates enable or disable interrupts 517 516 */ 518 - static void dpu_encoder_phys_wb_irq_ctrl( 519 - struct dpu_encoder_phys *phys, bool enable) 517 + static void dpu_encoder_phys_wb_irq_enable(struct dpu_encoder_phys *phys) 520 518 { 521 519 522 520 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys); 523 521 524 - if (enable && atomic_inc_return(&wb_enc->wbirq_refcount) == 1) 522 + if (atomic_inc_return(&wb_enc->wbirq_refcount) == 1) 525 523 dpu_core_irq_register_callback(phys->dpu_kms, 526 - phys->irq[INTR_IDX_WB_DONE], dpu_encoder_phys_wb_done_irq, phys); 527 - else if (!enable && 528 - atomic_dec_return(&wb_enc->wbirq_refcount) == 0) 524 + phys->irq[INTR_IDX_WB_DONE], 525 + dpu_encoder_phys_wb_done_irq, 526 + phys); 527 + } 528 + 529 + /** 530 + * dpu_encoder_phys_wb_irq_disable - irq control of WB 531 + * @phys: Pointer to physical encoder 532 + */ 533 + static void dpu_encoder_phys_wb_irq_disable(struct dpu_encoder_phys *phys) 534 + { 535 + 536 + struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys); 537 + 538 + if (atomic_dec_return(&wb_enc->wbirq_refcount) == 0) 529 539 dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]); 530 540 } 531 541 ··· 795 785 ops->trigger_start = dpu_encoder_helper_trigger_start; 796 786 ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job; 797 787 ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job; 798 - ops->irq_control = dpu_encoder_phys_wb_irq_ctrl; 788 + ops->irq_enable = dpu_encoder_phys_wb_irq_enable; 789 + ops->irq_disable = dpu_encoder_phys_wb_irq_disable; 799 790 ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit; 800 791 801 792 }

+48 -14

drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h

··· 514 514 __entry->expected_time, __entry->atomic_cnt) 515 515 ); 516 516 517 - TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl, 518 - TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable, 517 + TRACE_EVENT(dpu_enc_phys_cmd_irq_enable, 518 + TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, 519 519 int refcnt), 520 - TP_ARGS(drm_id, pp, enable, refcnt), 520 + TP_ARGS(drm_id, pp, refcnt), 521 521 TP_STRUCT__entry( 522 522 __field( uint32_t, drm_id ) 523 523 __field( enum dpu_pingpong, pp ) 524 - __field( bool, enable ) 525 524 __field( int, refcnt ) 526 525 ), 527 526 TP_fast_assign( 528 527 __entry->drm_id = drm_id; 529 528 __entry->pp = pp; 530 - __entry->enable = enable; 531 529 __entry->refcnt = refcnt; 532 530 ), 533 - TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id, 534 - __entry->pp, __entry->enable ? "true" : "false", 531 + TP_printk("id=%u, pp=%d, refcnt=%d", __entry->drm_id, 532 + __entry->pp, 533 + __entry->refcnt) 534 + ); 535 + 536 + TRACE_EVENT(dpu_enc_phys_cmd_irq_disable, 537 + TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, 538 + int refcnt), 539 + TP_ARGS(drm_id, pp, refcnt), 540 + TP_STRUCT__entry( 541 + __field( uint32_t, drm_id ) 542 + __field( enum dpu_pingpong, pp ) 543 + __field( int, refcnt ) 544 + ), 545 + TP_fast_assign( 546 + __entry->drm_id = drm_id; 547 + __entry->pp = pp; 548 + __entry->refcnt = refcnt; 549 + ), 550 + TP_printk("id=%u, pp=%d, refcnt=%d", __entry->drm_id, 551 + __entry->pp, 535 552 __entry->refcnt) 536 553 ); 537 554 ··· 609 592 TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx) 610 593 ); 611 594 612 - TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl, 613 - TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable, 595 + TRACE_EVENT(dpu_enc_phys_vid_irq_enable, 596 + TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, 614 597 int refcnt), 615 - TP_ARGS(drm_id, intf_idx, enable, refcnt), 598 + TP_ARGS(drm_id, intf_idx, refcnt), 616 599 TP_STRUCT__entry( 617 600 __field( uint32_t, drm_id ) 618 601 __field( enum dpu_intf, intf_idx ) 619 - __field( bool, enable ) 620 602 __field( int, refcnt ) 621 603 ), 622 604 TP_fast_assign( 623 605 __entry->drm_id = drm_id; 624 606 __entry->intf_idx = intf_idx; 625 - __entry->enable = enable; 626 607 __entry->refcnt = refcnt; 627 608 ), 628 - TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id, 629 - __entry->intf_idx, __entry->enable ? "true" : "false", 609 + TP_printk("id=%u, intf_idx=%d refcnt=%d", __entry->drm_id, 610 + __entry->intf_idx, 611 + __entry->drm_id) 612 + ); 613 + 614 + TRACE_EVENT(dpu_enc_phys_vid_irq_disable, 615 + TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, 616 + int refcnt), 617 + TP_ARGS(drm_id, intf_idx, refcnt), 618 + TP_STRUCT__entry( 619 + __field( uint32_t, drm_id ) 620 + __field( enum dpu_intf, intf_idx ) 621 + __field( int, refcnt ) 622 + ), 623 + TP_fast_assign( 624 + __entry->drm_id = drm_id; 625 + __entry->intf_idx = intf_idx; 626 + __entry->refcnt = refcnt; 627 + ), 628 + TP_printk("id=%u, intf_idx=%d refcnt=%d", __entry->drm_id, 629 + __entry->intf_idx, 630 630 __entry->drm_id) 631 631 ); 632 632

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