tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amd/display: Correct DSC padding accounting

[WHY]
- After the addition of all OVT patches, DSC padding was being accounted
for multiple times, effectively doubling the padding
- This caused compliance failures or corruption

[HOW]
- Add padding to DSC pic width when required by HW, and do not re-add
when calculating reg values
- Do not add padding when computing PPS values, and instead track padding
separately to add when calculating slice width values

Reviewed-by: Chris Park <chris.park@amd.com>
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Relja Vojvodic <rvojvodi@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Relja Vojvodic and committed by
Alex Deucher c7062be3 a574f53e

+8 -7
+1 -1
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
··· 108 108 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 109 109 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 110 110 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 111 - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 111 + dsc_cfg.dsc_padding = 0; 112 112 113 113 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 114 114 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
+1 -1
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
··· 1061 1061 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 1062 1062 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 1063 1063 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 1064 - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 1064 + dsc_cfg.dsc_padding = 0; 1065 1065 1066 1066 if (should_use_dto_dscclk) 1067 1067 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);
+1 -1
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
··· 364 364 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 365 365 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); 366 366 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 367 - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 367 + dsc_cfg.dsc_padding = 0; 368 368 369 369 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); 370 370 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
+3 -3
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
··· 1660 1660 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) 1661 1661 continue; 1662 1662 1663 - dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left 1664 - + stream->timing.h_border_right) / opp_cnt; 1663 + dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding 1664 + + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; 1665 1665 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top 1666 1666 + stream->timing.v_border_bottom; 1667 1667 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; ··· 1669 1669 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 1670 1670 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 1671 1671 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 1672 - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; 1672 + dsc_cfg.dsc_padding = 0; 1673 1673 1674 1674 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) 1675 1675 return false;